Merge tag 'amlogic-arm-dt-for-v5.15' of git://git.kernel.org/pub/scm/linux/kernel...

[linux-2.6-microblaze.git] / arch / arm64 / boot / dts / ti / k3-am642-evm.dts

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index dad0efa..24ce494 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -5,6 +5,8 @@
 
 /dts-v1/;
 
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/ti-serdes.h>
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/net/ti-dp83867.h>
@@ -36,6 +38,60 @@
                        alignment = <0x1000>;
                        no-map;
                };
+
+               main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa0000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa0100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa1000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa1100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa2000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa2100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa3000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa3100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               rtos_ipc_memory_region: ipc-memories@a5000000 {
+                       reg = <0x00 0xa5000000 0x00 0x00800000>;
+                       alignment = <0x1000>;
+                       no-map;
+               };
        };
 
        evm_12v0: fixedregulator-evm12v0 {
@@ -232,6 +288,12 @@
                        AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
                >;
        };
+
+       main_ecap0_pins_default: main-ecap0-pins-default {
+               pinctrl-single,pins = <
+                       AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
+               >;
+       };
 };
 
 &main_uart0 {
@@ -334,7 +396,7 @@
 &main_spi0 {
        pinctrl-names = "default";
        pinctrl-0 = <&main_spi0_pins_default>;
-       ti,pindir-d0-out-d1-in = <1>;
+       ti,pindir-d0-out-d1-in;
        eeprom@0 {
                compatible = "microchip,93lc46b";
                reg = <0>;
@@ -466,3 +528,105 @@
 &mailbox0_cluster7 {
        status = "disabled";
 };
+
+&main_r5fss0_core0 {
+       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+       memory-region = <&main_r5fss0_core0_dma_memory_region>,
+                       <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+       memory-region = <&main_r5fss0_core1_dma_memory_region>,
+                       <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+       mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+       memory-region = <&main_r5fss1_core0_dma_memory_region>,
+                       <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+       mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+       memory-region = <&main_r5fss1_core1_dma_memory_region>,
+                       <&main_r5fss1_core1_memory_region>;
+};
+
+&serdes_ln_ctrl {
+       idle-states = <AM64_SERDES0_LANE0_PCIE0>;
+};
+
+&serdes0 {
+       serdes0_pcie_link: phy@0 {
+               reg = <0>;
+               cdns,num-lanes = <1>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
+               resets = <&serdes_wiz0 1>;
+       };
+};
+
+&pcie0_rc {
+       reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
+       phys = <&serdes0_pcie_link>;
+       phy-names = "pcie-phy";
+       num-lanes = <1>;
+};
+
+&pcie0_ep {
+       phys = <&serdes0_pcie_link>;
+       phy-names = "pcie-phy";
+       num-lanes = <1>;
+       status = "disabled";
+};
+
+&ecap0 {
+       /* PWM is available on Pin 1 of header J12 */
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_ecap0_pins_default>;
+};
+
+&ecap1 {
+       status = "disabled";
+};
+
+&ecap2 {
+       status = "disabled";
+};
+
+&epwm0 {
+       status = "disabled";
+};
+
+&epwm1 {
+       status = "disabled";
+};
+
+&epwm2 {
+       status = "disabled";
+};
+
+&epwm3 {
+       status = "disabled";
+};
+
+&epwm4 {
+       status = "disabled";
+};
+
+&epwm5 {
+       status = "disabled";
+};
+
+&epwm6 {
+       status = "disabled";
+};
+
+&epwm7 {
+       status = "disabled";
+};
+
+&epwm8 {
+       status = "disabled";
+};