arm64: tegra: Enable SMMU support for PCIe on Tegra194

[linux-2.6-microblaze.git] / arch / arm64 / boot / dts / nvidia / tegra194.dtsi

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 9449156..5ba7a45 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -62,6 +62,7 @@
                        interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
                                        <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
                        interconnect-names = "dma-mem", "write";
+                       iommus = <&smmu TEGRA194_SID_EQOS>;
                        status = "disabled";
 
                        snps,write-requests = <1>;
@@ -733,6 +734,7 @@
                        interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
                                        <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
                        interconnect-names = "dma-mem", "write";
+                       iommus = <&smmu TEGRA194_SID_SDMMC1>;
                        nvidia,pad-autocal-pull-up-offset-3v3-timeout =
                                                                        <0x07>;
                        nvidia,pad-autocal-pull-down-offset-3v3-timeout =
@@ -759,6 +761,7 @@
                        interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
                                        <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
                        interconnect-names = "dma-mem", "write";
+                       iommus = <&smmu TEGRA194_SID_SDMMC3>;
                        nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
                        nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
                        nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
@@ -790,6 +793,7 @@
                        interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
                                        <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
                        interconnect-names = "dma-mem", "write";
+                       iommus = <&smmu TEGRA194_SID_SDMMC4>;
                        nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
                        nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
                        nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
@@ -821,6 +825,7 @@
                        interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
                                        <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
                        interconnect-names = "dma-mem", "write";
+                       iommus = <&smmu TEGRA194_SID_HDA>;
                        status = "disabled";
                };
 
@@ -943,6 +948,10 @@
                                 <&bpmp TEGRA194_CLK_XUSB_SS>,
                                 <&bpmp TEGRA194_CLK_XUSB_FS>;
                        clock-names = "dev", "ss", "ss_src", "fs_src";
+                       interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>,
+                                       <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>;
+                       interconnect-names = "dma-mem", "write";
+                       iommus = <&smmu TEGRA194_SID_XUSB_DEV>;
                        power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
                                        <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
                        power-domain-names = "dev", "ss";
@@ -972,6 +981,10 @@
                                      "xusb_ss", "xusb_ss_src", "xusb_hs_src",
                                      "xusb_fs_src", "pll_u_480m", "clk_m",
                                      "pll_e";
+                       interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>,
+                                       <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>;
+                       interconnect-names = "dma-mem", "write";
+                       iommus = <&smmu TEGRA194_SID_XUSB_HOST>;
 
                        power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
                                        <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
@@ -1300,6 +1313,84 @@
                        interrupt-controller;
                };
 
+               smmu: iommu@12000000 {
+                       compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
+                       reg = <0x12000000 0x800000>,
+                             <0x11000000 0x800000>;
+                       interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+                       stream-match-mask = <0x7f80>;
+                       #global-interrupts = <2>;
+                       #iommu-cells = <1>;
+
+                       nvidia,memory-controller = <&mc>;
+                       status = "okay";
+               };
+
                host1x@13e00000 {
                        compatible = "nvidia,tegra194-host1x";
                        reg = <0x13e00000 0x10000>,
@@ -1319,6 +1410,7 @@
                        ranges = <0x15000000 0x15000000 0x01000000>;
                        interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
                        interconnect-names = "dma-mem";
+                       iommus = <&smmu TEGRA194_SID_HOST1X>;
 
                        display-hub@15200000 {
                                compatible = "nvidia,tegra194-display";
@@ -1430,6 +1522,7 @@
                                interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
                                                <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
                                interconnect-names = "dma-mem", "write";
+                               iommus = <&smmu TEGRA194_SID_VIC>;
                        };
 
                        dpaux0: dpaux@155c0000 {
@@ -1747,7 +1840,11 @@
 
                interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
                                <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
-               interconnect-names = "read", "write";
+               interconnect-names = "dma-mem", "write";
+               iommus = <&smmu TEGRA194_SID_PCIE1>;
+               iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
+               iommu-map-mask = <0x0>;
+               dma-coherent;
        };
 
        pcie@14120000 {
@@ -1797,7 +1894,11 @@
 
                interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
                                <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
-               interconnect-names = "read", "write";
+               interconnect-names = "dma-mem", "write";
+               iommus = <&smmu TEGRA194_SID_PCIE2>;
+               iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
+               iommu-map-mask = <0x0>;
+               dma-coherent;
        };
 
        pcie@14140000 {
@@ -1847,7 +1948,11 @@
 
                interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
                                <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
-               interconnect-names = "read", "write";
+               interconnect-names = "dma-mem", "write";
+               iommus = <&smmu TEGRA194_SID_PCIE3>;
+               iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
+               iommu-map-mask = <0x0>;
+               dma-coherent;
        };
 
        pcie@14160000 {
@@ -1897,7 +2002,11 @@
 
                interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
                                <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
-               interconnect-names = "read", "write";
+               interconnect-names = "dma-mem", "write";
+               iommus = <&smmu TEGRA194_SID_PCIE4>;
+               iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
+               iommu-map-mask = <0x0>;
+               dma-coherent;
        };
 
        pcie@14180000 {
@@ -1947,7 +2056,11 @@
 
                interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
                                <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
-               interconnect-names = "read", "write";
+               interconnect-names = "dma-mem", "write";
+               iommus = <&smmu TEGRA194_SID_PCIE0>;
+               iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
+               iommu-map-mask = <0x0>;
+               dma-coherent;
        };
 
        pcie@141a0000 {
@@ -2001,7 +2114,11 @@
 
                interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
                                <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
-               interconnect-names = "read", "write";
+               interconnect-names = "dma-mem", "write";
+               iommus = <&smmu TEGRA194_SID_PCIE5>;
+               iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
+               iommu-map-mask = <0x0>;
+               dma-coherent;
        };
 
        pcie_ep@14160000 {
@@ -2034,6 +2151,14 @@
                nvidia,aspm-cmrt-us = <60>;
                nvidia,aspm-pwr-on-t-us = <20>;
                nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+               interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
+                               <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
+               interconnect-names = "dma-mem", "write";
+               iommus = <&smmu TEGRA194_SID_PCIE4>;
+               iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
+               iommu-map-mask = <0x0>;
+               dma-coherent;
        };
 
        pcie_ep@14180000 {
@@ -2066,6 +2191,14 @@
                nvidia,aspm-cmrt-us = <60>;
                nvidia,aspm-pwr-on-t-us = <20>;
                nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+               interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
+                               <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
+               interconnect-names = "dma-mem", "write";
+               iommus = <&smmu TEGRA194_SID_PCIE0>;
+               iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
+               iommu-map-mask = <0x0>;
+               dma-coherent;
        };
 
        pcie_ep@141a0000 {
@@ -2101,6 +2234,14 @@
                nvidia,aspm-cmrt-us = <60>;
                nvidia,aspm-pwr-on-t-us = <20>;
                nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+               interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
+                               <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
+               interconnect-names = "dma-mem", "write";
+               iommus = <&smmu TEGRA194_SID_PCIE5>;
+               iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
+               iommu-map-mask = <0x0>;
+               dma-coherent;
        };
 
        sram@40000000 {
@@ -2136,6 +2277,7 @@
                                <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
                                <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
                interconnect-names = "read", "write", "dma-mem", "dma-write";
+               iommus = <&smmu TEGRA194_SID_BPMP>;
 
                bpmp_i2c: i2c {
                        compatible = "nvidia,tegra186-bpmp-i2c";
@@ -2345,6 +2487,20 @@
                };
        };
 
+       pmu {
+               compatible = "arm,armv8-pmuv3";
+               interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
+                                     &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>;
+       };
+
        psci {
                compatible = "arm,psci-1.0";
                status = "okay";
@@ -2369,6 +2525,11 @@
                 * for 8x and 11.025x sample rate streams.
                 */
                assigned-clock-rates = <258000000>;
+
+               interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>,
+                               <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>;
+               interconnect-names = "dma-mem", "write";
+               iommus = <&smmu TEGRA194_SID_APE>;
        };
 
        tcu: tcu {