Merge tag 'gvt-fixes-2021-08-10' of https://github.com/intel/gvt-linux into drm-intel...

[linux-2.6-microblaze.git] / arch / arm64 / boot / dts / mediatek / mt8167.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
index 1c5639e..9029051 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
@@ -7,6 +7,7 @@
 
 #include <dt-bindings/clock/mt8167-clk.h>
 #include <dt-bindings/memory/mt8167-larb-port.h>
+#include <dt-bindings/power/mt8167-power.h>
 
 #include "mt8167-pinfunc.h"
 
@@ -34,6 +35,73 @@
                        #clock-cells = <1>;
                };
 
+               scpsys: syscon@10006000 {
+                       compatible = "syscon", "simple-mfd";
+                       reg = <0 0x10006000 0 0x1000>;
+                       #power-domain-cells = <1>;
+
+                       spm: power-controller {
+                               compatible = "mediatek,mt8167-power-controller";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               #power-domain-cells = <1>;
+
+                               /* power domains of the SoC */
+                               power-domain@MT8167_POWER_DOMAIN_MM {
+                                       reg = <MT8167_POWER_DOMAIN_MM>;
+                                       clocks = <&topckgen CLK_TOP_SMI_MM>;
+                                       clock-names = "mm";
+                                       #power-domain-cells = <0>;
+                                       mediatek,infracfg = <&infracfg>;
+                               };
+
+                               power-domain@MT8167_POWER_DOMAIN_VDEC {
+                                       reg = <MT8167_POWER_DOMAIN_VDEC>;
+                                       clocks = <&topckgen CLK_TOP_SMI_MM>,
+                                                <&topckgen CLK_TOP_RG_VDEC>;
+                                       clock-names = "mm", "vdec";
+                                       #power-domain-cells = <0>;
+                               };
+
+                               power-domain@MT8167_POWER_DOMAIN_ISP {
+                                       reg = <MT8167_POWER_DOMAIN_ISP>;
+                                       clocks = <&topckgen CLK_TOP_SMI_MM>;
+                                       clock-names = "mm";
+                                       #power-domain-cells = <0>;
+                               };
+
+                               power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {
+                                       reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>;
+                                       clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
+                                                <&topckgen CLK_TOP_RG_SLOW_MFG>;
+                                       clock-names = "axi_mfg", "mfg";
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       #power-domain-cells = <1>;
+                                       mediatek,infracfg = <&infracfg>;
+
+                                       power-domain@MT8167_POWER_DOMAIN_MFG_2D {
+                                               reg = <MT8167_POWER_DOMAIN_MFG_2D>;
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+                                               #power-domain-cells = <1>;
+
+                                               power-domain@MT8167_POWER_DOMAIN_MFG {
+                                                       reg = <MT8167_POWER_DOMAIN_MFG>;
+                                                       #power-domain-cells = <0>;
+                                                       mediatek,infracfg = <&infracfg>;
+                                               };
+                                       };
+                               };
+
+                               power-domain@MT8167_POWER_DOMAIN_CONN {
+                                       reg = <MT8167_POWER_DOMAIN_CONN>;
+                                       #power-domain-cells = <0>;
+                                       mediatek,infracfg = <&infracfg>;
+                               };
+                       };
+               };
+
                imgsys: syscon@15000000 {
                        compatible = "mediatek,mt8167-imgsys", "syscon";
                        reg = <0 0x15000000 0 0x1000>;
@@ -57,5 +125,58 @@
                        #interrupt-cells = <2>;
                        interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
                };
+
+               mmsys: mmsys@14000000 {
+                       compatible = "mediatek,mt8167-mmsys", "syscon";
+                       reg = <0 0x14000000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               smi_common: smi@14017000 {
+                       compatible = "mediatek,mt8167-smi-common";
+                       reg = <0 0x14017000 0 0x1000>;
+                       clocks = <&mmsys CLK_MM_SMI_COMMON>,
+                                <&mmsys CLK_MM_SMI_COMMON>;
+                       clock-names = "apb", "smi";
+                       power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+               };
+
+               larb0: larb@14016000 {
+                       compatible = "mediatek,mt8167-smi-larb";
+                       reg = <0 0x14016000 0 0x1000>;
+                       mediatek,smi = <&smi_common>;
+                       clocks = <&mmsys CLK_MM_SMI_LARB0>,
+                                <&mmsys CLK_MM_SMI_LARB0>;
+                       clock-names = "apb", "smi";
+                       power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+               };
+
+               larb1: larb@15001000 {
+                       compatible = "mediatek,mt8167-smi-larb";
+                       reg = <0 0x15001000 0 0x1000>;
+                       mediatek,smi = <&smi_common>;
+                       clocks = <&imgsys CLK_IMG_LARB1_SMI>,
+                                <&imgsys CLK_IMG_LARB1_SMI>;
+                       clock-names = "apb", "smi";
+                       power-domains = <&spm MT8167_POWER_DOMAIN_ISP>;
+               };
+
+               larb2: larb@16010000 {
+                       compatible = "mediatek,mt8167-smi-larb";
+                       reg = <0 0x16010000 0 0x1000>;
+                       mediatek,smi = <&smi_common>;
+                       clocks = <&vdecsys CLK_VDEC_CKEN>,
+                                <&vdecsys CLK_VDEC_LARB1_CKEN>;
+                       clock-names = "apb", "smi";
+                       power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
+               };
+
+               iommu: m4u@10203000 {
+                       compatible = "mediatek,mt8167-m4u";
+                       reg = <0 0x10203000 0 0x1000>;
+                       mediatek,larbs = <&larb0 &larb1 &larb2>;
+                       interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
+                       #iommu-cells = <1>;
+               };
        };
 };