Merge tag 'amlogic-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman...

[linux-2.6-microblaze.git] / arch / arm64 / boot / dts / freescale / imx8mq-phanbell.dts

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
index 77ab568..a3b9d61 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "imx8mq.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
        model = "Google i.MX8MQ Phanbell";
@@ -125,7 +126,7 @@
                clocks = <&pmic_osc>;
                clock-output-names = "pmic_clk";
                interrupt-parent = <&gpio1>;
-               interrupts = <3 GPIO_ACTIVE_LOW>;
+               interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 
                regulators {
                        buck1: BUCK1 {
@@ -262,9 +263,6 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_fec1>;
        phy-mode = "rgmii-id";
-       phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
-       phy-reset-duration = <10>;
-       phy-reset-post-delay = <50>;
        phy-handle = <&ethphy0>;
        fsl,magic-packet;
        status = "okay";
@@ -275,6 +273,9 @@
                ethphy0: ethernet-phy@0 {
                        compatible = "ethernet-phy-ieee802.3-c22";
                        reg = <0>;
+                       reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+                       reset-assert-us = <10000>;
+                       reset-deassert-us = <50000>;
                };
        };
 };
@@ -365,7 +366,7 @@
                >;
        };
 
-       pinctrl_pmic: pmicirq {
+       pinctrl_pmic: pmicirqgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x41
                >;
@@ -395,7 +396,7 @@
                >;
        };
 
-       pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+       pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x85
                        MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc5
@@ -412,7 +413,7 @@
                >;
        };
 
-       pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+       pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x87
                        MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc7
@@ -429,7 +430,7 @@
                >;
        };
 
-       pinctrl_usdhc2_gpio: usdhc2grpgpio {
+       pinctrl_usdhc2_gpio: usdhc2gpiogrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12        0x41
                        MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
@@ -448,7 +449,7 @@
                >;
        };
 
-       pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+       pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x85
                        MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc5
@@ -460,7 +461,7 @@
                >;
        };
 
-       pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+       pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x87
                        MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc7