Merge tag 'amlogic-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman...

[linux-2.6-microblaze.git] / arch / arm64 / boot / dts / freescale / imx8mq-phanbell.dts

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
index 3f2a489..a3b9d61 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "imx8mq.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
        model = "Google i.MX8MQ Phanbell";
@@ -35,6 +36,16 @@
                gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
                enable-active-high;
        };
+
+       fan: gpio-fan {
+               compatible = "gpio-fan";
+               gpio-fan,speed-map = <0 0 8600 1>;
+               gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
+               #cooling-cells = <2>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_gpio_fan>;
+               status = "okay";
+       };
 };
 
 &A53_0 {
@@ -53,6 +64,53 @@
        cpu-supply = <&buck2>;
 };
 
+&cpu_thermal {
+       trips {
+               cpu_alert0: trip0 {
+                       temperature = <75000>;
+                       hysteresis = <2000>;
+                       type = "passive";
+               };
+
+               cpu_alert1: trip1 {
+                       temperature = <80000>;
+                       hysteresis = <2000>;
+                       type = "passive";
+               };
+
+               cpu_crit0: trip3 {
+                       temperature = <90000>;
+                       hysteresis = <2000>;
+                       type = "critical";
+               };
+
+               fan_toggle0: trip4 {
+                       temperature = <65000>;
+                       hysteresis = <10000>;
+                       type = "active";
+               };
+       };
+
+       cooling-maps {
+               map0 {
+                       trip = <&cpu_alert0>;
+                       cooling-device =
+                       <&A53_0 0 1>; /* Exclude highest OPP */
+               };
+
+               map1 {
+                       trip = <&cpu_alert1>;
+                       cooling-device =
+                       <&A53_0 0 2>; /* Exclude two highest OPPs */
+               };
+
+               map4 {
+                       trip = <&fan_toggle0>;
+                       cooling-device = <&fan 0 1>;
+               };
+       };
+};
+
 &i2c1 {
        clock-frequency = <400000>;
        pinctrl-names = "default";
@@ -68,7 +126,7 @@
                clocks = <&pmic_osc>;
                clock-output-names = "pmic_clk";
                interrupt-parent = <&gpio1>;
-               interrupts = <3 GPIO_ACTIVE_LOW>;
+               interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 
                regulators {
                        buck1: BUCK1 {
@@ -201,6 +259,27 @@
        };
 };
 
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec1>;
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethphy0>;
+       fsl,magic-packet;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               ethphy0: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0>;
+                       reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+                       reset-assert-us = <10000>;
+                       reset-deassert-us = <50000>;
+               };
+       };
+};
+
 &uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1>;
@@ -254,6 +333,32 @@
 };
 
 &iomuxc {
+       pinctrl_fec1: fec1grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
+                       MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO               0x23
+                       MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
+                       MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
+                       MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
+                       MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
+                       MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
+                       MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
+                       MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
+                       MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
+                       MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
+                       MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
+                       MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
+                       MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
+                       MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x19
+               >;
+       };
+
+       pinctrl_gpio_fan: gpiofangrp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5                 0x16
+               >;
+       };
+
        pinctrl_i2c1: i2c1grp {
                fsl,pins = <
                        MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL                  0x4000007f
@@ -261,7 +366,7 @@
                >;
        };
 
-       pinctrl_pmic: pmicirq {
+       pinctrl_pmic: pmicirqgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x41
                >;
@@ -291,7 +396,7 @@
                >;
        };
 
-       pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+       pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x85
                        MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc5
@@ -308,7 +413,7 @@
                >;
        };
 
-       pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+       pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x87
                        MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc7
@@ -325,7 +430,7 @@
                >;
        };
 
-       pinctrl_usdhc2_gpio: usdhc2grpgpio {
+       pinctrl_usdhc2_gpio: usdhc2gpiogrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12        0x41
                        MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
@@ -344,7 +449,7 @@
                >;
        };
 
-       pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+       pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x85
                        MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc5
@@ -356,7 +461,7 @@
                >;
        };
 
-       pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+       pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x87
                        MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc7