nvmem-cells = <&imx8mp_uid>;
nvmem-cell-names = "soc_unique_id";
+ etm0: etm@28440000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x28440000 0x10000>;
+ arm,primecell-periphid = <0xbb95d>;
+ cpu = <&A53_0>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm0_out_port: endpoint {
+ remote-endpoint = <&ca_funnel_in_port0>;
+ };
+ };
+ };
+ };
+
+ etm1: etm@28540000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x28540000 0x10000>;
+ arm,primecell-periphid = <0xbb95d>;
+ cpu = <&A53_1>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm1_out_port: endpoint {
+ remote-endpoint = <&ca_funnel_in_port1>;
+ };
+ };
+ };
+ };
+
+ etm2: etm@28640000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x28640000 0x10000>;
+ arm,primecell-periphid = <0xbb95d>;
+ cpu = <&A53_2>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm2_out_port: endpoint {
+ remote-endpoint = <&ca_funnel_in_port2>;
+ };
+ };
+ };
+ };
+
+ etm3: etm@28740000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x28740000 0x10000>;
+ arm,primecell-periphid = <0xbb95d>;
+ cpu = <&A53_3>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm3_out_port: endpoint {
+ remote-endpoint = <&ca_funnel_in_port3>;
+ };
+ };
+ };
+ };
+
+ funnel {
+ /*
+ * non-configurable funnel don't show up on the AMBA
+ * bus. As such no need to add "arm,primecell".
+ */
+ compatible = "arm,coresight-static-funnel";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ca_funnel_in_port0: endpoint {
+ remote-endpoint = <&etm0_out_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ca_funnel_in_port1: endpoint {
+ remote-endpoint = <&etm1_out_port>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ca_funnel_in_port2: endpoint {
+ remote-endpoint = <&etm2_out_port>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ ca_funnel_in_port3: endpoint {
+ remote-endpoint = <&etm3_out_port>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ca_funnel_out_port0: endpoint {
+ remote-endpoint = <&hugo_funnel_in_port0>;
+ };
+ };
+ };
+ };
+
+ funnel@28c03000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x28c03000 0x1000>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hugo_funnel_in_port0: endpoint {
+ remote-endpoint = <&ca_funnel_out_port0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hugo_funnel_in_port1: endpoint {
+ /* M7 input */
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ hugo_funnel_in_port2: endpoint {
+ /* DSP input */
+ };
+ };
+ /* the other input ports are not connect to anything */
+ };
+
+ out-ports {
+ port {
+ hugo_funnel_out_port0: endpoint {
+ remote-endpoint = <&etf_in_port>;
+ };
+ };
+ };
+ };
+
+ etf@28c04000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x28c04000 0x1000>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ etf_in_port: endpoint {
+ remote-endpoint = <&hugo_funnel_out_port0>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etf_out_port: endpoint {
+ remote-endpoint = <&etr_in_port>;
+ };
+ };
+ };
+ };
+
+ etr@28c06000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x28c06000 0x1000>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ etr_in_port: endpoint {
+ remote-endpoint = <&etf_out_port>;
+ };
+ };
+ };
+ };
+
aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30000000 0x400000>;
<&clk IMX8MP_CLK_A53_CORE>,
<&clk IMX8MP_CLK_NOC>,
<&clk IMX8MP_CLK_NOC_IO>,
- <&clk IMX8MP_CLK_GIC>,
- <&clk IMX8MP_CLK_AUDIO_AHB>,
- <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
- <&clk IMX8MP_AUDIO_PLL1>,
- <&clk IMX8MP_AUDIO_PLL2>;
+ <&clk IMX8MP_CLK_GIC>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_ARM_PLL_OUT>,
<&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>,
- <&clk IMX8MP_SYS_PLL2_500M>,
- <&clk IMX8MP_SYS_PLL1_800M>,
- <&clk IMX8MP_SYS_PLL1_800M>;
+ <&clk IMX8MP_SYS_PLL2_500M>;
assigned-clock-rates = <0>, <0>,
<1000000000>,
<800000000>,
- <500000000>,
- <400000000>,
- <800000000>,
- <393216000>,
- <361267200>;
+ <500000000>;
};
src: reset-controller@30390000 {
reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
};
+ pgc_audio: power-domain@5 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
+ clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
+ <&clk IMX8MP_CLK_AUDIO_AXI>;
+ };
+
pgc_gpu2d: power-domain@6 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
};
};
+ aips5: bus@30c00000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x30c00000 0x400000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ spba-bus@30c00000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ reg = <0x30c00000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sai1: sai@30c10000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c10000 0x10000>;
+ #sound-dai-cells = <0>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
+ dma-names = "rx", "tx";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sai2: sai@30c20000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c20000 0x10000>;
+ #sound-dai-cells = <0>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
+ dma-names = "rx", "tx";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sai3: sai@30c30000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c30000 0x10000>;
+ #sound-dai-cells = <0>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
+ dma-names = "rx", "tx";
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sai5: sai@30c50000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c50000 0x10000>;
+ #sound-dai-cells = <0>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
+ dma-names = "rx", "tx";
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sai6: sai@30c60000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c60000 0x10000>;
+ #sound-dai-cells = <0>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
+ dma-names = "rx", "tx";
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sai7: sai@30c80000 {
+ compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
+ reg = <0x30c80000 0x10000>;
+ #sound-dai-cells = <0>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
+ dma-names = "rx", "tx";
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ sdma3: dma-controller@30e00000 {
+ compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
+ reg = <0x30e00000 0x10000>;
+ #dma-cells = <3>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
+ <&clk IMX8MP_CLK_AUDIO_ROOT>;
+ clock-names = "ipg", "ahb";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+ };
+
+ sdma2: dma-controller@30e10000 {
+ compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
+ reg = <0x30e10000 0x10000>;
+ #dma-cells = <3>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>,
+ <&clk IMX8MP_CLK_AUDIO_ROOT>;
+ clock-names = "ipg", "ahb";
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+ };
+
+ audio_blk_ctrl: clock-controller@30e20000 {
+ compatible = "fsl,imx8mp-audio-blk-ctrl";
+ reg = <0x30e20000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
+ <&clk IMX8MP_CLK_SAI1>,
+ <&clk IMX8MP_CLK_SAI2>,
+ <&clk IMX8MP_CLK_SAI3>,
+ <&clk IMX8MP_CLK_SAI5>,
+ <&clk IMX8MP_CLK_SAI6>,
+ <&clk IMX8MP_CLK_SAI7>;
+ clock-names = "ahb",
+ "sai1", "sai2", "sai3",
+ "sai5", "sai6", "sai7";
+ power-domains = <&pgc_audio>;
+ };
+ };
+
noc: interconnect@32700000 {
compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
reg = <0x32700000 0x100000>;
#size-cells = <1>;
ranges;
+ isi_0: isi@32e00000 {
+ compatible = "fsl,imx8mp-isi";
+ reg = <0x32e00000 0x4000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+ clock-names = "axi", "apb";
+ fsl,blk-ctrl = <&media_blk_ctrl>;
+ power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ isi_in_0: endpoint {
+ remote-endpoint = <&mipi_csi_0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ isi_in_1: endpoint {
+ remote-endpoint = <&mipi_csi_1_out>;
+ };
+ };
+ };
+ };
+
+ dewarp: dwe@32e30000 {
+ compatible = "nxp,imx8mp-dw100";
+ reg = <0x32e30000 0x10000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+ clock-names = "axi", "ahb";
+ power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
+ };
+
+ mipi_csi_0: csi@32e40000 {
+ compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
+ reg = <0x32e40000 0x10000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <500000000>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
+ clock-names = "pclk", "wrap", "phy", "axi";
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
+ assigned-clock-rates = <500000000>;
+ power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_csi_0_out: endpoint {
+ remote-endpoint = <&isi_in_0>;
+ };
+ };
+ };
+ };
+
+ mipi_csi_1: csi@32e50000 {
+ compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
+ reg = <0x32e50000 0x10000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <266000000>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
+ clock-names = "pclk", "wrap", "phy", "axi";
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
+ assigned-clock-rates = <266000000>;
+ power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_csi_1_out: endpoint {
+ remote-endpoint = <&isi_in_1>;
+ };
+ };
+ };
+ };
+
mipi_dsi: dsi@32e60000 {
compatible = "fsl,imx8mp-mipi-dsim";
reg = <0x32e60000 0x400>;
projects / linux-2.6-microblaze.git / blobdiff