Merge tag 'socfpga_dts_update_for_v5.18_part2' of git://git.kernel.org/pub/scm/linux...

[linux-2.6-microblaze.git] / arch / arm64 / boot / dts / freescale / imx8mn.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index b8d49d5..99f0f50 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -4,6 +4,8 @@
  */
 
 #include <dt-bindings/clock/imx8mn-clock.h>
+#include <dt-bindings/power/imx8mn-power.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -640,6 +642,53 @@
                                interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
                                #reset-cells = <1>;
                        };
+
+                       gpc: gpc@303a0000 {
+                               compatible = "fsl,imx8mn-gpc";
+                               reg = <0x303a0000 0x10000>;
+                               interrupt-parent = <&gic>;
+                               interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+
+                               pgc {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       pgc_hsiomix: power-domain@0 {
+                                               #power-domain-cells = <0>;
+                                               reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
+                                               clocks = <&clk IMX8MN_CLK_USB_BUS>;
+                                       };
+
+                                       pgc_otg1: power-domain@1 {
+                                               #power-domain-cells = <0>;
+                                               reg = <IMX8MN_POWER_DOMAIN_OTG1>;
+                                               power-domains = <&pgc_hsiomix>;
+                                       };
+
+                                       pgc_gpumix: power-domain@2 {
+                                               #power-domain-cells = <0>;
+                                               reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
+                                               clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
+                                                        <&clk IMX8MN_CLK_GPU_SHADER>,
+                                                        <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
+                                                        <&clk IMX8MN_CLK_GPU_AHB>;
+                                               resets = <&src IMX8MQ_RESET_GPU_RESET>;
+                                       };
+
+                                       pgc_dispmix: power-domain@3 {
+                                               #power-domain-cells = <0>;
+                                               reg = <IMX8MN_POWER_DOMAIN_DISPMIX>;
+                                               clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+                                                        <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+                                       };
+
+                                       pgc_mipi: power-domain@4 {
+                                               #power-domain-cells = <0>;
+                                               reg = <IMX8MN_POWER_DOMAIN_MIPI>;
+                                               power-domains = <&pgc_dispmix>;
+                                       };
+                               };
+                       };
                };
 
                aips2: bus@30400000 {
@@ -989,6 +1038,34 @@
                        #size-cells = <1>;
                        ranges;
 
+                       disp_blk_ctrl: blk-ctrl@32e28000 {
+                               compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
+                               reg = <0x32e28000 0x100>;
+                               power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
+                                               <&pgc_dispmix>, <&pgc_mipi>,
+                                               <&pgc_mipi>;
+                               power-domain-names = "bus", "isi",
+                                                    "lcdif", "mipi-dsi",
+                                                    "mipi-csi";
+                               clocks = <&clk IMX8MN_CLK_DISP_AXI>,
+                                        <&clk IMX8MN_CLK_DISP_APB>,
+                                        <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+                                        <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+                                        <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+                                        <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+                                        <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
+                                        <&clk IMX8MN_CLK_DSI_CORE>,
+                                        <&clk IMX8MN_CLK_DSI_PHY_REF>,
+                                        <&clk IMX8MN_CLK_CSI1_PHY_REF>,
+                                        <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
+                               clock-names = "disp_axi", "disp_apb",
+                                             "disp_axi_root", "disp_apb_root",
+                                             "lcdif-axi", "lcdif-apb", "lcdif-pix",
+                                             "dsi-pclk", "dsi-ref",
+                                             "csi-aclk", "csi-pclk";
+                               #power-domain-cells = <1>;
+                       };
+
                        usbotg1: usb@32e40000 {
                                compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
                                reg = <0x32e40000 0x200>;
@@ -999,6 +1076,7 @@
                                assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
                                phys = <&usbphynop1>;
                                fsl,usbmisc = <&usbmisc1 0>;
+                               power-domains = <&pgc_otg1>;
                                status = "disabled";
                        };
 
@@ -1038,6 +1116,32 @@
                        status = "disabled";
                };
 
+               gpu: gpu@38000000 {
+                       compatible = "vivante,gc";
+                       reg = <0x38000000 0x8000>;
+                       interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk IMX8MN_CLK_GPU_AHB>,
+                               <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
+                               <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
+                               <&clk IMX8MN_CLK_GPU_SHADER>;
+                       clock-names = "reg", "bus", "core", "shader";
+                       assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
+                                         <&clk IMX8MN_CLK_GPU_SHADER>,
+                                         <&clk IMX8MN_CLK_GPU_AXI>,
+                                         <&clk IMX8MN_CLK_GPU_AHB>,
+                                         <&clk IMX8MN_GPU_PLL>;
+                       assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
+                                                 <&clk IMX8MN_GPU_PLL_OUT>,
+                                                 <&clk IMX8MN_SYS_PLL1_800M>,
+                                                 <&clk IMX8MN_SYS_PLL1_800M>;
+                       assigned-clock-rates = <400000000>,
+                                              <400000000>,
+                                              <800000000>,
+                                              <400000000>,
+                                              <1200000000>;
+                       power-domains = <&pgc_gpumix>;
+               };
+
                gic: interrupt-controller@38800000 {
                        compatible = "arm,gic-v3";
                        reg = <0x38800000 0x10000>,