Merge tag 'socfpga_dts_update_for_v5.18_part2' of git://git.kernel.org/pub/scm/linux...

[linux-2.6-microblaze.git] / arch / arm64 / boot / dts / freescale / imx8mm.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index f77f90e..2692f3a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -548,7 +548,7 @@
                        };
 
                        gpr: iomuxc-gpr@30340000 {
-                               compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
+                               compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
                                reg = <0x30340000 0x10000>;
                        };
 
@@ -1211,6 +1211,19 @@
                                reg = <0x32e50200 0x200>;
                        };
 
+                       pcie_phy: pcie-phy@32f00000 {
+                               compatible = "fsl,imx8mm-pcie-phy";
+                               reg = <0x32f00000 0x10000>;
+                               clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+                               clock-names = "ref";
+                               assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+                               assigned-clock-rates = <100000000>;
+                               assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
+                               resets = <&src IMX8MQ_RESET_PCIEPHY>;
+                               reset-names = "pciephy";
+                               #phy-cells = <0>;
+                               status = "disabled";
+                       };
                };
 
                dma_apbh: dma-controller@33000000 {
@@ -1242,6 +1255,37 @@
                        status = "disabled";
                };
 
+               pcie0: pcie@33800000 {
+                       compatible = "fsl,imx8mm-pcie";
+                       reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
+                       reg-names = "dbi", "config";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       bus-range = <0x00 0xff>;
+                       ranges =  <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+                                  0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+                       num-lanes = <1>;
+                       num-viewport = <4>;
+                       interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi";
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+                       fsl,max-link-speed = <2>;
+                       linux,pci-domain = <0>;
+                       power-domains = <&pgc_pcie>;
+                       resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+                                <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+                       reset-names = "apps", "turnoff";
+                       phys = <&pcie_phy>;
+                       phy-names = "pcie-phy";
+                       status = "disabled";
+               };
+
                gpu_3d: gpu@38000000 {
                        compatible = "vivante,gc";
                        reg = <0x38000000 0x8000>;
@@ -1273,6 +1317,22 @@
                        power-domains = <&pgc_gpu>;
                };
 
+               vpu_g1: video-codec@38300000 {
+                       compatible = "nxp,imx8mm-vpu-g1";
+                       reg = <0x38300000 0x10000>;
+                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
+                       power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
+               };
+
+               vpu_g2: video-codec@38310000 {
+                       compatible = "nxp,imx8mq-vpu-g2";
+                       reg = <0x38310000 0x10000>;
+                       interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
+                       power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
+               };
+
                vpu_blk_ctrl: blk-ctrl@38330000 {
                        compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
                        reg = <0x38330000 0x100>;
@@ -1283,6 +1343,12 @@
                                 <&clk IMX8MM_CLK_VPU_G2_ROOT>,
                                 <&clk IMX8MM_CLK_VPU_H1_ROOT>;
                        clock-names = "g1", "g2", "h1";
+                       assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
+                                         <&clk IMX8MM_CLK_VPU_G2>;
+                       assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
+                                                <&clk IMX8MM_VPU_PLL_OUT>;
+                       assigned-clock-rates = <600000000>,
+                                              <600000000>;
                        #power-domain-cells = <1>;
                };