arm64: dts: freescale: Fix SP805 clock-names

[linux-2.6-microblaze.git] / arch / arm64 / boot / dts / freescale / fsl-ls208xa.dtsi

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 41102da..bf72918 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -79,20 +79,62 @@
        };
 
        thermal-zones {
-               cpu_thermal: cpu-thermal {
+               ddr-controller1 {
                        polling-delay-passive = <1000>;
                        polling-delay = <5000>;
+                       thermal-sensors = <&tmu 1>;
 
+                       trips {
+                               ddr-ctrler1-crit {
+                                       temperature = <95000>;
+                                       hysteresis = <2000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               ddr-controller2 {
+                       polling-delay-passive = <1000>;
+                       polling-delay = <5000>;
+                       thermal-sensors = <&tmu 2>;
+
+                       trips {
+                               ddr-ctrler2-crit {
+                                       temperature = <95000>;
+                                       hysteresis = <2000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               ddr-controller3 {
+                       polling-delay-passive = <1000>;
+                       polling-delay = <5000>;
+                       thermal-sensors = <&tmu 3>;
+
+                       trips {
+                               ddr-ctrler3-crit {
+                                       temperature = <95000>;
+                                       hysteresis = <2000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               core-cluster1 {
+                       polling-delay-passive = <1000>;
+                       polling-delay = <5000>;
                        thermal-sensors = <&tmu 4>;
 
                        trips {
-                               cpu_alert: cpu-alert {
-                                       temperature = <75000>;
+                               core_cluster1_alert: core-cluster1-alert {
+                                       temperature = <85000>;
                                        hysteresis = <2000>;
                                        type = "passive";
                                };
-                               cpu_crit: cpu-crit {
-                                       temperature = <85000>;
+
+                               core-cluster1-crit {
+                                       temperature = <95000>;
                                        hysteresis = <2000>;
                                        type = "critical";
                                };
@@ -100,14 +142,95 @@
 
                        cooling-maps {
                                map0 {
-                                       trip = <&cpu_alert>;
+                                       trip = <&core_cluster1_alert>;
                                        cooling-device =
                                                <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                               <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                               };
+                       };
+               };
+
+               core-cluster2 {
+                       polling-delay-passive = <1000>;
+                       polling-delay = <5000>;
+                       thermal-sensors = <&tmu 5>;
+
+                       trips {
+                               core_cluster2_alert: core-cluster2-alert {
+                                       temperature = <85000>;
+                                       hysteresis = <2000>;
+                                       type = "passive";
+                               };
+
+                               core-cluster2-crit {
+                                       temperature = <95000>;
+                                       hysteresis = <2000>;
+                                       type = "critical";
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&core_cluster2_alert>;
+                                       cooling-device =
                                                <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                               <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                               };
+                       };
+               };
+
+               core-cluster3 {
+                       polling-delay-passive = <1000>;
+                       polling-delay = <5000>;
+                       thermal-sensors = <&tmu 6>;
+
+                       trips {
+                               core_cluster3_alert: core-cluster3-alert {
+                                       temperature = <85000>;
+                                       hysteresis = <2000>;
+                                       type = "passive";
+                               };
+
+                               core-cluster3-crit {
+                                       temperature = <95000>;
+                                       hysteresis = <2000>;
+                                       type = "critical";
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&core_cluster3_alert>;
+                                       cooling-device =
                                                <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                               <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                               };
+                       };
+               };
+
+               core-cluster4 {
+                       polling-delay-passive = <1000>;
+                       polling-delay = <5000>;
+                       thermal-sensors = <&tmu 7>;
+
+                       trips {
+                               core_cluster4_alert: core-cluster4-alert {
+                                       temperature = <85000>;
+                                       hysteresis = <2000>;
+                                       type = "passive";
+                               };
+
+                               core-cluster4-crit {
+                                       temperature = <95000>;
+                                       hysteresis = <2000>;
+                                       type = "critical";
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&core_cluster4_alert>;
+                                       cooling-device =
                                                <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
                                                <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                };
@@ -231,56 +354,56 @@
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc000000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster1_core1_watchdog: wdt@c010000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc010000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core0_watchdog: wdt@c100000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc100000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core1_watchdog: wdt@c110000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc110000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster3_core0_watchdog: wdt@c200000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc200000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster3_core1_watchdog: wdt@c210000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc210000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster4_core0_watchdog: wdt@c300000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc300000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster4_core1_watchdog: wdt@c310000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc310000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                crypto: crypto@8000000 {