Merge tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

[linux-2.6-microblaze.git] / arch / arm / plat-omap / counter_32k.c

diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 44ae077..2132c4f 100644 (file)
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -28,19 +28,20 @@
 
 #include <plat/clock.h>
 
+/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
+#define OMAP2_32KSYNCNT_CR_OFF         0x10
+
 /*
  * 32KHz clocksource ... always available, on pretty most chips except
  * OMAP 730 and 1510.  Other timers could be used as clocksources, with
  * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
  * but systems won't necessarily want to spend resources that way.
  */
-static void __iomem *timer_32k_base;
-
-#define OMAP16XX_TIMER_32K_SYNCHRONIZED                0xfffbc410
+static void __iomem *sync32k_cnt_reg;
 
 static u32 notrace omap_32k_read_sched_clock(void)
 {
-       return timer_32k_base ? __raw_readl(timer_32k_base) : 0;
+       return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
 }
 
 /**
@@ -60,7 +61,7 @@ static void omap_read_persistent_clock(struct timespec *ts)
        struct timespec *tsp = &persistent_ts;
 
        last_cycles = cycles;
-       cycles = timer_32k_base ? __raw_readl(timer_32k_base) : 0;
+       cycles = sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
        delta = cycles - last_cycles;
 
        nsecs = clocksource_cyc2ns(delta, persistent_mult, persistent_shift);
@@ -69,55 +70,41 @@ static void omap_read_persistent_clock(struct timespec *ts)
        *ts = *tsp;
 }
 
-int __init omap_init_clocksource_32k(void)
+/**
+ * omap_init_clocksource_32k - setup and register counter 32k as a
+ * kernel clocksource
+ * @pbase: base addr of counter_32k module
+ * @size: size of counter_32k to map
+ *
+ * Returns 0 upon success or negative error code upon failure.
+ *
+ */
+int __init omap_init_clocksource_32k(void __iomem *vbase)
 {
-       static char err[] __initdata = KERN_ERR
-                       "%s: can't register clocksource!\n";
-
-       if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
-               u32 pbase;
-               unsigned long size = SZ_4K;
-               void __iomem *base;
-               struct clk *sync_32k_ick;
-
-               if (cpu_is_omap16xx()) {
-                       pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
-                       size = SZ_1K;
-               } else if (cpu_is_omap2420())
-                       pbase = OMAP2420_32KSYNCT_BASE + 0x10;
-               else if (cpu_is_omap2430())
-                       pbase = OMAP2430_32KSYNCT_BASE + 0x10;
-               else if (cpu_is_omap34xx())
-                       pbase = OMAP3430_32KSYNCT_BASE + 0x10;
-               else if (cpu_is_omap44xx())
-                       pbase = OMAP4430_32KSYNCT_BASE + 0x10;
-               else
-                       return -ENODEV;
-
-               /* For this to work we must have a static mapping in io.c for this area */
-               base = ioremap(pbase, size);
-               if (!base)
-                       return -ENODEV;
-
-               sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
-               if (!IS_ERR(sync_32k_ick))
-                       clk_enable(sync_32k_ick);
-
-               timer_32k_base = base;
-
-               /*
-                * 120000 rough estimate from the calculations in
-                * __clocksource_updatefreq_scale.
-                */
-               clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
-                               32768, NSEC_PER_SEC, 120000);
-
-               if (clocksource_mmio_init(base, "32k_counter", 32768, 250, 32,
-                                         clocksource_mmio_readl_up))
-                       printk(err, "32k_counter");
-
-               setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
-               register_persistent_clock(NULL, omap_read_persistent_clock);
+       int ret;
+
+       /*
+        * 32k sync Counter register offset is at 0x10
+        */
+       sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF;
+
+       /*
+        * 120000 rough estimate from the calculations in
+        * __clocksource_updatefreq_scale.
+        */
+       clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
+                       32768, NSEC_PER_SEC, 120000);
+
+       ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768,
+                               250, 32, clocksource_mmio_readl_up);
+       if (ret) {
+               pr_err("32k_counter: can't register clocksource\n");
+               return ret;
        }
+
+       setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
+       register_persistent_clock(NULL, omap_read_persistent_clock);
+       pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
+
        return 0;
 }