ARM: 8659/1: l2c: allow CA9 optimizations to be disabled

[linux-2.6-microblaze.git] / arch / arm / mm / cache-l2x0.c

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 2290be3..808efbb 100644 (file)
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -57,6 +57,9 @@ static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
 
 struct l2x0_regs l2x0_saved_regs;
 
+static bool l2x0_bresp_disable;
+static bool l2x0_flz_disable;
+
 /*
  * Common code for all cache controllers.
  */
@@ -620,7 +623,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock)
        u32 aux = l2x0_saved_regs.aux_ctrl;
 
        if (rev >= L310_CACHE_ID_RTL_R2P0) {
-               if (cortex_a9) {
+               if (cortex_a9 && !l2x0_bresp_disable) {
                        aux |= L310_AUX_CTRL_EARLY_BRESP;
                        pr_info("L2C-310 enabling early BRESP for Cortex-A9\n");
                } else if (aux & L310_AUX_CTRL_EARLY_BRESP) {
@@ -629,7 +632,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock)
                }
        }
 
-       if (cortex_a9) {
+       if (cortex_a9 && !l2x0_flz_disable) {
                u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL);
                u32 acr = get_auxcr();
 
@@ -1200,6 +1203,12 @@ static void __init l2c310_of_parse(const struct device_node *np,
                *aux_mask &= ~L2C_AUX_CTRL_PARITY_ENABLE;
        }
 
+       if (of_property_read_bool(np, "arm,early-bresp-disable"))
+               l2x0_bresp_disable = true;
+
+       if (of_property_read_bool(np, "arm,full-line-zero-disable"))
+               l2x0_flz_disable = true;
+
        prefetch = l2x0_saved_regs.prefetch_ctrl;
 
        ret = of_property_read_u32(np, "arm,double-linefill", &val);