+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-#include <dt-bindings/clock/tegra30-car.h>
-#include <dt-bindings/gpio/tegra-gpio.h>
-#include <dt-bindings/memory/tegra30-mc.h>
-#include <dt-bindings/pinctrl/pinctrl-tegra.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/soc/tegra-pmc.h>
-#include <dt-bindings/thermal/thermal.h>
-
-#include "tegra30-peripherals-opp.dtsi"
-
-/ {
- compatible = "nvidia,tegra30";
- interrupt-parent = <&lic>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x0>;
- };
-
- pcie@3000 {
- compatible = "nvidia,tegra30-pcie";
- device_type = "pci";
- reg = <0x00003000 0x00000800>, /* PADS registers */
- <0x00003800 0x00000200>, /* AFI registers */
- <0x10000000 0x10000000>; /* configuration space */
- reg-names = "pads", "afi", "cs";
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
- <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
- interrupt-names = "intr", "msi";
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-
- bus-range = <0x00 0xff>;
- #address-cells = <3>;
- #size-cells = <2>;
-
- ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
- <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
- <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
- <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */
- <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
- <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
-
- clocks = <&tegra_car TEGRA30_CLK_PCIE>,
- <&tegra_car TEGRA30_CLK_AFI>,
- <&tegra_car TEGRA30_CLK_PLL_E>,
- <&tegra_car TEGRA30_CLK_CML0>;
- clock-names = "pex", "afi", "pll_e", "cml";
- resets = <&tegra_car 70>,
- <&tegra_car 72>,
- <&tegra_car 74>;
- reset-names = "pex", "afi", "pcie_x";
- power-domains = <&pd_core>;
- operating-points-v2 = <&pcie_dvfs_opp_table>;
- status = "disabled";
-
- pci@1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
- reg = <0x000800 0 0 0 0>;
- bus-range = <0x00 0xff>;
- status = "disabled";
-
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- nvidia,num-lanes = <2>;
- };
-
- pci@2,0 {
- device_type = "pci";
- assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
- reg = <0x001000 0 0 0 0>;
- bus-range = <0x00 0xff>;
- status = "disabled";
-
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- nvidia,num-lanes = <2>;
- };
-
- pci@3,0 {
- device_type = "pci";
- assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
- reg = <0x001800 0 0 0 0>;
- bus-range = <0x00 0xff>;
- status = "disabled";
-
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- nvidia,num-lanes = <2>;
- };
- };
-
- sram@40000000 {
- compatible = "mmio-sram";
- reg = <0x40000000 0x40000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x40000000 0x40000>;
-
- vde_pool: sram@400 {
- reg = <0x400 0x3fc00>;
- pool;
- };
- };
-
- host1x@50000000 {
- compatible = "nvidia,tegra30-host1x";
- reg = <0x50000000 0x00024000>;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
- <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
- interrupt-names = "syncpt", "host1x";
- clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
- clock-names = "host1x";
- resets = <&tegra_car 28>, <&mc TEGRA30_MC_RESET_HC>;
- reset-names = "host1x", "mc";
- iommus = <&mc TEGRA_SWGROUP_HC>;
- power-domains = <&pd_heg>;
- operating-points-v2 = <&host1x_dvfs_opp_table>;
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- ranges = <0x54000000 0x54000000 0x04000000>;
-
- mpe@54040000 {
- compatible = "nvidia,tegra30-mpe";
- reg = <0x54040000 0x00040000>;
- interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_MPE>;
- resets = <&tegra_car 60>;
- reset-names = "mpe";
- power-domains = <&pd_mpe>;
- operating-points-v2 = <&mpe_dvfs_opp_table>;
-
- iommus = <&mc TEGRA_SWGROUP_MPE>;
-
- status = "disabled";
- };
-
- vi@54080000 {
- compatible = "nvidia,tegra30-vi";
- reg = <0x54080000 0x00040000>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_VI>;
- resets = <&tegra_car 20>;
- reset-names = "vi";
- power-domains = <&pd_venc>;
- operating-points-v2 = <&vi_dvfs_opp_table>;
-
- iommus = <&mc TEGRA_SWGROUP_VI>;
-
- status = "disabled";
- };
-
- epp@540c0000 {
- compatible = "nvidia,tegra30-epp";
- reg = <0x540c0000 0x00040000>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_EPP>;
- resets = <&tegra_car 19>;
- reset-names = "epp";
- power-domains = <&pd_heg>;
- operating-points-v2 = <&epp_dvfs_opp_table>;
-
- iommus = <&mc TEGRA_SWGROUP_EPP>;
-
- status = "disabled";
- };
-
- isp@54100000 {
- compatible = "nvidia,tegra30-isp";
- reg = <0x54100000 0x00040000>;
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_ISP>;
- resets = <&tegra_car 23>;
- reset-names = "isp";
- power-domains = <&pd_venc>;
-
- iommus = <&mc TEGRA_SWGROUP_ISP>;
-
- status = "disabled";
- };
-
- gr2d@54140000 {
- compatible = "nvidia,tegra30-gr2d";
- reg = <0x54140000 0x00040000>;
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_GR2D>;
- resets = <&tegra_car 21>, <&mc TEGRA30_MC_RESET_2D>;
- reset-names = "2d", "mc";
- power-domains = <&pd_heg>;
- operating-points-v2 = <&gr2d_dvfs_opp_table>;
-
- iommus = <&mc TEGRA_SWGROUP_G2>;
- };
-
- gr3d@54180000 {
- compatible = "nvidia,tegra30-gr3d";
- reg = <0x54180000 0x00040000>;
- clocks = <&tegra_car TEGRA30_CLK_GR3D>,
- <&tegra_car TEGRA30_CLK_GR3D2>;
- clock-names = "3d", "3d2";
- resets = <&tegra_car 24>,
- <&tegra_car 98>,
- <&mc TEGRA30_MC_RESET_3D>,
- <&mc TEGRA30_MC_RESET_3D2>;
- reset-names = "3d", "3d2", "mc", "mc2";
- power-domains = <&pd_3d0>, <&pd_3d1>;
- power-domain-names = "3d0", "3d1";
- operating-points-v2 = <&gr3d_dvfs_opp_table>;
-
- iommus = <&mc TEGRA_SWGROUP_NV>,
- <&mc TEGRA_SWGROUP_NV2>;
- };
-
- dc@54200000 {
- compatible = "nvidia,tegra30-dc";
- reg = <0x54200000 0x00040000>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_DISP1>,
- <&tegra_car TEGRA30_CLK_PLL_P>;
- clock-names = "dc", "parent";
- resets = <&tegra_car 27>;
- reset-names = "dc";
- power-domains = <&pd_core>;
- operating-points-v2 = <&disp1_dvfs_opp_table>;
-
- iommus = <&mc TEGRA_SWGROUP_DC>;
-
- nvidia,head = <0>;
-
- interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>,
- <&mc TEGRA30_MC_DISPLAY0B &emc>,
- <&mc TEGRA30_MC_DISPLAY1B &emc>,
- <&mc TEGRA30_MC_DISPLAY0C &emc>,
- <&mc TEGRA30_MC_DISPLAYHC &emc>;
- interconnect-names = "wina",
- "winb",
- "winb-vfilter",
- "winc",
- "cursor";
-
- rgb {
- status = "disabled";
- };
- };
-
- dc@54240000 {
- compatible = "nvidia,tegra30-dc";
- reg = <0x54240000 0x00040000>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_DISP2>,
- <&tegra_car TEGRA30_CLK_PLL_P>;
- clock-names = "dc", "parent";
- resets = <&tegra_car 26>;
- reset-names = "dc";
- power-domains = <&pd_core>;
- operating-points-v2 = <&disp2_dvfs_opp_table>;
-
- iommus = <&mc TEGRA_SWGROUP_DCB>;
-
- nvidia,head = <1>;
-
- interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>,
- <&mc TEGRA30_MC_DISPLAY0BB &emc>,
- <&mc TEGRA30_MC_DISPLAY1BB &emc>,
- <&mc TEGRA30_MC_DISPLAY0CB &emc>,
- <&mc TEGRA30_MC_DISPLAYHCB &emc>;
- interconnect-names = "wina",
- "winb",
- "winb-vfilter",
- "winc",
- "cursor";
-
- rgb {
- status = "disabled";
- };
- };
-
- hdmi@54280000 {
- compatible = "nvidia,tegra30-hdmi";
- reg = <0x54280000 0x00040000>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_HDMI>,
- <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
- clock-names = "hdmi", "parent";
- resets = <&tegra_car 51>;
- reset-names = "hdmi";
- power-domains = <&pd_core>;
- operating-points-v2 = <&hdmi_dvfs_opp_table>;
- status = "disabled";
- };
-
- tvo@542c0000 {
- compatible = "nvidia,tegra30-tvo";
- reg = <0x542c0000 0x00040000>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_TVO>;
- power-domains = <&pd_core>;
- operating-points-v2 = <&tvo_dvfs_opp_table>;
- status = "disabled";
- };
-
- dsi@54300000 {
- compatible = "nvidia,tegra30-dsi";
- reg = <0x54300000 0x00040000>;
- clocks = <&tegra_car TEGRA30_CLK_DSIA>,
- <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
- clock-names = "dsi", "parent";
- resets = <&tegra_car 48>;
- reset-names = "dsi";
- power-domains = <&pd_core>;
- operating-points-v2 = <&dsia_dvfs_opp_table>;
- status = "disabled";
- };
-
- dsi@54400000 {
- compatible = "nvidia,tegra30-dsi";
- reg = <0x54400000 0x00040000>;
- clocks = <&tegra_car TEGRA30_CLK_DSIB>,
- <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
- clock-names = "dsi", "parent";
- resets = <&tegra_car 84>;
- reset-names = "dsi";
- power-domains = <&pd_core>;
- operating-points-v2 = <&dsib_dvfs_opp_table>;
- status = "disabled";
- };
- };
-
- timer@50040600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x50040600 0x20>;
- interrupt-parent = <&intc>;
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
- clocks = <&tegra_car TEGRA30_CLK_TWD>;
- };
-
- intc: interrupt-controller@50041000 {
- compatible = "arm,cortex-a9-gic";
- reg = <0x50041000 0x1000>,
- <0x50040100 0x0100>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupt-parent = <&intc>;
- };
-
- cache-controller@50043000 {
- compatible = "arm,pl310-cache";
- reg = <0x50043000 0x1000>;
- arm,data-latency = <6 6 2>;
- arm,tag-latency = <5 5 2>;
- cache-unified;
- cache-level = <2>;
- };
-
- lic: interrupt-controller@60004000 {
- compatible = "nvidia,tegra30-ictlr";
- reg = <0x60004000 0x100>,
- <0x60004100 0x50>,
- <0x60004200 0x50>,
- <0x60004300 0x50>,
- <0x60004400 0x50>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupt-parent = <&intc>;
- };
-
- timer@60005000 {
- compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
- reg = <0x60005000 0x400>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_TIMER>;
- };
-
- tegra_car: clock@60006000 {
- compatible = "nvidia,tegra30-car";
- reg = <0x60006000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
-
- pll-c {
- compatible = "nvidia,tegra30-pllc";
- clocks = <&tegra_car TEGRA30_CLK_PLL_C>;
- power-domains = <&pd_core>;
- operating-points-v2 = <&pll_c_dvfs_opp_table>;
- };
-
- pll-e {
- compatible = "nvidia,tegra30-plle";
- clocks = <&tegra_car TEGRA30_CLK_PLL_E>;
- power-domains = <&pd_core>;
- operating-points-v2 = <&pll_e_dvfs_opp_table>;
- };
-
- pll-m {
- compatible = "nvidia,tegra30-pllm";
- clocks = <&tegra_car TEGRA30_CLK_PLL_M>;
- power-domains = <&pd_core>;
- operating-points-v2 = <&pll_m_dvfs_opp_table>;
- };
-
- sclk {
- compatible = "nvidia,tegra30-sclk";
- clocks = <&tegra_car TEGRA30_CLK_SCLK>;
- power-domains = <&pd_core>;
- operating-points-v2 = <&sclk_dvfs_opp_table>;
- };
- };
-
- flow-controller@60007000 {
- compatible = "nvidia,tegra30-flowctrl";
- reg = <0x60007000 0x1000>;
- };
-
- apbdma: dma@6000a000 {
- compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
- reg = <0x6000a000 0x1400>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
- resets = <&tegra_car 34>;
- reset-names = "dma";
- #dma-cells = <1>;
- };
-
- ahb: ahb@6000c000 {
- compatible = "nvidia,tegra30-ahb";
- reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
- };
-
- actmon: actmon@6000c800 {
- compatible = "nvidia,tegra30-actmon";
- reg = <0x6000c800 0x400>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_ACTMON>,
- <&tegra_car TEGRA30_CLK_EMC>;
- clock-names = "actmon", "emc";
- resets = <&tegra_car TEGRA30_CLK_ACTMON>;
- reset-names = "actmon";
- operating-points-v2 = <&emc_bw_dfs_opp_table>;
- interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
- interconnect-names = "cpu-read";
- #cooling-cells = <2>;
- };
-
- gpio: gpio@6000d000 {
- compatible = "nvidia,tegra30-gpio";
- reg = <0x6000d000 0x1000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- gpio-ranges = <&pinmux 0 0 248>;
- };
-
- vde@6001a000 {
- compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
- reg = <0x6001a000 0x1000>, /* Syntax Engine */
- <0x6001b000 0x1000>, /* Video Bitstream Engine */
- <0x6001c000 0x100>, /* Macroblock Engine */
- <0x6001c200 0x100>, /* Post-processing Engine */
- <0x6001c400 0x100>, /* Motion Compensation Engine */
- <0x6001c600 0x100>, /* Transform Engine */
- <0x6001c800 0x100>, /* Pixel prediction block */
- <0x6001ca00 0x100>, /* Video DMA */
- <0x6001d800 0x400>; /* Video frame controls */
- reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
- "tfe", "ppb", "vdma", "frameid";
- iram = <&vde_pool>; /* IRAM region */
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
- <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
- interrupt-names = "sync-token", "bsev", "sxe";
- clocks = <&tegra_car TEGRA30_CLK_VDE>;
- reset-names = "vde", "mc";
- resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
- iommus = <&mc TEGRA_SWGROUP_VDE>;
- power-domains = <&pd_vde>;
- operating-points-v2 = <&vde_dvfs_opp_table>;
- };
-
- apbmisc@70000800 {
- compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
- reg = <0x70000800 0x64>, /* Chip revision */
- <0x70000008 0x04>; /* Strapping options */
- };
-
- pinmux: pinmux@70000868 {
- compatible = "nvidia,tegra30-pinmux";
- reg = <0x70000868 0x0d4>, /* Pad control registers */
- <0x70003000 0x3e4>; /* Mux registers */
- };
-
- /*
- * There are two serial driver i.e. 8250 based simple serial
- * driver and APB DMA based serial driver for higher baudrate
- * and performace. To enable the 8250 based driver, the compatible
- * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
- * the APB DMA based serial driver, the compatible is
- * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
- */
- uarta: serial@70006000 {
- compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
- reg = <0x70006000 0x40>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_UARTA>;
- resets = <&tegra_car 6>;
- reset-names = "serial";
- dmas = <&apbdma 8>, <&apbdma 8>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uartb: serial@70006040 {
- compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
- reg = <0x70006040 0x40>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_UARTB>;
- resets = <&tegra_car 7>;
- reset-names = "serial";
- dmas = <&apbdma 9>, <&apbdma 9>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uartc: serial@70006200 {
- compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
- reg = <0x70006200 0x100>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_UARTC>;
- resets = <&tegra_car 55>;
- reset-names = "serial";
- dmas = <&apbdma 10>, <&apbdma 10>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uartd: serial@70006300 {
- compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
- reg = <0x70006300 0x100>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_UARTD>;
- resets = <&tegra_car 65>;
- reset-names = "serial";
- dmas = <&apbdma 19>, <&apbdma 19>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uarte: serial@70006400 {
- compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
- reg = <0x70006400 0x100>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_UARTE>;
- resets = <&tegra_car 66>;
- reset-names = "serial";
- dmas = <&apbdma 20>, <&apbdma 20>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- gmi@70009000 {
- compatible = "nvidia,tegra30-gmi";
- reg = <0x70009000 0x1000>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0x48000000 0x7ffffff>;
- clocks = <&tegra_car TEGRA30_CLK_NOR>;
- clock-names = "gmi";
- resets = <&tegra_car 42>;
- reset-names = "gmi";
- power-domains = <&pd_core>;
- operating-points-v2 = <&nor_dvfs_opp_table>;
- status = "disabled";
- };
-
- pwm: pwm@7000a000 {
- compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
- reg = <0x7000a000 0x100>;
- #pwm-cells = <2>;
- clocks = <&tegra_car TEGRA30_CLK_PWM>;
- resets = <&tegra_car 17>;
- reset-names = "pwm";
- power-domains = <&pd_core>;
- operating-points-v2 = <&pwm_dvfs_opp_table>;
- status = "disabled";
- };
-
- i2c@7000c000 {
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000c000 0x100>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car TEGRA30_CLK_I2C1>,
- <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
- clock-names = "div-clk", "fast-clk";
- resets = <&tegra_car 12>;
- reset-names = "i2c";
- dmas = <&apbdma 21>, <&apbdma 21>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2c@7000c400 {
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000c400 0x100>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car TEGRA30_CLK_I2C2>,
- <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
- clock-names = "div-clk", "fast-clk";
- resets = <&tegra_car 54>;
- reset-names = "i2c";
- dmas = <&apbdma 22>, <&apbdma 22>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2c@7000c500 {
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000c500 0x100>;
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car TEGRA30_CLK_I2C3>,
- <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
- clock-names = "div-clk", "fast-clk";
- resets = <&tegra_car 67>;
- reset-names = "i2c";
- dmas = <&apbdma 23>, <&apbdma 23>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2c@7000c700 {
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000c700 0x100>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car TEGRA30_CLK_I2C4>,
- <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
- resets = <&tegra_car 103>;
- reset-names = "i2c";
- clock-names = "div-clk", "fast-clk";
- dmas = <&apbdma 26>, <&apbdma 26>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2c@7000d000 {
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000d000 0x100>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car TEGRA30_CLK_I2C5>,
- <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
- clock-names = "div-clk", "fast-clk";
- resets = <&tegra_car 47>;
- reset-names = "i2c";
- dmas = <&apbdma 24>, <&apbdma 24>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi@7000d400 {
- compatible = "nvidia,tegra30-slink";
- reg = <0x7000d400 0x200>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car TEGRA30_CLK_SBC1>;
- resets = <&tegra_car 41>;
- reset-names = "spi";
- dmas = <&apbdma 15>, <&apbdma 15>;
- dma-names = "rx", "tx";
- power-domains = <&pd_core>;
- operating-points-v2 = <&sbc1_dvfs_opp_table>;
- status = "disabled";
- };
-
- spi@7000d600 {
- compatible = "nvidia,tegra30-slink";
- reg = <0x7000d600 0x200>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car TEGRA30_CLK_SBC2>;
- resets = <&tegra_car 44>;
- reset-names = "spi";
- dmas = <&apbdma 16>, <&apbdma 16>;
- dma-names = "rx", "tx";
- power-domains = <&pd_core>;
- operating-points-v2 = <&sbc2_dvfs_opp_table>;
- status = "disabled";
- };
-
- spi@7000d800 {
- compatible = "nvidia,tegra30-slink";
- reg = <0x7000d800 0x200>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car TEGRA30_CLK_SBC3>;
- resets = <&tegra_car 46>;
- reset-names = "spi";
- dmas = <&apbdma 17>, <&apbdma 17>;
- dma-names = "rx", "tx";
- power-domains = <&pd_core>;
- operating-points-v2 = <&sbc3_dvfs_opp_table>;
- status = "disabled";
- };
-
- spi@7000da00 {
- compatible = "nvidia,tegra30-slink";
- reg = <0x7000da00 0x200>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car TEGRA30_CLK_SBC4>;
- resets = <&tegra_car 68>;
- reset-names = "spi";
- dmas = <&apbdma 18>, <&apbdma 18>;
- dma-names = "rx", "tx";
- power-domains = <&pd_core>;
- operating-points-v2 = <&sbc4_dvfs_opp_table>;
- status = "disabled";
- };
-
- spi@7000dc00 {
- compatible = "nvidia,tegra30-slink";
- reg = <0x7000dc00 0x200>;
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car TEGRA30_CLK_SBC5>;
- resets = <&tegra_car 104>;
- reset-names = "spi";
- dmas = <&apbdma 27>, <&apbdma 27>;
- dma-names = "rx", "tx";
- power-domains = <&pd_core>;
- operating-points-v2 = <&sbc5_dvfs_opp_table>;
- status = "disabled";
- };
-
- spi@7000de00 {
- compatible = "nvidia,tegra30-slink";
- reg = <0x7000de00 0x200>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car TEGRA30_CLK_SBC6>;
- resets = <&tegra_car 106>;
- reset-names = "spi";
- dmas = <&apbdma 28>, <&apbdma 28>;
- dma-names = "rx", "tx";
- power-domains = <&pd_core>;
- operating-points-v2 = <&sbc6_dvfs_opp_table>;
- status = "disabled";
- };
-
- rtc@7000e000 {
- compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
- reg = <0x7000e000 0x100>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_RTC>;
- };
-
- kbc@7000e200 {
- compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
- reg = <0x7000e200 0x100>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_KBC>;
- resets = <&tegra_car 36>;
- reset-names = "kbc";
- status = "disabled";
- };
-
- tegra_pmc: pmc@7000e400 {
- compatible = "nvidia,tegra30-pmc";
- reg = <0x7000e400 0x400>;
- clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
- clock-names = "pclk", "clk32k_in";
- #clock-cells = <1>;
-
- pd_core: core-domain {
- #power-domain-cells = <0>;
- operating-points-v2 = <&core_opp_table>;
- };
-
- powergates {
- pd_heg: heg {
- clocks = <&tegra_car TEGRA30_CLK_GR2D>,
- <&tegra_car TEGRA30_CLK_EPP>,
- <&tegra_car TEGRA30_CLK_HOST1X>;
- resets = <&mc TEGRA30_MC_RESET_2D>,
- <&mc TEGRA30_MC_RESET_EPP>,
- <&mc TEGRA30_MC_RESET_HC>,
- <&tegra_car TEGRA30_CLK_GR2D>,
- <&tegra_car TEGRA30_CLK_EPP>,
- <&tegra_car TEGRA30_CLK_HOST1X>;
- power-domains = <&pd_core>;
- #power-domain-cells = <0>;
- };
-
- pd_mpe: mpe {
- clocks = <&tegra_car TEGRA30_CLK_MPE>;
- resets = <&mc TEGRA30_MC_RESET_MPE>,
- <&tegra_car TEGRA30_CLK_MPE>;
- power-domains = <&pd_core>;
- #power-domain-cells = <0>;
- };
-
- pd_3d0: td {
- clocks = <&tegra_car TEGRA30_CLK_GR3D>;
- resets = <&mc TEGRA30_MC_RESET_3D>,
- <&tegra_car TEGRA30_CLK_GR3D>;
- power-domains = <&pd_core>;
- #power-domain-cells = <0>;
- };
-
- pd_3d1: td2 {
- clocks = <&tegra_car TEGRA30_CLK_GR3D2>;
- resets = <&mc TEGRA30_MC_RESET_3D2>,
- <&tegra_car TEGRA30_CLK_GR3D2>;
- power-domains = <&pd_core>;
- #power-domain-cells = <0>;
- };
-
- pd_vde: vdec {
- clocks = <&tegra_car TEGRA30_CLK_VDE>;
- resets = <&mc TEGRA30_MC_RESET_VDE>,
- <&tegra_car TEGRA30_CLK_VDE>;
- power-domains = <&pd_core>;
- #power-domain-cells = <0>;
- };
-
- pd_venc: venc {
- clocks = <&tegra_car TEGRA30_CLK_ISP>,
- <&tegra_car TEGRA30_CLK_VI>,
- <&tegra_car TEGRA30_CLK_CSI>;
- resets = <&mc TEGRA30_MC_RESET_ISP>,
- <&mc TEGRA30_MC_RESET_VI>,
- <&tegra_car TEGRA30_CLK_ISP>,
- <&tegra_car 20 /* VI */>,
- <&tegra_car TEGRA30_CLK_CSI>;
- power-domains = <&pd_core>;
- #power-domain-cells = <0>;
- };
- };
- };
-
- mc: memory-controller@7000f000 {
- compatible = "nvidia,tegra30-mc";
- reg = <0x7000f000 0x400>;
- clocks = <&tegra_car TEGRA30_CLK_MC>;
- clock-names = "mc";
-
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-
- #iommu-cells = <1>;
- #reset-cells = <1>;
- #interconnect-cells = <1>;
- };
-
- emc: memory-controller@7000f400 {
- compatible = "nvidia,tegra30-emc";
- reg = <0x7000f400 0x400>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_EMC>;
- power-domains = <&pd_core>;
-
- nvidia,memory-controller = <&mc>;
- operating-points-v2 = <&emc_icc_dvfs_opp_table>;
-
- #interconnect-cells = <0>;
- };
-
- fuse@7000f800 {
- compatible = "nvidia,tegra30-efuse";
- reg = <0x7000f800 0x400>;
- clocks = <&tegra_car TEGRA30_CLK_FUSE>;
- clock-names = "fuse";
- resets = <&tegra_car 39>;
- reset-names = "fuse";
- power-domains = <&pd_core>;
- operating-points-v2 = <&fuse_burn_dvfs_opp_table>;
- };
-
- tsensor: tsensor@70014000 {
- compatible = "nvidia,tegra30-tsensor";
- reg = <0x70014000 0x500>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_TSENSOR>;
- resets = <&tegra_car TEGRA30_CLK_TSENSOR>;
-
- assigned-clocks = <&tegra_car TEGRA30_CLK_TSENSOR>;
- assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
- assigned-clock-rates = <500000>;
-
- #thermal-sensor-cells = <1>;
- };
-
- hda@70030000 {
- compatible = "nvidia,tegra30-hda";
- reg = <0x70030000 0x10000>;
- interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_HDA>,
- <&tegra_car TEGRA30_CLK_HDA2HDMI>,
- <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
- clock-names = "hda", "hda2hdmi", "hda2codec_2x";
- resets = <&tegra_car 125>, /* hda */
- <&tegra_car 128>, /* hda2hdmi */
- <&tegra_car 111>; /* hda2codec_2x */
- reset-names = "hda", "hda2hdmi", "hda2codec_2x";
- status = "disabled";
- };
-
- ahub@70080000 {
- compatible = "nvidia,tegra30-ahub";
- reg = <0x70080000 0x200>,
- <0x70080200 0x100>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
- <&tegra_car TEGRA30_CLK_APBIF>;
- clock-names = "d_audio", "apbif";
- resets = <&tegra_car 106>, /* d_audio */
- <&tegra_car 107>, /* apbif */
- <&tegra_car 30>, /* i2s0 */
- <&tegra_car 11>, /* i2s1 */
- <&tegra_car 18>, /* i2s2 */
- <&tegra_car 101>, /* i2s3 */
- <&tegra_car 102>, /* i2s4 */
- <&tegra_car 108>, /* dam0 */
- <&tegra_car 109>, /* dam1 */
- <&tegra_car 110>, /* dam2 */
- <&tegra_car 10>; /* spdif */
- reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
- "i2s3", "i2s4", "dam0", "dam1", "dam2",
- "spdif";
- dmas = <&apbdma 1>, <&apbdma 1>,
- <&apbdma 2>, <&apbdma 2>,
- <&apbdma 3>, <&apbdma 3>,
- <&apbdma 4>, <&apbdma 4>;
- dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
- "rx3", "tx3";
- ranges;
- #address-cells = <1>;
- #size-cells = <1>;
-
- tegra_i2s0: i2s@70080300 {
- compatible = "nvidia,tegra30-i2s";
- reg = <0x70080300 0x100>;
- nvidia,ahub-cif-ids = <4 4>;
- clocks = <&tegra_car TEGRA30_CLK_I2S0>;
- resets = <&tegra_car 30>;
- reset-names = "i2s";
- status = "disabled";
- };
-
- tegra_i2s1: i2s@70080400 {
- compatible = "nvidia,tegra30-i2s";
- reg = <0x70080400 0x100>;
- nvidia,ahub-cif-ids = <5 5>;
- clocks = <&tegra_car TEGRA30_CLK_I2S1>;
- resets = <&tegra_car 11>;
- reset-names = "i2s";
- status = "disabled";
- };
-
- tegra_i2s2: i2s@70080500 {
- compatible = "nvidia,tegra30-i2s";
- reg = <0x70080500 0x100>;
- nvidia,ahub-cif-ids = <6 6>;
- clocks = <&tegra_car TEGRA30_CLK_I2S2>;
- resets = <&tegra_car 18>;
- reset-names = "i2s";
- status = "disabled";
- };
-
- tegra_i2s3: i2s@70080600 {
- compatible = "nvidia,tegra30-i2s";
- reg = <0x70080600 0x100>;
- nvidia,ahub-cif-ids = <7 7>;
- clocks = <&tegra_car TEGRA30_CLK_I2S3>;
- resets = <&tegra_car 101>;
- reset-names = "i2s";
- status = "disabled";
- };
-
- tegra_i2s4: i2s@70080700 {
- compatible = "nvidia,tegra30-i2s";
- reg = <0x70080700 0x100>;
- nvidia,ahub-cif-ids = <8 8>;
- clocks = <&tegra_car TEGRA30_CLK_I2S4>;
- resets = <&tegra_car 102>;
- reset-names = "i2s";
- status = "disabled";
- };
- };
-
- mmc@78000000 {
- compatible = "nvidia,tegra30-sdhci";
- reg = <0x78000000 0x200>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
- clock-names = "sdhci";
- resets = <&tegra_car 14>;
- reset-names = "sdhci";
- power-domains = <&pd_core>;
- operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
- status = "disabled";
- };
-
- mmc@78000200 {
- compatible = "nvidia,tegra30-sdhci";
- reg = <0x78000200 0x200>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
- clock-names = "sdhci";
- resets = <&tegra_car 9>;
- reset-names = "sdhci";
- status = "disabled";
- };
-
- mmc@78000400 {
- compatible = "nvidia,tegra30-sdhci";
- reg = <0x78000400 0x200>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
- clock-names = "sdhci";
- resets = <&tegra_car 69>;
- reset-names = "sdhci";
- power-domains = <&pd_core>;
- operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
- status = "disabled";
- };
-
- mmc@78000600 {
- compatible = "nvidia,tegra30-sdhci";
- reg = <0x78000600 0x200>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
- clock-names = "sdhci";
- resets = <&tegra_car 15>;
- reset-names = "sdhci";
- status = "disabled";
- };
-
- usb@7d000000 {
- compatible = "nvidia,tegra30-ehci";
- reg = <0x7d000000 0x4000>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- phy_type = "utmi";
- clocks = <&tegra_car TEGRA30_CLK_USBD>;
- resets = <&tegra_car 22>;
- reset-names = "usb";
- nvidia,needs-double-reset;
- nvidia,phy = <&phy1>;
- power-domains = <&pd_core>;
- operating-points-v2 = <&usbd_dvfs_opp_table>;
- status = "disabled";
- };
-
- phy1: usb-phy@7d000000 {
- compatible = "nvidia,tegra30-usb-phy";
- reg = <0x7d000000 0x4000>,
- <0x7d000000 0x4000>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- phy_type = "utmi";
- clocks = <&tegra_car TEGRA30_CLK_USBD>,
- <&tegra_car TEGRA30_CLK_PLL_U>,
- <&tegra_car TEGRA30_CLK_USBD>;
- clock-names = "reg", "pll_u", "utmi-pads";
- resets = <&tegra_car 22>, <&tegra_car 22>;
- reset-names = "usb", "utmi-pads";
- #phy-cells = <0>;
- nvidia,hssync-start-delay = <9>;
- nvidia,idle-wait-delay = <17>;
- nvidia,elastic-limit = <16>;
- nvidia,term-range-adj = <6>;
- nvidia,xcvr-setup = <51>;
- nvidia,xcvr-setup-use-fuses;
- nvidia,xcvr-lsfslew = <1>;
- nvidia,xcvr-lsrslew = <1>;
- nvidia,xcvr-hsslew = <32>;
- nvidia,hssquelch-level = <2>;
- nvidia,hsdiscon-level = <5>;
- nvidia,has-utmi-pad-registers;
- nvidia,pmc = <&tegra_pmc 0>;
- status = "disabled";
- };
-
- usb@7d004000 {
- compatible = "nvidia,tegra30-ehci";
- reg = <0x7d004000 0x4000>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- phy_type = "utmi";
- clocks = <&tegra_car TEGRA30_CLK_USB2>;
- resets = <&tegra_car 58>;
- reset-names = "usb";
- nvidia,phy = <&phy2>;
- power-domains = <&pd_core>;
- operating-points-v2 = <&usb2_dvfs_opp_table>;
- status = "disabled";
- };
-
- phy2: usb-phy@7d004000 {
- compatible = "nvidia,tegra30-usb-phy";
- reg = <0x7d004000 0x4000>,
- <0x7d000000 0x4000>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- phy_type = "utmi";
- clocks = <&tegra_car TEGRA30_CLK_USB2>,
- <&tegra_car TEGRA30_CLK_PLL_U>,
- <&tegra_car TEGRA30_CLK_USBD>;
- clock-names = "reg", "pll_u", "utmi-pads";
- resets = <&tegra_car 58>, <&tegra_car 22>;
- reset-names = "usb", "utmi-pads";
- #phy-cells = <0>;
- nvidia,hssync-start-delay = <9>;
- nvidia,idle-wait-delay = <17>;
- nvidia,elastic-limit = <16>;
- nvidia,term-range-adj = <6>;
- nvidia,xcvr-setup = <51>;
- nvidia,xcvr-setup-use-fuses;
- nvidia,xcvr-lsfslew = <2>;
- nvidia,xcvr-lsrslew = <2>;
- nvidia,xcvr-hsslew = <32>;
- nvidia,hssquelch-level = <2>;
- nvidia,hsdiscon-level = <5>;
- nvidia,pmc = <&tegra_pmc 2>;
- status = "disabled";
- };
-
- usb@7d008000 {
- compatible = "nvidia,tegra30-ehci";
- reg = <0x7d008000 0x4000>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- phy_type = "utmi";
- clocks = <&tegra_car TEGRA30_CLK_USB3>;
- resets = <&tegra_car 59>;
- reset-names = "usb";
- nvidia,phy = <&phy3>;
- power-domains = <&pd_core>;
- operating-points-v2 = <&usb3_dvfs_opp_table>;
- status = "disabled";
- };
-
- phy3: usb-phy@7d008000 {
- compatible = "nvidia,tegra30-usb-phy";
- reg = <0x7d008000 0x4000>,
- <0x7d000000 0x4000>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- phy_type = "utmi";
- clocks = <&tegra_car TEGRA30_CLK_USB3>,
- <&tegra_car TEGRA30_CLK_PLL_U>,
- <&tegra_car TEGRA30_CLK_USBD>;
- clock-names = "reg", "pll_u", "utmi-pads";
- resets = <&tegra_car 59>, <&tegra_car 22>;
- reset-names = "usb", "utmi-pads";
- #phy-cells = <0>;
- nvidia,hssync-start-delay = <0>;
- nvidia,idle-wait-delay = <17>;
- nvidia,elastic-limit = <16>;
- nvidia,term-range-adj = <6>;
- nvidia,xcvr-setup = <51>;
- nvidia,xcvr-setup-use-fuses;
- nvidia,xcvr-lsfslew = <2>;
- nvidia,xcvr-lsrslew = <2>;
- nvidia,xcvr-hsslew = <32>;
- nvidia,hssquelch-level = <2>;
- nvidia,hsdiscon-level = <5>;
- nvidia,pmc = <&tegra_pmc 1>;
- status = "disabled";
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
- #cooling-cells = <2>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
- #cooling-cells = <2>;
- };
-
- cpu2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <2>;
- clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
- #cooling-cells = <2>;
- };
-
- cpu3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <3>;
- clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
- #cooling-cells = <2>;
- };
- };
-
- pmu {
- compatible = "arm,cortex-a9-pmu";
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
-
- thermal-zones {
- tsensor0-thermal {
- polling-delay-passive = <1000>; /* milliseconds */
- polling-delay = <5000>; /* milliseconds */
-
- thermal-sensors = <&tsensor 0>;
-
- trips {
- level1_trip: dvfs-alert {
- /* throttle at 80C until temperature drops to 79.8C */
- temperature = <80000>;
- hysteresis = <200>;
- type = "passive";
- };
-
- level2_trip: cpu-div2-throttle {
- /* hardware CPU x2 freq throttle at 85C */
- temperature = <85000>;
- hysteresis = <200>;
- type = "hot";
- };
-
- level3_trip: soc-critical {
- /* hardware shut down at 90C */
- temperature = <90000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&level1_trip>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&actmon THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
-
- tsensor1-thermal {
- status = "disabled";
-
- polling-delay-passive = <1000>; /* milliseconds */
- polling-delay = <0>; /* milliseconds */
-
- thermal-sensors = <&tsensor 1>;
-
- trips {
- dvfs-alert {
- temperature = <80000>;
- hysteresis = <200>;
- type = "passive";
- };
- };
- };
- };
-};
projects / linux-2.6-microblaze.git / blobdiff