Merge branch 'timers-compat' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[linux-2.6-microblaze.git] / arch / arm / boot / dts / sun8i-a83t.dtsi
index 1dc4cfe..8923ba6 100644 (file)
@@ -44,6 +44,8 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
+#include <dt-bindings/clock/sun8i-r-ccu.h>
+
 / {
        interrupt-parent = <&gic>;
        #address-cells = <1>;
                #size-cells = <1>;
                ranges;
 
+               syscon: syscon@1c00000 {
+                       compatible = "allwinner,sun8i-a83t-system-controller",
+                               "syscon";
+                       reg = <0x01c00000 0x1000>;
+               };
+
                dma: dma-controller@1c02000 {
                        compatible = "allwinner,sun8i-a83t-dma";
                        reg = <0x01c02000 0x1000>;
                        #interrupt-cells = <3>;
                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
                };
+
+               r_ccu: clock@1f01400 {
+                       compatible = "allwinner,sun8i-a83t-r-ccu";
+                       reg = <0x01f01400 0x400>;
+                       clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
+                                <&ccu 6>;
+                       clock-names = "hosc", "losc", "iosc", "pll-periph";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               r_pio: pinctrl@1f02c00 {
+                       compatible = "allwinner,sun8i-a83t-r-pinctrl";
+                       reg = <0x01f02c00 0x400>;
+                       interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
+                                <&osc16Md512>;
+                       clock-names = "apb", "hosc", "losc";
+                       gpio-controller;
+                       #gpio-cells = <3>;
+                       interrupt-controller;
+                       #interrupt-cells = <3>;
+               };
        };
 };