ARM: dts: imx7d-sdb: Add Wifi support

[linux-2.6-microblaze.git] / arch / arm / boot / dts / r8a7793.dtsi

diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 48ce21c..4de6041 100644 (file)
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -65,9 +65,8 @@
                        power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
                };
 
-               L2_CA15: cache-controller@0 {
+               L2_CA15: cache-controller-0 {
                        compatible = "cache";
-                       reg = <0>;
                        power-domains = <&sysc R8A7793_PD_CA15_SCU>;
                        cache-unified;
                        cache-level = <2>;
@@ -109,6 +108,9 @@
                        <0 0xf1004000 0 0x2000>,
                        <0 0xf1006000 0 0x2000>;
                interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+               clocks = <&mstp4_clks R8A7793_CLK_INTC_SYS>;
+               clock-names = "clk";
+               power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
        };
 
        gpio0: gpio@e6050000 {
@@ -1179,10 +1181,12 @@
                mstp4_clks: mstp4_clks@e6150140 {
                        compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
-                       clocks = <&cp_clk>;
+                       clocks = <&cp_clk>, <&zs_clk>;
                        #clock-cells = <1>;
-                       clock-indices = <R8A7793_CLK_IRQC>;
-                       clock-output-names = "irqc";
+                       clock-indices = <
+                               R8A7793_CLK_IRQC R8A7793_CLK_INTC_SYS
+                       >;
+                       clock-output-names = "irqc", "intc-sys";
                };
                mstp5_clks: mstp5_clks@e6150144 {
                        compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1265,8 +1269,11 @@
                        compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
                        clocks = <&p_clk>,
-                               <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
-                               <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+                               <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
+                               <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
+                               <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
+                               <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
+                               <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
                                <&p_clk>,
                                <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
                                <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
@@ -1426,11 +1433,11 @@
 
                rcar_sound,dvc {
                        dvc0: dvc-0 {
-                               dmas = <&audma0 0xbc>;
+                               dmas = <&audma1 0xbc>;
                                dma-names = "tx";
                        };
                        dvc1: dvc-1 {
-                               dmas = <&audma0 0xbe>;
+                               dmas = <&audma1 0xbe>;
                                dma-names = "tx";
                        };
                };