Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

[linux-2.6-microblaze.git] / arch / arm / boot / dts / mt7623.dtsi

diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 8e7c654..e10c034 100644 (file)
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -28,7 +28,7 @@
        compatible = "mediatek,mt7623";
        interrupt-parent = <&sysirq>;
 
-       cpu_opp_table: opp_table {
+       cpu_opp_table: opp-table {
                compatible = "operating-points-v2";
                opp-shared;
 
@@ -94,6 +94,9 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
                        reg = <0x1>;
+                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
+                                <&apmixedsys CLK_APMIXED_MAINPLL>;
+                       clock-names = "cpu", "intermediate";
                        operating-points-v2 = <&cpu_opp_table>;
                        clock-frequency = <1300000000>;
                };
@@ -102,6 +105,9 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
                        reg = <0x2>;
+                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
+                                <&apmixedsys CLK_APMIXED_MAINPLL>;
+                       clock-names = "cpu", "intermediate";
                        operating-points-v2 = <&cpu_opp_table>;
                        clock-frequency = <1300000000>;
                };
@@ -110,6 +116,9 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
                        reg = <0x3>;
+                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
+                                <&apmixedsys CLK_APMIXED_MAINPLL>;
+                       clock-names = "cpu", "intermediate";
                        operating-points-v2 = <&cpu_opp_table>;
                        clock-frequency = <1300000000>;
                };
@@ -136,32 +145,32 @@
        };
 
        thermal-zones {
-                       cpu_thermal: cpu_thermal {
+                       cpu_thermal: cpu-thermal {
                                polling-delay-passive = <1000>;
                                polling-delay = <1000>;
 
                                thermal-sensors = <&thermal 0>;
 
                                trips {
-                                       cpu_passive: cpu_passive {
+                                       cpu_passive: cpu-passive {
                                                temperature = <47000>;
                                                hysteresis = <2000>;
                                                type = "passive";
                                        };
 
-                                       cpu_active: cpu_active {
+                                       cpu_active: cpu-active {
                                                temperature = <67000>;
                                                hysteresis = <2000>;
                                                type = "active";
                                        };
 
-                                       cpu_hot: cpu_hot {
+                                       cpu_hot: cpu-hot {
                                                temperature = <87000>;
                                                hysteresis = <2000>;
                                                type = "hot";
                                        };
 
-                                       cpu_crit {
+                                       cpu-crit {
                                                temperature = <107000>;
                                                hysteresis = <2000>;
                                                type = "critical";
@@ -668,6 +677,111 @@
                #reset-cells = <1>;
        };
 
+       pcie: pcie@1a140000 {
+               compatible = "mediatek,mt7623-pcie";
+               device_type = "pci";
+               reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
+                     <0 0x1a142000 0 0x1000>, /* Port0 registers */
+                     <0 0x1a143000 0 0x1000>, /* Port1 registers */
+                     <0 0x1a144000 0 0x1000>; /* Port2 registers */
+               reg-names = "subsys", "port0", "port1", "port2";
+               #address-cells = <3>;
+               #size-cells = <2>;
+               #interrupt-cells = <1>;
+               interrupt-map-mask = <0xf800 0 0 0>;
+               interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
+                               <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
+                               <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+                        <&hifsys CLK_HIFSYS_PCIE0>,
+                        <&hifsys CLK_HIFSYS_PCIE1>,
+                        <&hifsys CLK_HIFSYS_PCIE2>;
+               clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
+               resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
+                        <&hifsys MT2701_HIFSYS_PCIE1_RST>,
+                        <&hifsys MT2701_HIFSYS_PCIE2_RST>;
+               reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
+               phys = <&pcie0_port PHY_TYPE_PCIE>,
+                      <&pcie1_port PHY_TYPE_PCIE>,
+                      <&u3port1 PHY_TYPE_PCIE>;
+               phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+               bus-range = <0x00 0xff>;
+               status = "disabled";
+               ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
+                         0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
+
+               pcie@0,0 {
+                       reg = <0x0000 0 0 0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0>;
+                       interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
+                       ranges;
+                       num-lanes = <1>;
+                       status = "disabled";
+               };
+
+               pcie@1,0 {
+                       reg = <0x0800 0 0 0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0>;
+                       interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+                       ranges;
+                       num-lanes = <1>;
+                       status = "disabled";
+               };
+
+               pcie@2,0 {
+                       reg = <0x1000 0 0 0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0>;
+                       interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+                       ranges;
+                       num-lanes = <1>;
+                       status = "disabled";
+               };
+       };
+
+       pcie0_phy: pcie-phy@1a149000 {
+               compatible = "mediatek,generic-tphy-v1";
+               reg = <0 0x1a149000 0 0x0700>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+               status = "disabled";
+
+               pcie0_port: pcie-phy@1a149900 {
+                       reg = <0 0x1a149900 0 0x0700>;
+                       clocks = <&clk26m>;
+                       clock-names = "ref";
+                       #phy-cells = <1>;
+                       status = "okay";
+               };
+       };
+
+       pcie1_phy: pcie-phy@1a14a000 {
+               compatible = "mediatek,generic-tphy-v1";
+               reg = <0 0x1a14a000 0 0x0700>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+               status = "disabled";
+
+               pcie1_port: pcie-phy@1a14a900 {
+                       reg = <0 0x1a14a900 0 0x0700>;
+                       clocks = <&clk26m>;
+                       clock-names = "ref";
+                       #phy-cells = <1>;
+                       status = "okay";
+               };
+       };
+
        usb1: usb@1a1c0000 {
                compatible = "mediatek,mt7623-xhci",
                             "mediatek,mt8173-xhci";