arm: dts: mt7623: add Mali-450 device node

[linux-2.6-microblaze.git] / arch / arm / boot / dts / mt7623.dtsi

diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index f76b4a3..3a6b856 100644 (file)
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -3,6 +3,7 @@
  * Copyright (c) 2017-2018 MediaTek Inc.
  * Author: John Crispin <john@phrozen.org>
  *        Sean Wang <sean.wang@mediatek.com>
+ *        Ryder Lee <ryder.lee@mediatek.com>
  *
  */
 
@@ -733,6 +734,30 @@
                #reset-cells = <1>;
        };
 
+       mali: gpu@13040000 {
+               compatible = "mediatek,mt7623-mali", "arm,mali-450";
+               reg = <0 0x13040000 0 0x30000>;
+               interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
+                                 "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",
+                                 "pp";
+               clocks = <&topckgen CLK_TOP_MMPLL>,
+                        <&g3dsys CLK_G3DSYS_CORE>;
+               clock-names = "bus", "core";
+               power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
+               resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
+       };
+
        mmsys: syscon@14000000 {
                compatible = "mediatek,mt7623-mmsys",
                             "mediatek,mt2701-mmsys",