Merge tag 'media/v5.8-3' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab...

[linux-2.6-microblaze.git] / arch / arm / boot / dts / imx6qdl.dtsi

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 98da446..32114cf 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -74,7 +74,8 @@
                interrupt-parent = <&gpc>;
                interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
                fsl,tempmon = <&anatop>;
-               fsl,tempmon-data = <&ocotp>;
+               nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
+               nvmem-cell-names = "calib", "temp_grade";
                clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
                #thermal-sensor-cells = <0>;
        };
@@ -857,7 +858,7 @@
                                interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
                        };
 
-                       src: src@20d8000 {
+                       src: reset-controller@20d8000 {
                                compatible = "fsl,imx6q-src", "fsl,imx51-src";
                                reg = <0x020d8000 0x4000>;
                                interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
@@ -1045,7 +1046,7 @@
                                         <&clks IMX6QDL_CLK_ENET>,
                                         <&clks IMX6QDL_CLK_ENET_REF>;
                                clock-names = "ipg", "ahb", "ptp";
-                               gpr = <&gpr>;
+                               fsl,stop-mode = <&gpr 0x34 27>;
                                status = "disabled";
                        };
 
@@ -1171,6 +1172,14 @@
                                cpu_speed_grade: speed-grade@10 {
                                        reg = <0x10 4>;
                                };
+
+                               tempmon_calib: calib@38 {
+                                       reg = <0x38 4>;
+                               };
+
+                               tempmon_temp_grade: temp-grade@20 {
+                                       reg = <0x20 4>;
+                               };
                        };
 
                        tzasc@21d0000 { /* TZASC1 */