Merge tag 'omap-for-v5.6/dt-late-signed' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-microblaze.git] / arch / arm / boot / dts / dra7-l4.dtsi
index c174086..fc41883 100644 (file)
                };
 
                target-module@170000 {                  /* 0x48970000, ap 21 0a.0 */
-                       compatible = "ti,sysc";
-                       status = "disabled";
+                       compatible = "ti,sysc-omap4", "ti,sysc";
+                       reg = <0x170010 0x4>;
+                       reg-names = "sysc";
+                       ti,sysc-midle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
+                       clock-names = "fck";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges = <0x0 0x170000 0x10000>;
+                       status = "disabled";
                };
 
                target-module@190000 {                  /* 0x48990000, ap 23 2e.0 */
-                       compatible = "ti,sysc";
-                       status = "disabled";
+                       compatible = "ti,sysc-omap4", "ti,sysc";
+                       reg = <0x190010 0x4>;
+                       reg-names = "sysc";
+                       ti,sysc-midle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
+                       clock-names = "fck";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges = <0x0 0x190000 0x10000>;
+                       status = "disabled";
                };
 
                target-module@1b0000 {                  /* 0x489b0000, ap 25 34.0 */
-                       compatible = "ti,sysc";
-                       status = "disabled";
+                       compatible = "ti,sysc-omap4", "ti,sysc";
+                       reg = <0x1b0000 0x4>,
+                             <0x1b0010 0x4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-midle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
+                       clock-names = "fck";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges = <0x0 0x1b0000 0x10000>;
+                       status = "disabled";
                };
 
-               target-module@1d0000 {                  /* 0x489d0000, ap 27 30.0 */
-                       compatible = "ti,sysc";
-                       status = "disabled";
+               target-module@1d0010 {                  /* 0x489d0000, ap 27 30.0 */
+                       compatible = "ti,sysc-omap4", "ti,sysc";
+                       reg = <0x1d0010 0x4>;
+                       reg-names = "sysc";
+                       ti,sysc-midle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
+                       clock-names = "fck";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges = <0x0 0x1d0000 0x10000>;
+
+                       vpe: vpe@0 {
+                               compatible = "ti,dra7-vpe";
+                               reg = <0x0000 0x120>,
+                                     <0x0700 0x80>,
+                                     <0x5700 0x18>,
+                                     <0xd000 0x400>;
+                               reg-names = "vpe_top",
+                                           "sc",
+                                           "csc",
+                                           "vpdma";
+                               interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+                       };
                };
        };
 };