Merge tag 'media/v5.8-3' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab...
[linux-2.6-microblaze.git] / arch / arm / boot / dts / am571x-idk.dts
index c13756f..99a408a 100644 (file)
@@ -10,6 +10,7 @@
 #include "dra7-mmc-iodelay.dtsi"
 #include "dra72x-mmc-iodelay.dtsi"
 #include "am57xx-idk-common.dtsi"
+#include "dra7-ipu-dsp-common.dtsi"
 
 / {
        model = "TI AM5718 IDK";
                reg = <0x0 0x80000000 0x0 0x40000000>;
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               ipu2_memory_region: ipu2-memory@95800000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x0 0x95800000 0x0 0x3800000>;
+                       reusable;
+                       status = "okay";
+               };
+
+               dsp1_memory_region: dsp1-memory@99000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x0 0x99000000 0x0 0x4000000>;
+                       reusable;
+                       status = "okay";
+               };
+
+               ipu1_memory_region: ipu1-memory@9d000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x0 0x9d000000 0x0 0x2000000>;
+                       reusable;
+                       status = "okay";
+               };
+       };
+
        leds {
                compatible = "gpio-leds";
                cpu0-led {
        load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
 };
 
-&mailbox5 {
+&ipu2 {
        status = "okay";
-       mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
-               status = "okay";
-       };
-       mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
-               status = "okay";
-       };
+       memory-region = <&ipu2_memory_region>;
 };
 
-&mailbox6 {
+&ipu1 {
        status = "okay";
-       mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
-               status = "okay";
-       };
+       memory-region = <&ipu1_memory_region>;
+};
+
+&dsp1 {
+       status = "okay";
+       memory-region = <&dsp1_memory_region>;
 };
 
 &pcie1_rc {