The processor idle states which are available for use have the
following attributes:
- name: (RO) Name of the idle state (string).
+ ======== ==== =================================================
+ name: (RO) Name of the idle state (string).
latency: (RO) The latency to exit out of this idle state (in
- microseconds).
+ microseconds).
- power: (RO) The power consumed while in this idle state (in
- milliwatts).
+ power: (RO) The power consumed while in this idle state (in
+ milliwatts).
- time: (RO) The total time spent in this idle state (in microseconds).
+ time: (RO) The total time spent in this idle state
+ (in microseconds).
- usage: (RO) Number of times this state was entered (a count).
+ usage: (RO) Number of times this state was entered (a count).
- above: (RO) Number of times this state was entered, but the
- observed CPU idle duration was too short for it (a count).
+ above: (RO) Number of times this state was entered, but the
+ observed CPU idle duration was too short for it
+ (a count).
- below: (RO) Number of times this state was entered, but the
- observed CPU idle duration was too long for it (a count).
+ below: (RO) Number of times this state was entered, but the
+ observed CPU idle duration was too long for it
+ (a count).
+ ======== ==== =================================================
What: /sys/devices/system/cpu/cpuX/cpuidle/stateN/desc
Date: February 2008
This switch controls the boost setting for the whole system.
Boosting allows the CPU and the firmware to run at a frequency
beyound it's nominal limit.
+
More details can be found in
Documentation/admin-guide/pm/cpufreq.rst
Description: Parameters for the CPU cache attributes
allocation_policy:
- - WriteAllocate: allocate a memory location to a cache line
- on a cache miss because of a write
- - ReadAllocate: allocate a memory location to a cache line
+ - WriteAllocate:
+ allocate a memory location to a cache line
+ on a cache miss because of a write
+ - ReadAllocate:
+ allocate a memory location to a cache line
on a cache miss because of a read
- - ReadWriteAllocate: both writeallocate and readallocate
+ - ReadWriteAllocate:
+ both writeallocate and readallocate
- attributes: LEGACY used only on IA64 and is same as write_policy
+ attributes:
+ LEGACY used only on IA64 and is same as write_policy
- coherency_line_size: the minimum amount of data in bytes that gets
+ coherency_line_size:
+ the minimum amount of data in bytes that gets
transferred from memory to cache
- level: the cache hierarchy in the multi-level cache configuration
+ level:
+ the cache hierarchy in the multi-level cache configuration
- number_of_sets: total number of sets in the cache, a set is a
+ number_of_sets:
+ total number of sets in the cache, a set is a
collection of cache lines with the same cache index
- physical_line_partition: number of physical cache line per cache tag
+ physical_line_partition:
+ number of physical cache line per cache tag
- shared_cpu_list: the list of logical cpus sharing the cache
+ shared_cpu_list:
+ the list of logical cpus sharing the cache
- shared_cpu_map: logical cpu mask containing the list of cpus sharing
+ shared_cpu_map:
+ logical cpu mask containing the list of cpus sharing
the cache
- size: the total cache size in kB
+ size:
+ the total cache size in kB
type:
- Instruction: cache that only holds instructions
- Data: cache that only caches data
- Unified: cache that holds both data and instructions
- ways_of_associativity: degree of freedom in placing a particular block
- of memory in the cache
+ ways_of_associativity:
+ degree of freedom in placing a particular block
+ of memory in the cache
write_policy:
- - WriteThrough: data is written to both the cache line
+ - WriteThrough:
+ data is written to both the cache line
and to the block in the lower-level memory
- - WriteBack: data is written only to the cache line and
+ - WriteBack:
+ data is written only to the cache line and
the modified cache line is written to main
memory only when it is replaced
throttle attributes exported in the 'throttle_stats' directory:
- turbo_stat : This file gives the total number of times the max
- frequency is throttled to lower frequency in turbo (at and above
- nominal frequency) range of frequencies.
+ frequency is throttled to lower frequency in turbo (at and above
+ nominal frequency) range of frequencies.
- sub_turbo_stat : This file gives the total number of times the
- max frequency is throttled to lower frequency in sub-turbo(below
- nominal frequency) range of frequencies.
+ max frequency is throttled to lower frequency in sub-turbo(below
+ nominal frequency) range of frequencies.
- unthrottle : This file gives the total number of times the max
- frequency is unthrottled after being throttled.
+ frequency is unthrottled after being throttled.
- powercap : This file gives the total number of times the max
- frequency is throttled due to 'Power Capping'.
+ frequency is throttled due to 'Power Capping'.
- overtemp : This file gives the total number of times the max
- frequency is throttled due to 'CPU Over Temperature'.
+ frequency is throttled due to 'CPU Over Temperature'.
- supply_fault : This file gives the total number of times the
- max frequency is throttled due to 'Power Supply Failure'.
+ max frequency is throttled due to 'Power Supply Failure'.
- overcurrent : This file gives the total number of times the
- max frequency is throttled due to 'Overcurrent'.
+ max frequency is throttled due to 'Overcurrent'.
- occ_reset : This file gives the total number of times the max
- frequency is throttled due to 'OCC Reset'.
+ frequency is throttled due to 'OCC Reset'.
The sysfs attributes representing different throttle reasons like
powercap, overtemp, supply_fault, overcurrent and occ_reset map to
Date: June 2016
Contact: Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>
Description: AArch64 CPU registers
+
'identification' directory exposes the CPU ID registers for
- identifying model and revision of the CPU.
+ identifying model and revision of the CPU.
What: /sys/devices/system/cpu/cpu#/cpu_capacity
Date: December 2016
vulnerabilities. The output of those files reflects the
state of the CPUs in the system. Possible output values:
+ ================ ==============================================
"Not affected" CPU is not affected by the vulnerability
"Vulnerable" CPU is affected and no mitigation in effect
"Mitigation: $M" CPU is affected and mitigation $M is in effect
+ ================ ==============================================
See also: Documentation/admin-guide/hw-vuln/index.rst
control: Read/write interface to control SMT. Possible
values:
+ ================ =========================================
"on" SMT is enabled
"off" SMT is disabled
"forceoff" SMT is force disabled. Cannot be changed.
"notsupported" SMT is not supported by the CPU
"notimplemented" SMT runtime toggling is not
implemented for the architecture
+ ================ =========================================
If control status is "forceoff" or "notsupported" writes
are rejected.
Facility in POWER9 and newer processors. i.e., it is a Secure
Virtual Machine.
-What: /sys/devices/system/cpu/cpuX/purr
+What: /sys/devices/system/cpu/cpuX/purr
Date: Apr 2005
Contact: Linux for PowerPC mailing list <linuxppc-dev@ozlabs.org>
Description: PURR ticks for this CPU since the system boot.
projects / linux-2.6-microblaze.git / blobdiff