+#define LTQ_WDT_CR_PW1 0x00BE0000
+#define LTQ_WDT_CR_PW2 0x00DC0000
+
+#define LTQ_WDT_CR 0x0 /* watchdog control register */
+#define LTQ_WDT_CR_GEN BIT(31) /* enable bit */
+/* Pre-warning limit set to 1/16 of max WDT period */
+#define LTQ_WDT_CR_PWL (0x3 << 26)
+/* set clock divider to 0x40000 */
+#define LTQ_WDT_CR_CLKDIV (0x3 << 24)
+#define LTQ_WDT_CR_PW_MASK GENMASK(23, 16) /* Password field */
+#define LTQ_WDT_CR_MAX_TIMEOUT ((1 << 16) - 1) /* The reload field is 16 bit */