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PCI: dwc: Remove root_bus pointer
[linux-2.6-microblaze.git]
/
drivers
/
pci
/
controller
/
dwc
/
pcie-tegra194.c
diff --git
a/drivers/pci/controller/dwc/pcie-tegra194.c
b/drivers/pci/controller/dwc/pcie-tegra194.c
index
7049868
..
a5dce56
100644
(file)
--- a/
drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/
drivers/pci/controller/dwc/pcie-tegra194.c
@@
-568,42
+568,44
@@
static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
return IRQ_HANDLED;
}
return IRQ_HANDLED;
}
-static int tegra_pcie_dw_rd_own_conf(struct pci
e_port *pp, int where, int siz
e,
- u32 *val)
+static int tegra_pcie_dw_rd_own_conf(struct pci
_bus *bus, u32 devfn, int wher
e,
+
int size,
u32 *val)
{
{
- struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-
/*
* This is an endpoint mode specific register happen to appear even
* when controller is operating in root port mode and system hangs
* when it is accessed with link being in ASPM-L1 state.
* So skip accessing it altogether
*/
/*
* This is an endpoint mode specific register happen to appear even
* when controller is operating in root port mode and system hangs
* when it is accessed with link being in ASPM-L1 state.
* So skip accessing it altogether
*/
- if (where == PORT_LOGIC_MSIX_DOORBELL) {
+ if (
!PCI_SLOT(devfn) &&
where == PORT_LOGIC_MSIX_DOORBELL) {
*val = 0x00000000;
return PCIBIOS_SUCCESSFUL;
}
*val = 0x00000000;
return PCIBIOS_SUCCESSFUL;
}
- return
dw_pcie_read(pci->dbi_base +
where, size, val);
+ return
pci_generic_config_read(bus, devfn,
where, size, val);
}
}
-static int tegra_pcie_dw_wr_own_conf(struct pci
e_port *pp, int where, int siz
e,
- u32 val)
+static int tegra_pcie_dw_wr_own_conf(struct pci
_bus *bus, u32 devfn, int wher
e,
+
int size,
u32 val)
{
{
- struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-
/*
* This is an endpoint mode specific register happen to appear even
* when controller is operating in root port mode and system hangs
* when it is accessed with link being in ASPM-L1 state.
* So skip accessing it altogether
*/
/*
* This is an endpoint mode specific register happen to appear even
* when controller is operating in root port mode and system hangs
* when it is accessed with link being in ASPM-L1 state.
* So skip accessing it altogether
*/
- if (where == PORT_LOGIC_MSIX_DOORBELL)
+ if (
!PCI_SLOT(devfn) &&
where == PORT_LOGIC_MSIX_DOORBELL)
return PCIBIOS_SUCCESSFUL;
return PCIBIOS_SUCCESSFUL;
- return
dw_pcie_write(pci->dbi_base +
where, size, val);
+ return
pci_generic_config_write(bus, devfn,
where, size, val);
}
}
+static struct pci_ops tegra_pci_ops = {
+ .map_bus = dw_pcie_own_conf_map_bus,
+ .read = tegra_pcie_dw_rd_own_conf,
+ .write = tegra_pcie_dw_wr_own_conf,
+};
+
#if defined(CONFIG_PCIEASPM)
static void disable_aspm_l11(struct tegra_pcie_dw *pcie)
{
#if defined(CONFIG_PCIEASPM)
static void disable_aspm_l11(struct tegra_pcie_dw *pcie)
{
@@
-970,6
+972,8
@@
static int tegra_pcie_dw_host_init(struct pcie_port *pp)
struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
u32 val, tmp, offset, speed;
struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
u32 val, tmp, offset, speed;
+ pp->bridge->ops = &tegra_pci_ops;
+
tegra_pcie_prepare_host(pp);
if (dw_pcie_wait_for_link(pci)) {
tegra_pcie_prepare_host(pp);
if (dw_pcie_wait_for_link(pci)) {
@@
-1057,8
+1061,6
@@
static const struct dw_pcie_ops tegra_dw_pcie_ops = {
};
static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = {
};
static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = {
- .rd_own_conf = tegra_pcie_dw_rd_own_conf,
- .wr_own_conf = tegra_pcie_dw_wr_own_conf,
.host_init = tegra_pcie_dw_host_init,
.set_num_vectors = tegra_pcie_set_msi_vec_num,
};
.host_init = tegra_pcie_dw_host_init,
.set_num_vectors = tegra_pcie_set_msi_vec_num,
};
@@
-1262,9
+1264,9
@@
static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
* 5.2 Link State Power Management (Page #428).
*/
* 5.2 Link State Power Management (Page #428).
*/
- list_for_each_entry(child, &pp->
root_
bus->children, node) {
+ list_for_each_entry(child, &pp->
bridge->
bus->children, node) {
/* Bring downstream devices to D0 if they are not already in */
/* Bring downstream devices to D0 if they are not already in */
- if (child->parent == pp->
root_
bus) {
+ if (child->parent == pp->
bridge->
bus) {
root_bus = child;
break;
}
root_bus = child;
break;
}