- tfr_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.tfr\
- .low));
- err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error\
- .low));
-
- dev_dbg(ap->dev, "eot=0x%08x err=0x%08x pending=%d active port=%d\n",
- tfr_reg, err_reg, hsdevp->dma_pending[tag], port);
-
- chan = host_pvt.dma_channel;
- if (chan >= 0) {
- /* Check for end-of-transfer interrupt. */
- if (tfr_reg & DMA_CHANNEL(chan)) {
- /*
- * Each DMA command produces 2 interrupts. Only
- * complete the command after both interrupts have been
- * seen. (See sata_dwc_isr())
- */
- host_pvt.dma_interrupt_count++;
- sata_dwc_clear_dmacr(hsdevp, tag);
-
- if (hsdevp->dma_pending[tag] ==
- SATA_DWC_DMA_PENDING_NONE) {
- dev_err(ap->dev, "DMA not pending eot=0x%08x "
- "err=0x%08x tag=0x%02x pending=%d\n",
- tfr_reg, err_reg, tag,
- hsdevp->dma_pending[tag]);
- }
-
- if ((host_pvt.dma_interrupt_count % 2) == 0)
- sata_dwc_dma_xfer_complete(ap, 1);
-
- /* Clear the interrupt */
- out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
- .tfr.low),
- DMA_CHANNEL(chan));
- }
-
- /* Check for error interrupt. */
- if (err_reg & DMA_CHANNEL(chan)) {
- /* TODO Need error handler ! */
- dev_err(ap->dev, "error interrupt err_reg=0x%08x\n",
- err_reg);
-
- /* Clear the interrupt. */
- out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
- .error.low),
- DMA_CHANNEL(chan));
- }
- }
- spin_unlock_irqrestore(&host->lock, flags);
- return IRQ_HANDLED;
-}
-
-/*
- * Function: dma_request_interrupts
- * arguments: hsdev
- * returns status
- * This function registers ISR for a particular DMA channel interrupt
- */
-static int dma_request_interrupts(struct sata_dwc_device *hsdev, int irq)
-{
- int retval = 0;
- int chan = host_pvt.dma_channel;
-
- if (chan >= 0) {
- /* Unmask error interrupt */
- out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.error.low,
- DMA_ENABLE_CHAN(chan));
-
- /* Unmask end-of-transfer interrupt */
- out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.tfr.low,
- DMA_ENABLE_CHAN(chan));
- }
-
- retval = request_irq(irq, dma_dwc_interrupt, 0, "SATA DMA", hsdev);
- if (retval) {
- dev_err(host_pvt.dwc_dev, "%s: could not get IRQ %d\n",
- __func__, irq);
- return -ENODEV;
- }
-
- /* Mark this interrupt as requested */
- hsdev->irq_dma = irq;
- return 0;
-}
-
-/*
- * Function: map_sg_to_lli
- * The Synopsis driver has a comment proposing that better performance
- * is possible by only enabling interrupts on the last item in the linked list.
- * However, it seems that could be a problem if an error happened on one of the
- * first items. The transfer would halt, but no error interrupt would occur.
- * Currently this function sets interrupts enabled for each linked list item:
- * DMA_CTL_INT_EN.
- */
-static int map_sg_to_lli(struct scatterlist *sg, int num_elems,
- struct lli *lli, dma_addr_t dma_lli,
- void __iomem *dmadr_addr, int dir)
-{
- int i, idx = 0;
- int fis_len = 0;
- dma_addr_t next_llp;
- int bl;
- int sms_val, dms_val;
-
- sms_val = 0;
- dms_val = 1 + host_pvt.dma_channel;
- dev_dbg(host_pvt.dwc_dev,
- "%s: sg=%p nelem=%d lli=%p dma_lli=0x%pad dmadr=0x%p\n",
- __func__, sg, num_elems, lli, &dma_lli, dmadr_addr);
-
- bl = get_burst_length_encode(AHB_DMA_BRST_DFLT);
-
- for (i = 0; i < num_elems; i++, sg++) {
- u32 addr, offset;
- u32 sg_len, len;
-
- addr = (u32) sg_dma_address(sg);
- sg_len = sg_dma_len(sg);
-
- dev_dbg(host_pvt.dwc_dev, "%s: elem=%d sg_addr=0x%x sg_len"
- "=%d\n", __func__, i, addr, sg_len);
-
- while (sg_len) {
- if (idx >= SATA_DWC_DMAC_LLI_NUM) {
- /* The LLI table is not large enough. */
- dev_err(host_pvt.dwc_dev, "LLI table overrun "
- "(idx=%d)\n", idx);
- break;
- }
- len = (sg_len > SATA_DWC_DMAC_CTRL_TSIZE_MAX) ?
- SATA_DWC_DMAC_CTRL_TSIZE_MAX : sg_len;
-
- offset = addr & 0xffff;
- if ((offset + sg_len) > 0x10000)
- len = 0x10000 - offset;
-
- /*
- * Make sure a LLI block is not created that will span
- * 8K max FIS boundary. If the block spans such a FIS
- * boundary, there is a chance that a DMA burst will
- * cross that boundary -- this results in an error in
- * the host controller.
- */
- if (fis_len + len > 8192) {
- dev_dbg(host_pvt.dwc_dev, "SPLITTING: fis_len="
- "%d(0x%x) len=%d(0x%x)\n", fis_len,
- fis_len, len, len);
- len = 8192 - fis_len;
- fis_len = 0;
- } else {
- fis_len += len;
- }
- if (fis_len == 8192)
- fis_len = 0;
-
- /*
- * Set DMA addresses and lower half of control register
- * based on direction.
- */
- if (dir == DMA_FROM_DEVICE) {
- lli[idx].dar = cpu_to_le32(addr);
- lli[idx].sar = cpu_to_le32((u32)dmadr_addr);
-
- lli[idx].ctl.low = cpu_to_le32(
- DMA_CTL_TTFC(DMA_CTL_TTFC_P2M_DMAC) |
- DMA_CTL_SMS(sms_val) |
- DMA_CTL_DMS(dms_val) |
- DMA_CTL_SRC_MSIZE(bl) |
- DMA_CTL_DST_MSIZE(bl) |
- DMA_CTL_SINC_NOCHANGE |
- DMA_CTL_SRC_TRWID(2) |
- DMA_CTL_DST_TRWID(2) |
- DMA_CTL_INT_EN |
- DMA_CTL_LLP_SRCEN |
- DMA_CTL_LLP_DSTEN);
- } else { /* DMA_TO_DEVICE */
- lli[idx].sar = cpu_to_le32(addr);
- lli[idx].dar = cpu_to_le32((u32)dmadr_addr);
-
- lli[idx].ctl.low = cpu_to_le32(
- DMA_CTL_TTFC(DMA_CTL_TTFC_M2P_PER) |
- DMA_CTL_SMS(dms_val) |
- DMA_CTL_DMS(sms_val) |
- DMA_CTL_SRC_MSIZE(bl) |
- DMA_CTL_DST_MSIZE(bl) |
- DMA_CTL_DINC_NOCHANGE |
- DMA_CTL_SRC_TRWID(2) |
- DMA_CTL_DST_TRWID(2) |
- DMA_CTL_INT_EN |
- DMA_CTL_LLP_SRCEN |
- DMA_CTL_LLP_DSTEN);
- }
-
- dev_dbg(host_pvt.dwc_dev, "%s setting ctl.high len: "
- "0x%08x val: 0x%08x\n", __func__,
- len, DMA_CTL_BLK_TS(len / 4));
-
- /* Program the LLI CTL high register */
- lli[idx].ctl.high = cpu_to_le32(DMA_CTL_BLK_TS\
- (len / 4));
-
- /* Program the next pointer. The next pointer must be
- * the physical address, not the virtual address.
- */
- next_llp = (dma_lli + ((idx + 1) * sizeof(struct \
- lli)));
-
- /* The last 2 bits encode the list master select. */
- next_llp = DMA_LLP_LMS(next_llp, DMA_LLP_AHBMASTER2);
-
- lli[idx].llp = cpu_to_le32(next_llp);
- idx++;
- sg_len -= len;
- addr += len;
- }
- }
-