+struct ixp4xx_pata {
+ struct ata_host *host;
+ struct regmap *rmap;
+ u32 cmd_csreg;
+ void __iomem *cmd;
+ void __iomem *ctl;
+};
+
+#define IXP4XX_EXP_TIMING_STRIDE 0x04
+/* The timings for the chipselect is in bits 29..16 */
+#define IXP4XX_EXP_T1_T5_MASK GENMASK(29, 16)
+#define IXP4XX_EXP_PIO_0_8 0x0a470000
+#define IXP4XX_EXP_PIO_1_8 0x06430000
+#define IXP4XX_EXP_PIO_2_8 0x02410000
+#define IXP4XX_EXP_PIO_3_8 0x00820000
+#define IXP4XX_EXP_PIO_4_8 0x00400000
+#define IXP4XX_EXP_PIO_0_16 0x29640000
+#define IXP4XX_EXP_PIO_1_16 0x05030000
+#define IXP4XX_EXP_PIO_2_16 0x00b20000
+#define IXP4XX_EXP_PIO_3_16 0x00820000
+#define IXP4XX_EXP_PIO_4_16 0x00400000
+#define IXP4XX_EXP_BW_MASK (BIT(6)|BIT(0))
+#define IXP4XX_EXP_BYTE_RD16 BIT(6) /* Byte reads on half-word devices */
+#define IXP4XX_EXP_BYTE_EN BIT(0) /* Use 8bit data bus if set */
+
+static void ixp4xx_set_8bit_timing(struct ixp4xx_pata *ixpp, u8 pio_mode)
+{
+ switch (pio_mode) {
+ case XFER_PIO_0:
+ regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+ IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_0_8);
+ break;
+ case XFER_PIO_1:
+ regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+ IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_1_8);
+ break;
+ case XFER_PIO_2:
+ regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+ IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_2_8);
+ break;
+ case XFER_PIO_3:
+ regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+ IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_3_8);
+ break;
+ case XFER_PIO_4:
+ regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+ IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_4_8);
+ break;
+ default:
+ break;
+ }
+ regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+ IXP4XX_EXP_BW_MASK, IXP4XX_EXP_BYTE_RD16|IXP4XX_EXP_BYTE_EN);
+}
+
+static void ixp4xx_set_16bit_timing(struct ixp4xx_pata *ixpp, u8 pio_mode)