2 * Copyright (C) 2015, 2016 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __KVM_ARM_VGIC_NEW_H__
17 #define __KVM_ARM_VGIC_NEW_H__
19 #include <linux/irqchip/arm-gic-common.h>
21 #define PRODUCT_ID_KVM 0x4b /* ASCII code K */
22 #define IMPLEMENTER_ARM 0x43b
24 #define VGIC_ADDR_UNDEF (-1)
25 #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
27 #define INTERRUPT_ID_BITS_SPIS 10
28 #define INTERRUPT_ID_BITS_ITS 16
29 #define VGIC_PRI_BITS 5
31 #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
33 #define VGIC_AFFINITY_0_SHIFT 0
34 #define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
35 #define VGIC_AFFINITY_1_SHIFT 8
36 #define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
37 #define VGIC_AFFINITY_2_SHIFT 16
38 #define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
39 #define VGIC_AFFINITY_3_SHIFT 24
40 #define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)
42 #define VGIC_AFFINITY_LEVEL(reg, level) \
43 ((((reg) & VGIC_AFFINITY_## level ##_MASK) \
44 >> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
47 * The Userspace encodes the affinity differently from the MPIDR,
48 * Below macro converts vgic userspace format to MPIDR reg format.
50 #define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \
51 VGIC_AFFINITY_LEVEL(val, 1) | \
52 VGIC_AFFINITY_LEVEL(val, 2) | \
53 VGIC_AFFINITY_LEVEL(val, 3))
56 * As per Documentation/virtual/kvm/devices/arm-vgic-v3.txt,
57 * below macros are defined for CPUREG encoding.
59 #define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK 0x000000000000c000
60 #define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT 14
61 #define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK 0x0000000000003800
62 #define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT 11
63 #define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK 0x0000000000000780
64 #define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT 7
65 #define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK 0x0000000000000078
66 #define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT 3
67 #define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK 0x0000000000000007
68 #define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT 0
70 #define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \
71 KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \
72 KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \
73 KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \
74 KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)
77 * As per Documentation/virtual/kvm/devices/arm-vgic-its.txt,
78 * below macros are defined for ITS table entry encoding.
80 #define KVM_ITS_CTE_VALID_SHIFT 63
81 #define KVM_ITS_CTE_VALID_MASK BIT_ULL(63)
82 #define KVM_ITS_CTE_RDBASE_SHIFT 16
83 #define KVM_ITS_CTE_ICID_MASK GENMASK_ULL(15, 0)
84 #define KVM_ITS_ITE_NEXT_SHIFT 48
85 #define KVM_ITS_ITE_PINTID_SHIFT 16
86 #define KVM_ITS_ITE_PINTID_MASK GENMASK_ULL(47, 16)
87 #define KVM_ITS_ITE_ICID_MASK GENMASK_ULL(15, 0)
88 #define KVM_ITS_DTE_VALID_SHIFT 63
89 #define KVM_ITS_DTE_VALID_MASK BIT_ULL(63)
90 #define KVM_ITS_DTE_NEXT_SHIFT 49
91 #define KVM_ITS_DTE_NEXT_MASK GENMASK_ULL(62, 49)
92 #define KVM_ITS_DTE_ITTADDR_SHIFT 5
93 #define KVM_ITS_DTE_ITTADDR_MASK GENMASK_ULL(48, 5)
94 #define KVM_ITS_DTE_SIZE_MASK GENMASK_ULL(4, 0)
95 #define KVM_ITS_L1E_VALID_MASK BIT_ULL(63)
96 /* we only support 64 kB translation table page size */
97 #define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16)
99 /* Requires the irq_lock to be held by the caller. */
100 static inline bool irq_is_pending(struct vgic_irq *irq)
102 if (irq->config == VGIC_CONFIG_EDGE)
103 return irq->pending_latch;
105 return irq->pending_latch || irq->line_level;
108 static inline bool vgic_irq_is_mapped_level(struct vgic_irq *irq)
110 return irq->config == VGIC_CONFIG_LEVEL && irq->hw;
113 static inline int vgic_irq_get_lr_count(struct vgic_irq *irq)
115 /* Account for the active state as an interrupt */
116 if (vgic_irq_is_sgi(irq->intid) && irq->source)
117 return hweight8(irq->source) + irq->active;
119 return irq_is_pending(irq) || irq->active;
122 static inline bool vgic_irq_is_multi_sgi(struct vgic_irq *irq)
124 return vgic_irq_get_lr_count(irq) > 1;
128 * This struct provides an intermediate representation of the fields contained
129 * in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC
130 * state to userspace can generate either GICv2 or GICv3 CPU interface
131 * registers regardless of the hardware backed GIC used.
144 u32 pmr; /* Priority mask field in the GICC_PMR and
145 * ICC_PMR_EL1 priority field format */
148 struct vgic_reg_attr {
149 struct kvm_vcpu *vcpu;
153 int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
154 struct vgic_reg_attr *reg_attr);
155 int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
156 struct vgic_reg_attr *reg_attr);
157 const struct vgic_register_region *
158 vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
159 gpa_t addr, int len);
160 struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
162 void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq);
163 bool vgic_get_phys_line_level(struct vgic_irq *irq);
164 void vgic_irq_set_phys_pending(struct vgic_irq *irq, bool pending);
165 void vgic_irq_set_phys_active(struct vgic_irq *irq, bool active);
166 bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq,
167 unsigned long flags);
168 void vgic_kick_vcpus(struct kvm *kvm);
170 int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr,
171 phys_addr_t addr, phys_addr_t alignment);
173 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
174 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
175 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
176 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
177 void vgic_v2_set_npie(struct kvm_vcpu *vcpu);
178 int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
179 int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
180 int offset, u32 *val);
181 int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
182 int offset, u32 *val);
183 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
184 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
185 void vgic_v2_enable(struct kvm_vcpu *vcpu);
186 int vgic_v2_probe(const struct gic_kvm_info *info);
187 int vgic_v2_map_resources(struct kvm *kvm);
188 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
191 void vgic_v2_init_lrs(void);
192 void vgic_v2_load(struct kvm_vcpu *vcpu);
193 void vgic_v2_put(struct kvm_vcpu *vcpu);
195 void vgic_v2_save_state(struct kvm_vcpu *vcpu);
196 void vgic_v2_restore_state(struct kvm_vcpu *vcpu);
198 static inline void vgic_get_irq_kref(struct vgic_irq *irq)
200 if (irq->intid < VGIC_MIN_LPI)
203 kref_get(&irq->refcount);
206 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
207 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
208 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
209 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
210 void vgic_v3_set_npie(struct kvm_vcpu *vcpu);
211 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
212 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
213 void vgic_v3_enable(struct kvm_vcpu *vcpu);
214 int vgic_v3_probe(const struct gic_kvm_info *info);
215 int vgic_v3_map_resources(struct kvm *kvm);
216 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq);
217 int vgic_v3_save_pending_tables(struct kvm *kvm);
218 int vgic_v3_set_redist_base(struct kvm *kvm, u64 addr);
219 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu);
220 bool vgic_v3_check_base(struct kvm *kvm);
222 void vgic_v3_load(struct kvm_vcpu *vcpu);
223 void vgic_v3_put(struct kvm_vcpu *vcpu);
225 bool vgic_has_its(struct kvm *kvm);
226 int kvm_vgic_register_its_device(void);
227 void vgic_enable_lpis(struct kvm_vcpu *vcpu);
228 int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
229 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
230 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
231 int offset, u32 *val);
232 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
233 int offset, u32 *val);
234 int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write,
236 int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
238 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
239 u32 intid, u64 *val);
240 int kvm_register_vgic_device(unsigned long type);
241 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
242 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
243 int vgic_lazy_init(struct kvm *kvm);
244 int vgic_init(struct kvm *kvm);
246 int vgic_debug_init(struct kvm *kvm);
247 int vgic_debug_destroy(struct kvm *kvm);
249 bool lock_all_vcpus(struct kvm *kvm);
250 void unlock_all_vcpus(struct kvm *kvm);
252 static inline int vgic_v3_max_apr_idx(struct kvm_vcpu *vcpu)
254 struct vgic_cpu *cpu_if = &vcpu->arch.vgic_cpu;
257 * num_pri_bits are initialized with HW supported values.
258 * We can rely safely on num_pri_bits even if VM has not
259 * restored ICC_CTLR_EL1 before restoring APnR registers.
261 switch (cpu_if->num_pri_bits) {
268 int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its,
269 u32 devid, u32 eventid, struct vgic_irq **irq);
270 struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi);
272 bool vgic_supports_direct_msis(struct kvm *kvm);
273 int vgic_v4_init(struct kvm *kvm);
274 void vgic_v4_teardown(struct kvm *kvm);
275 int vgic_v4_sync_hwstate(struct kvm_vcpu *vcpu);
276 int vgic_v4_flush_hwstate(struct kvm_vcpu *vcpu);