virt/kvm/arm/vgic/vgic-mmio.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * VGIC MMIO handling functions
   4  */
   5
   6 #include <linux/bitops.h>
   7 #include <linux/bsearch.h>
   8 #include <linux/kvm.h>
   9 #include <linux/kvm_host.h>
  10 #include <kvm/iodev.h>
  11 #include <kvm/arm_arch_timer.h>
  12 #include <kvm/arm_vgic.h>
  13
  14 #include "vgic.h"
  15 #include "vgic-mmio.h"
  16
  17 unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
  18                                  gpa_t addr, unsigned int len)
  19 {
  20         return 0;
  21 }
  22
  23 unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
  24                                  gpa_t addr, unsigned int len)
  25 {
  26         return -1UL;
  27 }
  28
  29 void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
  30                         unsigned int len, unsigned long val)
  31 {
  32         /* Ignore */
  33 }
  34
  35 int vgic_mmio_uaccess_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
  36                                unsigned int len, unsigned long val)
  37 {
  38         /* Ignore */
  39         return 0;
  40 }
  41
  42 unsigned long vgic_mmio_read_group(struct kvm_vcpu *vcpu,
  43                                    gpa_t addr, unsigned int len)
  44 {
  45         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
  46         u32 value = 0;
  47         int i;
  48
  49         /* Loop over all IRQs affected by this read */
  50         for (i = 0; i < len * 8; i++) {
  51                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
  52
  53                 if (irq->group)
  54                         value |= BIT(i);
  55
  56                 vgic_put_irq(vcpu->kvm, irq);
  57         }
  58
  59         return value;
  60 }
  61
  62 void vgic_mmio_write_group(struct kvm_vcpu *vcpu, gpa_t addr,
  63                            unsigned int len, unsigned long val)
  64 {
  65         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
  66         int i;
  67         unsigned long flags;
  68
  69         for (i = 0; i < len * 8; i++) {
  70                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
  71
  72                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
  73                 irq->group = !!(val & BIT(i));
  74                 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
  75
  76                 vgic_put_irq(vcpu->kvm, irq);
  77         }
  78 }
  79
  80 /*
  81  * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value
  82  * of the enabled bit, so there is only one function for both here.
  83  */
  84 unsigned long vgic_mmio_read_enable(struct kvm_vcpu *vcpu,
  85                                     gpa_t addr, unsigned int len)
  86 {
  87         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
  88         u32 value = 0;
  89         int i;
  90
  91         /* Loop over all IRQs affected by this read */
  92         for (i = 0; i < len * 8; i++) {
  93                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
  94
  95                 if (irq->enabled)
  96                         value |= (1U << i);
  97
  98                 vgic_put_irq(vcpu->kvm, irq);
  99         }
 100
 101         return value;
 102 }
 103
 104 void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
 105                              gpa_t addr, unsigned int len,
 106                              unsigned long val)
 107 {
 108         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 109         int i;
 110         unsigned long flags;
 111
 112         for_each_set_bit(i, &val, len * 8) {
 113                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 114
 115                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 116                 if (vgic_irq_is_mapped_level(irq)) {
 117                         bool was_high = irq->line_level;
 118
 119                         /*
 120                          * We need to update the state of the interrupt because
 121                          * the guest might have changed the state of the device
 122                          * while the interrupt was disabled at the VGIC level.
 123                          */
 124                         irq->line_level = vgic_get_phys_line_level(irq);
 125                         /*
 126                          * Deactivate the physical interrupt so the GIC will let
 127                          * us know when it is asserted again.
 128                          */
 129                         if (!irq->active && was_high && !irq->line_level)
 130                                 vgic_irq_set_phys_active(irq, false);
 131                 }
 132                 irq->enabled = true;
 133                 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 134
 135                 vgic_put_irq(vcpu->kvm, irq);
 136         }
 137 }
 138
 139 void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
 140                              gpa_t addr, unsigned int len,
 141                              unsigned long val)
 142 {
 143         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 144         int i;
 145         unsigned long flags;
 146
 147         for_each_set_bit(i, &val, len * 8) {
 148                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 149
 150                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 151
 152                 irq->enabled = false;
 153
 154                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 155                 vgic_put_irq(vcpu->kvm, irq);
 156         }
 157 }
 158
 159 unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
 160                                      gpa_t addr, unsigned int len)
 161 {
 162         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 163         u32 value = 0;
 164         int i;
 165
 166         /* Loop over all IRQs affected by this read */
 167         for (i = 0; i < len * 8; i++) {
 168                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 169                 unsigned long flags;
 170
 171                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 172                 if (irq_is_pending(irq))
 173                         value |= (1U << i);
 174                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 175
 176                 vgic_put_irq(vcpu->kvm, irq);
 177         }
 178
 179         return value;
 180 }
 181
 182 /*
 183  * This function will return the VCPU that performed the MMIO access and
 184  * trapped from within the VM, and will return NULL if this is a userspace
 185  * access.
 186  *
 187  * We can disable preemption locally around accessing the per-CPU variable,
 188  * and use the resolved vcpu pointer after enabling preemption again, because
 189  * even if the current thread is migrated to another CPU, reading the per-CPU
 190  * value later will give us the same value as we update the per-CPU variable
 191  * in the preempt notifier handlers.
 192  */
 193
 194 /* Must be called with irq->irq_lock held */
 195 static void vgic_hw_irq_spending(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
 196                                  bool is_uaccess)
 197 {
 198         if (is_uaccess)
 199                 return;
 200
 201         irq->pending_latch = true;
 202         vgic_irq_set_phys_active(irq, true);
 203 }
 204
 205 static bool is_vgic_v2_sgi(struct kvm_vcpu *vcpu, struct vgic_irq *irq)
 206 {
 207         return (vgic_irq_is_sgi(irq->intid) &&
 208                 vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2);
 209 }
 210
 211 void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
 212                               gpa_t addr, unsigned int len,
 213                               unsigned long val)
 214 {
 215         bool is_uaccess = !kvm_get_running_vcpu();
 216         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 217         int i;
 218         unsigned long flags;
 219
 220         for_each_set_bit(i, &val, len * 8) {
 221                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 222
 223                 /* GICD_ISPENDR0 SGI bits are WI */
 224                 if (is_vgic_v2_sgi(vcpu, irq)) {
 225                         vgic_put_irq(vcpu->kvm, irq);
 226                         continue;
 227                 }
 228
 229                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 230                 if (irq->hw)
 231                         vgic_hw_irq_spending(vcpu, irq, is_uaccess);
 232                 else
 233                         irq->pending_latch = true;
 234                 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 235                 vgic_put_irq(vcpu->kvm, irq);
 236         }
 237 }
 238
 239 /* Must be called with irq->irq_lock held */
 240 static void vgic_hw_irq_cpending(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
 241                                  bool is_uaccess)
 242 {
 243         if (is_uaccess)
 244                 return;
 245
 246         irq->pending_latch = false;
 247
 248         /*
 249          * We don't want the guest to effectively mask the physical
 250          * interrupt by doing a write to SPENDR followed by a write to
 251          * CPENDR for HW interrupts, so we clear the active state on
 252          * the physical side if the virtual interrupt is not active.
 253          * This may lead to taking an additional interrupt on the
 254          * host, but that should not be a problem as the worst that
 255          * can happen is an additional vgic injection.  We also clear
 256          * the pending state to maintain proper semantics for edge HW
 257          * interrupts.
 258          */
 259         vgic_irq_set_phys_pending(irq, false);
 260         if (!irq->active)
 261                 vgic_irq_set_phys_active(irq, false);
 262 }
 263
 264 void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
 265                               gpa_t addr, unsigned int len,
 266                               unsigned long val)
 267 {
 268         bool is_uaccess = !kvm_get_running_vcpu();
 269         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 270         int i;
 271         unsigned long flags;
 272
 273         for_each_set_bit(i, &val, len * 8) {
 274                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 275
 276                 /* GICD_ICPENDR0 SGI bits are WI */
 277                 if (is_vgic_v2_sgi(vcpu, irq)) {
 278                         vgic_put_irq(vcpu->kvm, irq);
 279                         continue;
 280                 }
 281
 282                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 283
 284                 if (irq->hw)
 285                         vgic_hw_irq_cpending(vcpu, irq, is_uaccess);
 286                 else
 287                         irq->pending_latch = false;
 288
 289                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 290                 vgic_put_irq(vcpu->kvm, irq);
 291         }
 292 }
 293
 294 unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
 295                                     gpa_t addr, unsigned int len)
 296 {
 297         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 298         u32 value = 0;
 299         int i;
 300
 301         /* Loop over all IRQs affected by this read */
 302         for (i = 0; i < len * 8; i++) {
 303                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 304
 305                 if (irq->active)
 306                         value |= (1U << i);
 307
 308                 vgic_put_irq(vcpu->kvm, irq);
 309         }
 310
 311         return value;
 312 }
 313
 314 /* Must be called with irq->irq_lock held */
 315 static void vgic_hw_irq_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
 316                                       bool active, bool is_uaccess)
 317 {
 318         if (is_uaccess)
 319                 return;
 320
 321         irq->active = active;
 322         vgic_irq_set_phys_active(irq, active);
 323 }
 324
 325 static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
 326                                     bool active)
 327 {
 328         unsigned long flags;
 329         struct kvm_vcpu *requester_vcpu = kvm_get_running_vcpu();
 330
 331         raw_spin_lock_irqsave(&irq->irq_lock, flags);
 332
 333         if (irq->hw) {
 334                 vgic_hw_irq_change_active(vcpu, irq, active, !requester_vcpu);
 335         } else {
 336                 u32 model = vcpu->kvm->arch.vgic.vgic_model;
 337                 u8 active_source;
 338
 339                 irq->active = active;
 340
 341                 /*
 342                  * The GICv2 architecture indicates that the source CPUID for
 343                  * an SGI should be provided during an EOI which implies that
 344                  * the active state is stored somewhere, but at the same time
 345                  * this state is not architecturally exposed anywhere and we
 346                  * have no way of knowing the right source.
 347                  *
 348                  * This may lead to a VCPU not being able to receive
 349                  * additional instances of a particular SGI after migration
 350                  * for a GICv2 VM on some GIC implementations.  Oh well.
 351                  */
 352                 active_source = (requester_vcpu) ? requester_vcpu->vcpu_id : 0;
 353
 354                 if (model == KVM_DEV_TYPE_ARM_VGIC_V2 &&
 355                     active && vgic_irq_is_sgi(irq->intid))
 356                         irq->active_source = active_source;
 357         }
 358
 359         if (irq->active)
 360                 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 361         else
 362                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 363 }
 364
 365 /*
 366  * If we are fiddling with an IRQ's active state, we have to make sure the IRQ
 367  * is not queued on some running VCPU's LRs, because then the change to the
 368  * active state can be overwritten when the VCPU's state is synced coming back
 369  * from the guest.
 370  *
 371  * For shared interrupts, we have to stop all the VCPUs because interrupts can
 372  * be migrated while we don't hold the IRQ locks and we don't want to be
 373  * chasing moving targets.
 374  *
 375  * For private interrupts we don't have to do anything because userspace
 376  * accesses to the VGIC state already require all VCPUs to be stopped, and
 377  * only the VCPU itself can modify its private interrupts active state, which
 378  * guarantees that the VCPU is not running.
 379  */
 380 static void vgic_change_active_prepare(struct kvm_vcpu *vcpu, u32 intid)
 381 {
 382         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3 ||
 383             intid > VGIC_NR_PRIVATE_IRQS)
 384                 kvm_arm_halt_guest(vcpu->kvm);
 385 }
 386
 387 /* See vgic_change_active_prepare */
 388 static void vgic_change_active_finish(struct kvm_vcpu *vcpu, u32 intid)
 389 {
 390         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3 ||
 391             intid > VGIC_NR_PRIVATE_IRQS)
 392                 kvm_arm_resume_guest(vcpu->kvm);
 393 }
 394
 395 static void __vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
 396                                       gpa_t addr, unsigned int len,
 397                                       unsigned long val)
 398 {
 399         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 400         int i;
 401
 402         for_each_set_bit(i, &val, len * 8) {
 403                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 404                 vgic_mmio_change_active(vcpu, irq, false);
 405                 vgic_put_irq(vcpu->kvm, irq);
 406         }
 407 }
 408
 409 void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
 410                              gpa_t addr, unsigned int len,
 411                              unsigned long val)
 412 {
 413         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 414
 415         mutex_lock(&vcpu->kvm->lock);
 416         vgic_change_active_prepare(vcpu, intid);
 417
 418         __vgic_mmio_write_cactive(vcpu, addr, len, val);
 419
 420         vgic_change_active_finish(vcpu, intid);
 421         mutex_unlock(&vcpu->kvm->lock);
 422 }
 423
 424 int vgic_mmio_uaccess_write_cactive(struct kvm_vcpu *vcpu,
 425                                      gpa_t addr, unsigned int len,
 426                                      unsigned long val)
 427 {
 428         __vgic_mmio_write_cactive(vcpu, addr, len, val);
 429         return 0;
 430 }
 431
 432 static void __vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
 433                                       gpa_t addr, unsigned int len,
 434                                       unsigned long val)
 435 {
 436         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 437         int i;
 438
 439         for_each_set_bit(i, &val, len * 8) {
 440                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 441                 vgic_mmio_change_active(vcpu, irq, true);
 442                 vgic_put_irq(vcpu->kvm, irq);
 443         }
 444 }
 445
 446 void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
 447                              gpa_t addr, unsigned int len,
 448                              unsigned long val)
 449 {
 450         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 451
 452         mutex_lock(&vcpu->kvm->lock);
 453         vgic_change_active_prepare(vcpu, intid);
 454
 455         __vgic_mmio_write_sactive(vcpu, addr, len, val);
 456
 457         vgic_change_active_finish(vcpu, intid);
 458         mutex_unlock(&vcpu->kvm->lock);
 459 }
 460
 461 int vgic_mmio_uaccess_write_sactive(struct kvm_vcpu *vcpu,
 462                                      gpa_t addr, unsigned int len,
 463                                      unsigned long val)
 464 {
 465         __vgic_mmio_write_sactive(vcpu, addr, len, val);
 466         return 0;
 467 }
 468
 469 unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
 470                                       gpa_t addr, unsigned int len)
 471 {
 472         u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
 473         int i;
 474         u64 val = 0;
 475
 476         for (i = 0; i < len; i++) {
 477                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 478
 479                 val |= (u64)irq->priority << (i * 8);
 480
 481                 vgic_put_irq(vcpu->kvm, irq);
 482         }
 483
 484         return val;
 485 }
 486
 487 /*
 488  * We currently don't handle changing the priority of an interrupt that
 489  * is already pending on a VCPU. If there is a need for this, we would
 490  * need to make this VCPU exit and re-evaluate the priorities, potentially
 491  * leading to this interrupt getting presented now to the guest (if it has
 492  * been masked by the priority mask before).
 493  */
 494 void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
 495                               gpa_t addr, unsigned int len,
 496                               unsigned long val)
 497 {
 498         u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
 499         int i;
 500         unsigned long flags;
 501
 502         for (i = 0; i < len; i++) {
 503                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 504
 505                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 506                 /* Narrow the priority range to what we actually support */
 507                 irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);
 508                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 509
 510                 vgic_put_irq(vcpu->kvm, irq);
 511         }
 512 }
 513
 514 unsigned long vgic_mmio_read_config(struct kvm_vcpu *vcpu,
 515                                     gpa_t addr, unsigned int len)
 516 {
 517         u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
 518         u32 value = 0;
 519         int i;
 520
 521         for (i = 0; i < len * 4; i++) {
 522                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 523
 524                 if (irq->config == VGIC_CONFIG_EDGE)
 525                         value |= (2U << (i * 2));
 526
 527                 vgic_put_irq(vcpu->kvm, irq);
 528         }
 529
 530         return value;
 531 }
 532
 533 void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
 534                             gpa_t addr, unsigned int len,
 535                             unsigned long val)
 536 {
 537         u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
 538         int i;
 539         unsigned long flags;
 540
 541         for (i = 0; i < len * 4; i++) {
 542                 struct vgic_irq *irq;
 543
 544                 /*
 545                  * The configuration cannot be changed for SGIs in general,
 546                  * for PPIs this is IMPLEMENTATION DEFINED. The arch timer
 547                  * code relies on PPIs being level triggered, so we also
 548                  * make them read-only here.
 549                  */
 550                 if (intid + i < VGIC_NR_PRIVATE_IRQS)
 551                         continue;
 552
 553                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 554                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 555
 556                 if (test_bit(i * 2 + 1, &val))
 557                         irq->config = VGIC_CONFIG_EDGE;
 558                 else
 559                         irq->config = VGIC_CONFIG_LEVEL;
 560
 561                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 562                 vgic_put_irq(vcpu->kvm, irq);
 563         }
 564 }
 565
 566 u64 vgic_read_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid)
 567 {
 568         int i;
 569         u64 val = 0;
 570         int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
 571
 572         for (i = 0; i < 32; i++) {
 573                 struct vgic_irq *irq;
 574
 575                 if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
 576                         continue;
 577
 578                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 579                 if (irq->config == VGIC_CONFIG_LEVEL && irq->line_level)
 580                         val |= (1U << i);
 581
 582                 vgic_put_irq(vcpu->kvm, irq);
 583         }
 584
 585         return val;
 586 }
 587
 588 void vgic_write_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid,
 589                                     const u64 val)
 590 {
 591         int i;
 592         int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
 593         unsigned long flags;
 594
 595         for (i = 0; i < 32; i++) {
 596                 struct vgic_irq *irq;
 597                 bool new_level;
 598
 599                 if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
 600                         continue;
 601
 602                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 603
 604                 /*
 605                  * Line level is set irrespective of irq type
 606                  * (level or edge) to avoid dependency that VM should
 607                  * restore irq config before line level.
 608                  */
 609                 new_level = !!(val & (1U << i));
 610                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 611                 irq->line_level = new_level;
 612                 if (new_level)
 613                         vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 614                 else
 615                         raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 616
 617                 vgic_put_irq(vcpu->kvm, irq);
 618         }
 619 }
 620
 621 static int match_region(const void *key, const void *elt)
 622 {
 623         const unsigned int offset = (unsigned long)key;
 624         const struct vgic_register_region *region = elt;
 625
 626         if (offset < region->reg_offset)
 627                 return -1;
 628
 629         if (offset >= region->reg_offset + region->len)
 630                 return 1;
 631
 632         return 0;
 633 }
 634
 635 const struct vgic_register_region *
 636 vgic_find_mmio_region(const struct vgic_register_region *regions,
 637                       int nr_regions, unsigned int offset)
 638 {
 639         return bsearch((void *)(uintptr_t)offset, regions, nr_regions,
 640                        sizeof(regions[0]), match_region);
 641 }
 642
 643 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
 644 {
 645         if (kvm_vgic_global_state.type == VGIC_V2)
 646                 vgic_v2_set_vmcr(vcpu, vmcr);
 647         else
 648                 vgic_v3_set_vmcr(vcpu, vmcr);
 649 }
 650
 651 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
 652 {
 653         if (kvm_vgic_global_state.type == VGIC_V2)
 654                 vgic_v2_get_vmcr(vcpu, vmcr);
 655         else
 656                 vgic_v3_get_vmcr(vcpu, vmcr);
 657 }
 658
 659 /*
 660  * kvm_mmio_read_buf() returns a value in a format where it can be converted
 661  * to a byte array and be directly observed as the guest wanted it to appear
 662  * in memory if it had done the store itself, which is LE for the GIC, as the
 663  * guest knows the GIC is always LE.
 664  *
 665  * We convert this value to the CPUs native format to deal with it as a data
 666  * value.
 667  */
 668 unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len)
 669 {
 670         unsigned long data = kvm_mmio_read_buf(val, len);
 671
 672         switch (len) {
 673         case 1:
 674                 return data;
 675         case 2:
 676                 return le16_to_cpu(data);
 677         case 4:
 678                 return le32_to_cpu(data);
 679         default:
 680                 return le64_to_cpu(data);
 681         }
 682 }
 683
 684 /*
 685  * kvm_mmio_write_buf() expects a value in a format such that if converted to
 686  * a byte array it is observed as the guest would see it if it could perform
 687  * the load directly.  Since the GIC is LE, and the guest knows this, the
 688  * guest expects a value in little endian format.
 689  *
 690  * We convert the data value from the CPUs native format to LE so that the
 691  * value is returned in the proper format.
 692  */
 693 void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
 694                                 unsigned long data)
 695 {
 696         switch (len) {
 697         case 1:
 698                 break;
 699         case 2:
 700                 data = cpu_to_le16(data);
 701                 break;
 702         case 4:
 703                 data = cpu_to_le32(data);
 704                 break;
 705         default:
 706                 data = cpu_to_le64(data);
 707         }
 708
 709         kvm_mmio_write_buf(buf, len, data);
 710 }
 711
 712 static
 713 struct vgic_io_device *kvm_to_vgic_iodev(const struct kvm_io_device *dev)
 714 {
 715         return container_of(dev, struct vgic_io_device, dev);
 716 }
 717
 718 static bool check_region(const struct kvm *kvm,
 719                          const struct vgic_register_region *region,
 720                          gpa_t addr, int len)
 721 {
 722         int flags, nr_irqs = kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
 723
 724         switch (len) {
 725         case sizeof(u8):
 726                 flags = VGIC_ACCESS_8bit;
 727                 break;
 728         case sizeof(u32):
 729                 flags = VGIC_ACCESS_32bit;
 730                 break;
 731         case sizeof(u64):
 732                 flags = VGIC_ACCESS_64bit;
 733                 break;
 734         default:
 735                 return false;
 736         }
 737
 738         if ((region->access_flags & flags) && IS_ALIGNED(addr, len)) {
 739                 if (!region->bits_per_irq)
 740                         return true;
 741
 742                 /* Do we access a non-allocated IRQ? */
 743                 return VGIC_ADDR_TO_INTID(addr, region->bits_per_irq) < nr_irqs;
 744         }
 745
 746         return false;
 747 }
 748
 749 const struct vgic_register_region *
 750 vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
 751                      gpa_t addr, int len)
 752 {
 753         const struct vgic_register_region *region;
 754
 755         region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
 756                                        addr - iodev->base_addr);
 757         if (!region || !check_region(vcpu->kvm, region, addr, len))
 758                 return NULL;
 759
 760         return region;
 761 }
 762
 763 static int vgic_uaccess_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 764                              gpa_t addr, u32 *val)
 765 {
 766         struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
 767         const struct vgic_register_region *region;
 768         struct kvm_vcpu *r_vcpu;
 769
 770         region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
 771         if (!region) {
 772                 *val = 0;
 773                 return 0;
 774         }
 775
 776         r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
 777         if (region->uaccess_read)
 778                 *val = region->uaccess_read(r_vcpu, addr, sizeof(u32));
 779         else
 780                 *val = region->read(r_vcpu, addr, sizeof(u32));
 781
 782         return 0;
 783 }
 784
 785 static int vgic_uaccess_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 786                               gpa_t addr, const u32 *val)
 787 {
 788         struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
 789         const struct vgic_register_region *region;
 790         struct kvm_vcpu *r_vcpu;
 791
 792         region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
 793         if (!region)
 794                 return 0;
 795
 796         r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
 797         if (region->uaccess_write)
 798                 return region->uaccess_write(r_vcpu, addr, sizeof(u32), *val);
 799
 800         region->write(r_vcpu, addr, sizeof(u32), *val);
 801         return 0;
 802 }
 803
 804 /*
 805  * Userland access to VGIC registers.
 806  */
 807 int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
 808                  bool is_write, int offset, u32 *val)
 809 {
 810         if (is_write)
 811                 return vgic_uaccess_write(vcpu, &dev->dev, offset, val);
 812         else
 813                 return vgic_uaccess_read(vcpu, &dev->dev, offset, val);
 814 }
 815
 816 static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 817                               gpa_t addr, int len, void *val)
 818 {
 819         struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
 820         const struct vgic_register_region *region;
 821         unsigned long data = 0;
 822
 823         region = vgic_get_mmio_region(vcpu, iodev, addr, len);
 824         if (!region) {
 825                 memset(val, 0, len);
 826                 return 0;
 827         }
 828
 829         switch (iodev->iodev_type) {
 830         case IODEV_CPUIF:
 831                 data = region->read(vcpu, addr, len);
 832                 break;
 833         case IODEV_DIST:
 834                 data = region->read(vcpu, addr, len);
 835                 break;
 836         case IODEV_REDIST:
 837                 data = region->read(iodev->redist_vcpu, addr, len);
 838                 break;
 839         case IODEV_ITS:
 840                 data = region->its_read(vcpu->kvm, iodev->its, addr, len);
 841                 break;
 842         }
 843
 844         vgic_data_host_to_mmio_bus(val, len, data);
 845         return 0;
 846 }
 847
 848 static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 849                                gpa_t addr, int len, const void *val)
 850 {
 851         struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
 852         const struct vgic_register_region *region;
 853         unsigned long data = vgic_data_mmio_bus_to_host(val, len);
 854
 855         region = vgic_get_mmio_region(vcpu, iodev, addr, len);
 856         if (!region)
 857                 return 0;
 858
 859         switch (iodev->iodev_type) {
 860         case IODEV_CPUIF:
 861                 region->write(vcpu, addr, len, data);
 862                 break;
 863         case IODEV_DIST:
 864                 region->write(vcpu, addr, len, data);
 865                 break;
 866         case IODEV_REDIST:
 867                 region->write(iodev->redist_vcpu, addr, len, data);
 868                 break;
 869         case IODEV_ITS:
 870                 region->its_write(vcpu->kvm, iodev->its, addr, len, data);
 871                 break;
 872         }
 873
 874         return 0;
 875 }
 876
 877 struct kvm_io_device_ops kvm_io_gic_ops = {
 878         .read = dispatch_mmio_read,
 879         .write = dispatch_mmio_write,
 880 };
 881
 882 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
 883                              enum vgic_type type)
 884 {
 885         struct vgic_io_device *io_device = &kvm->arch.vgic.dist_iodev;
 886         int ret = 0;
 887         unsigned int len;
 888
 889         switch (type) {
 890         case VGIC_V2:
 891                 len = vgic_v2_init_dist_iodev(io_device);
 892                 break;
 893         case VGIC_V3:
 894                 len = vgic_v3_init_dist_iodev(io_device);
 895                 break;
 896         default:
 897                 BUG_ON(1);
 898         }
 899
 900         io_device->base_addr = dist_base_address;
 901         io_device->iodev_type = IODEV_DIST;
 902         io_device->redist_vcpu = NULL;
 903
 904         mutex_lock(&kvm->slots_lock);
 905         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist_base_address,
 906                                       len, &io_device->dev);
 907         mutex_unlock(&kvm->slots_lock);
 908
 909         return ret;
 910 }