2 * VGIC MMIO handling functions
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/bitops.h>
15 #include <linux/bsearch.h>
16 #include <linux/kvm.h>
17 #include <linux/kvm_host.h>
18 #include <kvm/iodev.h>
19 #include <kvm/arm_arch_timer.h>
20 #include <kvm/arm_vgic.h>
23 #include "vgic-mmio.h"
25 unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
26 gpa_t addr, unsigned int len)
31 unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
32 gpa_t addr, unsigned int len)
37 void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
38 unsigned int len, unsigned long val)
43 int vgic_mmio_uaccess_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
44 unsigned int len, unsigned long val)
50 unsigned long vgic_mmio_read_group(struct kvm_vcpu *vcpu,
51 gpa_t addr, unsigned int len)
53 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
57 /* Loop over all IRQs affected by this read */
58 for (i = 0; i < len * 8; i++) {
59 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
64 vgic_put_irq(vcpu->kvm, irq);
70 void vgic_mmio_write_group(struct kvm_vcpu *vcpu, gpa_t addr,
71 unsigned int len, unsigned long val)
73 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
77 for (i = 0; i < len * 8; i++) {
78 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
80 spin_lock_irqsave(&irq->irq_lock, flags);
81 irq->group = !!(val & BIT(i));
82 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
84 vgic_put_irq(vcpu->kvm, irq);
89 * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value
90 * of the enabled bit, so there is only one function for both here.
92 unsigned long vgic_mmio_read_enable(struct kvm_vcpu *vcpu,
93 gpa_t addr, unsigned int len)
95 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
99 /* Loop over all IRQs affected by this read */
100 for (i = 0; i < len * 8; i++) {
101 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
106 vgic_put_irq(vcpu->kvm, irq);
112 void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
113 gpa_t addr, unsigned int len,
116 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
120 for_each_set_bit(i, &val, len * 8) {
121 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
123 spin_lock_irqsave(&irq->irq_lock, flags);
125 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
127 vgic_put_irq(vcpu->kvm, irq);
131 void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
132 gpa_t addr, unsigned int len,
135 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
139 for_each_set_bit(i, &val, len * 8) {
140 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
142 spin_lock_irqsave(&irq->irq_lock, flags);
144 irq->enabled = false;
146 spin_unlock_irqrestore(&irq->irq_lock, flags);
147 vgic_put_irq(vcpu->kvm, irq);
151 unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
152 gpa_t addr, unsigned int len)
154 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
158 /* Loop over all IRQs affected by this read */
159 for (i = 0; i < len * 8; i++) {
160 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
163 spin_lock_irqsave(&irq->irq_lock, flags);
164 if (irq_is_pending(irq))
166 spin_unlock_irqrestore(&irq->irq_lock, flags);
168 vgic_put_irq(vcpu->kvm, irq);
175 * This function will return the VCPU that performed the MMIO access and
176 * trapped from within the VM, and will return NULL if this is a userspace
179 * We can disable preemption locally around accessing the per-CPU variable,
180 * and use the resolved vcpu pointer after enabling preemption again, because
181 * even if the current thread is migrated to another CPU, reading the per-CPU
182 * value later will give us the same value as we update the per-CPU variable
183 * in the preempt notifier handlers.
185 static struct kvm_vcpu *vgic_get_mmio_requester_vcpu(void)
187 struct kvm_vcpu *vcpu;
190 vcpu = kvm_arm_get_running_vcpu();
195 /* Must be called with irq->irq_lock held */
196 static void vgic_hw_irq_spending(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
202 irq->pending_latch = true;
203 vgic_irq_set_phys_active(irq, true);
206 void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
207 gpa_t addr, unsigned int len,
210 bool is_uaccess = !vgic_get_mmio_requester_vcpu();
211 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
215 for_each_set_bit(i, &val, len * 8) {
216 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
218 spin_lock_irqsave(&irq->irq_lock, flags);
220 vgic_hw_irq_spending(vcpu, irq, is_uaccess);
222 irq->pending_latch = true;
223 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
224 vgic_put_irq(vcpu->kvm, irq);
228 /* Must be called with irq->irq_lock held */
229 static void vgic_hw_irq_cpending(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
235 irq->pending_latch = false;
238 * We don't want the guest to effectively mask the physical
239 * interrupt by doing a write to SPENDR followed by a write to
240 * CPENDR for HW interrupts, so we clear the active state on
241 * the physical side if the virtual interrupt is not active.
242 * This may lead to taking an additional interrupt on the
243 * host, but that should not be a problem as the worst that
244 * can happen is an additional vgic injection. We also clear
245 * the pending state to maintain proper semantics for edge HW
248 vgic_irq_set_phys_pending(irq, false);
250 vgic_irq_set_phys_active(irq, false);
253 void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
254 gpa_t addr, unsigned int len,
257 bool is_uaccess = !vgic_get_mmio_requester_vcpu();
258 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
262 for_each_set_bit(i, &val, len * 8) {
263 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
265 spin_lock_irqsave(&irq->irq_lock, flags);
268 vgic_hw_irq_cpending(vcpu, irq, is_uaccess);
270 irq->pending_latch = false;
272 spin_unlock_irqrestore(&irq->irq_lock, flags);
273 vgic_put_irq(vcpu->kvm, irq);
277 unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
278 gpa_t addr, unsigned int len)
280 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
284 /* Loop over all IRQs affected by this read */
285 for (i = 0; i < len * 8; i++) {
286 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
291 vgic_put_irq(vcpu->kvm, irq);
297 /* Must be called with irq->irq_lock held */
298 static void vgic_hw_irq_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
299 bool active, bool is_uaccess)
304 irq->active = active;
305 vgic_irq_set_phys_active(irq, active);
308 static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
312 struct kvm_vcpu *requester_vcpu = vgic_get_mmio_requester_vcpu();
314 spin_lock_irqsave(&irq->irq_lock, flags);
317 vgic_hw_irq_change_active(vcpu, irq, active, !requester_vcpu);
319 u32 model = vcpu->kvm->arch.vgic.vgic_model;
322 irq->active = active;
325 * The GICv2 architecture indicates that the source CPUID for
326 * an SGI should be provided during an EOI which implies that
327 * the active state is stored somewhere, but at the same time
328 * this state is not architecturally exposed anywhere and we
329 * have no way of knowing the right source.
331 * This may lead to a VCPU not being able to receive
332 * additional instances of a particular SGI after migration
333 * for a GICv2 VM on some GIC implementations. Oh well.
335 active_source = (requester_vcpu) ? requester_vcpu->vcpu_id : 0;
337 if (model == KVM_DEV_TYPE_ARM_VGIC_V2 &&
338 active && vgic_irq_is_sgi(irq->intid))
339 irq->active_source = active_source;
343 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
345 spin_unlock_irqrestore(&irq->irq_lock, flags);
349 * If we are fiddling with an IRQ's active state, we have to make sure the IRQ
350 * is not queued on some running VCPU's LRs, because then the change to the
351 * active state can be overwritten when the VCPU's state is synced coming back
354 * For shared interrupts, we have to stop all the VCPUs because interrupts can
355 * be migrated while we don't hold the IRQ locks and we don't want to be
356 * chasing moving targets.
358 * For private interrupts we don't have to do anything because userspace
359 * accesses to the VGIC state already require all VCPUs to be stopped, and
360 * only the VCPU itself can modify its private interrupts active state, which
361 * guarantees that the VCPU is not running.
363 static void vgic_change_active_prepare(struct kvm_vcpu *vcpu, u32 intid)
365 if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3 ||
366 intid > VGIC_NR_PRIVATE_IRQS)
367 kvm_arm_halt_guest(vcpu->kvm);
370 /* See vgic_change_active_prepare */
371 static void vgic_change_active_finish(struct kvm_vcpu *vcpu, u32 intid)
373 if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3 ||
374 intid > VGIC_NR_PRIVATE_IRQS)
375 kvm_arm_resume_guest(vcpu->kvm);
378 static void __vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
379 gpa_t addr, unsigned int len,
382 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
385 for_each_set_bit(i, &val, len * 8) {
386 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
387 vgic_mmio_change_active(vcpu, irq, false);
388 vgic_put_irq(vcpu->kvm, irq);
392 void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
393 gpa_t addr, unsigned int len,
396 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
398 mutex_lock(&vcpu->kvm->lock);
399 vgic_change_active_prepare(vcpu, intid);
401 __vgic_mmio_write_cactive(vcpu, addr, len, val);
403 vgic_change_active_finish(vcpu, intid);
404 mutex_unlock(&vcpu->kvm->lock);
407 int vgic_mmio_uaccess_write_cactive(struct kvm_vcpu *vcpu,
408 gpa_t addr, unsigned int len,
411 __vgic_mmio_write_cactive(vcpu, addr, len, val);
415 static void __vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
416 gpa_t addr, unsigned int len,
419 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
422 for_each_set_bit(i, &val, len * 8) {
423 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
424 vgic_mmio_change_active(vcpu, irq, true);
425 vgic_put_irq(vcpu->kvm, irq);
429 void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
430 gpa_t addr, unsigned int len,
433 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
435 mutex_lock(&vcpu->kvm->lock);
436 vgic_change_active_prepare(vcpu, intid);
438 __vgic_mmio_write_sactive(vcpu, addr, len, val);
440 vgic_change_active_finish(vcpu, intid);
441 mutex_unlock(&vcpu->kvm->lock);
444 int vgic_mmio_uaccess_write_sactive(struct kvm_vcpu *vcpu,
445 gpa_t addr, unsigned int len,
448 __vgic_mmio_write_sactive(vcpu, addr, len, val);
452 unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
453 gpa_t addr, unsigned int len)
455 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
459 for (i = 0; i < len; i++) {
460 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
462 val |= (u64)irq->priority << (i * 8);
464 vgic_put_irq(vcpu->kvm, irq);
471 * We currently don't handle changing the priority of an interrupt that
472 * is already pending on a VCPU. If there is a need for this, we would
473 * need to make this VCPU exit and re-evaluate the priorities, potentially
474 * leading to this interrupt getting presented now to the guest (if it has
475 * been masked by the priority mask before).
477 void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
478 gpa_t addr, unsigned int len,
481 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
485 for (i = 0; i < len; i++) {
486 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
488 spin_lock_irqsave(&irq->irq_lock, flags);
489 /* Narrow the priority range to what we actually support */
490 irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);
491 spin_unlock_irqrestore(&irq->irq_lock, flags);
493 vgic_put_irq(vcpu->kvm, irq);
497 unsigned long vgic_mmio_read_config(struct kvm_vcpu *vcpu,
498 gpa_t addr, unsigned int len)
500 u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
504 for (i = 0; i < len * 4; i++) {
505 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
507 if (irq->config == VGIC_CONFIG_EDGE)
508 value |= (2U << (i * 2));
510 vgic_put_irq(vcpu->kvm, irq);
516 void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
517 gpa_t addr, unsigned int len,
520 u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
524 for (i = 0; i < len * 4; i++) {
525 struct vgic_irq *irq;
528 * The configuration cannot be changed for SGIs in general,
529 * for PPIs this is IMPLEMENTATION DEFINED. The arch timer
530 * code relies on PPIs being level triggered, so we also
531 * make them read-only here.
533 if (intid + i < VGIC_NR_PRIVATE_IRQS)
536 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
537 spin_lock_irqsave(&irq->irq_lock, flags);
539 if (test_bit(i * 2 + 1, &val))
540 irq->config = VGIC_CONFIG_EDGE;
542 irq->config = VGIC_CONFIG_LEVEL;
544 spin_unlock_irqrestore(&irq->irq_lock, flags);
545 vgic_put_irq(vcpu->kvm, irq);
549 u64 vgic_read_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid)
553 int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
555 for (i = 0; i < 32; i++) {
556 struct vgic_irq *irq;
558 if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
561 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
562 if (irq->config == VGIC_CONFIG_LEVEL && irq->line_level)
565 vgic_put_irq(vcpu->kvm, irq);
571 void vgic_write_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid,
575 int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
578 for (i = 0; i < 32; i++) {
579 struct vgic_irq *irq;
582 if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
585 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
588 * Line level is set irrespective of irq type
589 * (level or edge) to avoid dependency that VM should
590 * restore irq config before line level.
592 new_level = !!(val & (1U << i));
593 spin_lock_irqsave(&irq->irq_lock, flags);
594 irq->line_level = new_level;
596 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
598 spin_unlock_irqrestore(&irq->irq_lock, flags);
600 vgic_put_irq(vcpu->kvm, irq);
604 static int match_region(const void *key, const void *elt)
606 const unsigned int offset = (unsigned long)key;
607 const struct vgic_register_region *region = elt;
609 if (offset < region->reg_offset)
612 if (offset >= region->reg_offset + region->len)
618 const struct vgic_register_region *
619 vgic_find_mmio_region(const struct vgic_register_region *regions,
620 int nr_regions, unsigned int offset)
622 return bsearch((void *)(uintptr_t)offset, regions, nr_regions,
623 sizeof(regions[0]), match_region);
626 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
628 if (kvm_vgic_global_state.type == VGIC_V2)
629 vgic_v2_set_vmcr(vcpu, vmcr);
631 vgic_v3_set_vmcr(vcpu, vmcr);
634 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
636 if (kvm_vgic_global_state.type == VGIC_V2)
637 vgic_v2_get_vmcr(vcpu, vmcr);
639 vgic_v3_get_vmcr(vcpu, vmcr);
643 * kvm_mmio_read_buf() returns a value in a format where it can be converted
644 * to a byte array and be directly observed as the guest wanted it to appear
645 * in memory if it had done the store itself, which is LE for the GIC, as the
646 * guest knows the GIC is always LE.
648 * We convert this value to the CPUs native format to deal with it as a data
651 unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len)
653 unsigned long data = kvm_mmio_read_buf(val, len);
659 return le16_to_cpu(data);
661 return le32_to_cpu(data);
663 return le64_to_cpu(data);
668 * kvm_mmio_write_buf() expects a value in a format such that if converted to
669 * a byte array it is observed as the guest would see it if it could perform
670 * the load directly. Since the GIC is LE, and the guest knows this, the
671 * guest expects a value in little endian format.
673 * We convert the data value from the CPUs native format to LE so that the
674 * value is returned in the proper format.
676 void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
683 data = cpu_to_le16(data);
686 data = cpu_to_le32(data);
689 data = cpu_to_le64(data);
692 kvm_mmio_write_buf(buf, len, data);
696 struct vgic_io_device *kvm_to_vgic_iodev(const struct kvm_io_device *dev)
698 return container_of(dev, struct vgic_io_device, dev);
701 static bool check_region(const struct kvm *kvm,
702 const struct vgic_register_region *region,
705 int flags, nr_irqs = kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
709 flags = VGIC_ACCESS_8bit;
712 flags = VGIC_ACCESS_32bit;
715 flags = VGIC_ACCESS_64bit;
721 if ((region->access_flags & flags) && IS_ALIGNED(addr, len)) {
722 if (!region->bits_per_irq)
725 /* Do we access a non-allocated IRQ? */
726 return VGIC_ADDR_TO_INTID(addr, region->bits_per_irq) < nr_irqs;
732 const struct vgic_register_region *
733 vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
736 const struct vgic_register_region *region;
738 region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
739 addr - iodev->base_addr);
740 if (!region || !check_region(vcpu->kvm, region, addr, len))
746 static int vgic_uaccess_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
747 gpa_t addr, u32 *val)
749 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
750 const struct vgic_register_region *region;
751 struct kvm_vcpu *r_vcpu;
753 region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
759 r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
760 if (region->uaccess_read)
761 *val = region->uaccess_read(r_vcpu, addr, sizeof(u32));
763 *val = region->read(r_vcpu, addr, sizeof(u32));
768 static int vgic_uaccess_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
769 gpa_t addr, const u32 *val)
771 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
772 const struct vgic_register_region *region;
773 struct kvm_vcpu *r_vcpu;
775 region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
779 r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
780 if (region->uaccess_write)
781 return region->uaccess_write(r_vcpu, addr, sizeof(u32), *val);
783 region->write(r_vcpu, addr, sizeof(u32), *val);
788 * Userland access to VGIC registers.
790 int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
791 bool is_write, int offset, u32 *val)
794 return vgic_uaccess_write(vcpu, &dev->dev, offset, val);
796 return vgic_uaccess_read(vcpu, &dev->dev, offset, val);
799 static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
800 gpa_t addr, int len, void *val)
802 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
803 const struct vgic_register_region *region;
804 unsigned long data = 0;
806 region = vgic_get_mmio_region(vcpu, iodev, addr, len);
812 switch (iodev->iodev_type) {
814 data = region->read(vcpu, addr, len);
817 data = region->read(vcpu, addr, len);
820 data = region->read(iodev->redist_vcpu, addr, len);
823 data = region->its_read(vcpu->kvm, iodev->its, addr, len);
827 vgic_data_host_to_mmio_bus(val, len, data);
831 static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
832 gpa_t addr, int len, const void *val)
834 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
835 const struct vgic_register_region *region;
836 unsigned long data = vgic_data_mmio_bus_to_host(val, len);
838 region = vgic_get_mmio_region(vcpu, iodev, addr, len);
842 switch (iodev->iodev_type) {
844 region->write(vcpu, addr, len, data);
847 region->write(vcpu, addr, len, data);
850 region->write(iodev->redist_vcpu, addr, len, data);
853 region->its_write(vcpu->kvm, iodev->its, addr, len, data);
860 struct kvm_io_device_ops kvm_io_gic_ops = {
861 .read = dispatch_mmio_read,
862 .write = dispatch_mmio_write,
865 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
868 struct vgic_io_device *io_device = &kvm->arch.vgic.dist_iodev;
874 len = vgic_v2_init_dist_iodev(io_device);
877 len = vgic_v3_init_dist_iodev(io_device);
883 io_device->base_addr = dist_base_address;
884 io_device->iodev_type = IODEV_DIST;
885 io_device->redist_vcpu = NULL;
887 mutex_lock(&kvm->slots_lock);
888 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist_base_address,
889 len, &io_device->dev);
890 mutex_unlock(&kvm->slots_lock);