virt/kvm/arm/vgic/vgic-mmio-v3.c

   1 /*
   2  * VGICv3 MMIO handling functions
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/irqchip/arm-gic-v3.h>
  15 #include <linux/kvm.h>
  16 #include <linux/kvm_host.h>
  17 #include <kvm/iodev.h>
  18 #include <kvm/arm_vgic.h>
  19
  20 #include <asm/kvm_emulate.h>
  21 #include <asm/kvm_arm.h>
  22 #include <asm/kvm_mmu.h>
  23
  24 #include "vgic.h"
  25 #include "vgic-mmio.h"
  26
  27 /* extract @num bytes at @offset bytes offset in data */
  28 unsigned long extract_bytes(u64 data, unsigned int offset,
  29                             unsigned int num)
  30 {
  31         return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
  32 }
  33
  34 /* allows updates of any half of a 64-bit register (or the whole thing) */
  35 u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
  36                      unsigned long val)
  37 {
  38         int lower = (offset & 4) * 8;
  39         int upper = lower + 8 * len - 1;
  40
  41         reg &= ~GENMASK_ULL(upper, lower);
  42         val &= GENMASK_ULL(len * 8 - 1, 0);
  43
  44         return reg | ((u64)val << lower);
  45 }
  46
  47 bool vgic_has_its(struct kvm *kvm)
  48 {
  49         struct vgic_dist *dist = &kvm->arch.vgic;
  50
  51         if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3)
  52                 return false;
  53
  54         return dist->has_its;
  55 }
  56
  57 bool vgic_supports_direct_msis(struct kvm *kvm)
  58 {
  59         return kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm);
  60 }
  61
  62 /*
  63  * The Revision field in the IIDR have the following meanings:
  64  *
  65  * Revision 2: Interrupt groups are guest-configurable and signaled using
  66  *             their configured groups.
  67  */
  68
  69 static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
  70                                             gpa_t addr, unsigned int len)
  71 {
  72         struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
  73         u32 value = 0;
  74
  75         switch (addr & 0x0c) {
  76         case GICD_CTLR:
  77                 if (vgic->enabled)
  78                         value |= GICD_CTLR_ENABLE_SS_G1;
  79                 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
  80                 break;
  81         case GICD_TYPER:
  82                 value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
  83                 value = (value >> 5) - 1;
  84                 if (vgic_has_its(vcpu->kvm)) {
  85                         value |= (INTERRUPT_ID_BITS_ITS - 1) << 19;
  86                         value |= GICD_TYPER_LPIS;
  87                 } else {
  88                         value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
  89                 }
  90                 break;
  91         case GICD_IIDR:
  92                 value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) |
  93                         (vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) |
  94                         (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT);
  95                 break;
  96         default:
  97                 return 0;
  98         }
  99
 100         return value;
 101 }
 102
 103 static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
 104                                     gpa_t addr, unsigned int len,
 105                                     unsigned long val)
 106 {
 107         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 108         bool was_enabled = dist->enabled;
 109
 110         switch (addr & 0x0c) {
 111         case GICD_CTLR:
 112                 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
 113
 114                 if (!was_enabled && dist->enabled)
 115                         vgic_kick_vcpus(vcpu->kvm);
 116                 break;
 117         case GICD_TYPER:
 118         case GICD_IIDR:
 119                 return;
 120         }
 121 }
 122
 123 static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu,
 124                                            gpa_t addr, unsigned int len,
 125                                            unsigned long val)
 126 {
 127         switch (addr & 0x0c) {
 128         case GICD_IIDR:
 129                 if (val != vgic_mmio_read_v3_misc(vcpu, addr, len))
 130                         return -EINVAL;
 131         }
 132
 133         vgic_mmio_write_v3_misc(vcpu, addr, len, val);
 134         return 0;
 135 }
 136
 137 static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu,
 138                                             gpa_t addr, unsigned int len)
 139 {
 140         int intid = VGIC_ADDR_TO_INTID(addr, 64);
 141         struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
 142         unsigned long ret = 0;
 143
 144         if (!irq)
 145                 return 0;
 146
 147         /* The upper word is RAZ for us. */
 148         if (!(addr & 4))
 149                 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len);
 150
 151         vgic_put_irq(vcpu->kvm, irq);
 152         return ret;
 153 }
 154
 155 static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu,
 156                                     gpa_t addr, unsigned int len,
 157                                     unsigned long val)
 158 {
 159         int intid = VGIC_ADDR_TO_INTID(addr, 64);
 160         struct vgic_irq *irq;
 161         unsigned long flags;
 162
 163         /* The upper word is WI for us since we don't implement Aff3. */
 164         if (addr & 4)
 165                 return;
 166
 167         irq = vgic_get_irq(vcpu->kvm, NULL, intid);
 168
 169         if (!irq)
 170                 return;
 171
 172         raw_spin_lock_irqsave(&irq->irq_lock, flags);
 173
 174         /* We only care about and preserve Aff0, Aff1 and Aff2. */
 175         irq->mpidr = val & GENMASK(23, 0);
 176         irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
 177
 178         raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 179         vgic_put_irq(vcpu->kvm, irq);
 180 }
 181
 182 static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu,
 183                                              gpa_t addr, unsigned int len)
 184 {
 185         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 186
 187         return vgic_cpu->lpis_enabled ? GICR_CTLR_ENABLE_LPIS : 0;
 188 }
 189
 190
 191 static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,
 192                                      gpa_t addr, unsigned int len,
 193                                      unsigned long val)
 194 {
 195         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 196         bool was_enabled = vgic_cpu->lpis_enabled;
 197
 198         if (!vgic_has_its(vcpu->kvm))
 199                 return;
 200
 201         vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS;
 202
 203         if (was_enabled && !vgic_cpu->lpis_enabled)
 204                 vgic_flush_pending_lpis(vcpu);
 205
 206         if (!was_enabled && vgic_cpu->lpis_enabled)
 207                 vgic_enable_lpis(vcpu);
 208 }
 209
 210 static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
 211                                               gpa_t addr, unsigned int len)
 212 {
 213         unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
 214         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 215         struct vgic_redist_region *rdreg = vgic_cpu->rdreg;
 216         int target_vcpu_id = vcpu->vcpu_id;
 217         gpa_t last_rdist_typer = rdreg->base + GICR_TYPER +
 218                         (rdreg->free_index - 1) * KVM_VGIC_V3_REDIST_SIZE;
 219         u64 value;
 220
 221         value = (u64)(mpidr & GENMASK(23, 0)) << 32;
 222         value |= ((target_vcpu_id & 0xffff) << 8);
 223
 224         if (addr == last_rdist_typer)
 225                 value |= GICR_TYPER_LAST;
 226         if (vgic_has_its(vcpu->kvm))
 227                 value |= GICR_TYPER_PLPIS;
 228
 229         return extract_bytes(value, addr & 7, len);
 230 }
 231
 232 static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
 233                                              gpa_t addr, unsigned int len)
 234 {
 235         return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
 236 }
 237
 238 static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
 239                                               gpa_t addr, unsigned int len)
 240 {
 241         switch (addr & 0xffff) {
 242         case GICD_PIDR2:
 243                 /* report a GICv3 compliant implementation */
 244                 return 0x3b;
 245         }
 246
 247         return 0;
 248 }
 249
 250 static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu,
 251                                                   gpa_t addr, unsigned int len)
 252 {
 253         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 254         u32 value = 0;
 255         int i;
 256
 257         /*
 258          * pending state of interrupt is latched in pending_latch variable.
 259          * Userspace will save and restore pending state and line_level
 260          * separately.
 261          * Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
 262          * for handling of ISPENDR and ICPENDR.
 263          */
 264         for (i = 0; i < len * 8; i++) {
 265                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 266
 267                 if (irq->pending_latch)
 268                         value |= (1U << i);
 269
 270                 vgic_put_irq(vcpu->kvm, irq);
 271         }
 272
 273         return value;
 274 }
 275
 276 static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu,
 277                                          gpa_t addr, unsigned int len,
 278                                          unsigned long val)
 279 {
 280         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 281         int i;
 282         unsigned long flags;
 283
 284         for (i = 0; i < len * 8; i++) {
 285                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 286
 287                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 288                 if (test_bit(i, &val)) {
 289                         /*
 290                          * pending_latch is set irrespective of irq type
 291                          * (level or edge) to avoid dependency that VM should
 292                          * restore irq config before pending info.
 293                          */
 294                         irq->pending_latch = true;
 295                         vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 296                 } else {
 297                         irq->pending_latch = false;
 298                         raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 299                 }
 300
 301                 vgic_put_irq(vcpu->kvm, irq);
 302         }
 303
 304         return 0;
 305 }
 306
 307 /* We want to avoid outer shareable. */
 308 u64 vgic_sanitise_shareability(u64 field)
 309 {
 310         switch (field) {
 311         case GIC_BASER_OuterShareable:
 312                 return GIC_BASER_InnerShareable;
 313         default:
 314                 return field;
 315         }
 316 }
 317
 318 /* Avoid any inner non-cacheable mapping. */
 319 u64 vgic_sanitise_inner_cacheability(u64 field)
 320 {
 321         switch (field) {
 322         case GIC_BASER_CACHE_nCnB:
 323         case GIC_BASER_CACHE_nC:
 324                 return GIC_BASER_CACHE_RaWb;
 325         default:
 326                 return field;
 327         }
 328 }
 329
 330 /* Non-cacheable or same-as-inner are OK. */
 331 u64 vgic_sanitise_outer_cacheability(u64 field)
 332 {
 333         switch (field) {
 334         case GIC_BASER_CACHE_SameAsInner:
 335         case GIC_BASER_CACHE_nC:
 336                 return field;
 337         default:
 338                 return GIC_BASER_CACHE_nC;
 339         }
 340 }
 341
 342 u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
 343                         u64 (*sanitise_fn)(u64))
 344 {
 345         u64 field = (reg & field_mask) >> field_shift;
 346
 347         field = sanitise_fn(field) << field_shift;
 348         return (reg & ~field_mask) | field;
 349 }
 350
 351 #define PROPBASER_RES0_MASK                                             \
 352         (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5))
 353 #define PENDBASER_RES0_MASK                                             \
 354         (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) |      \
 355          GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0))
 356
 357 static u64 vgic_sanitise_pendbaser(u64 reg)
 358 {
 359         reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK,
 360                                   GICR_PENDBASER_SHAREABILITY_SHIFT,
 361                                   vgic_sanitise_shareability);
 362         reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK,
 363                                   GICR_PENDBASER_INNER_CACHEABILITY_SHIFT,
 364                                   vgic_sanitise_inner_cacheability);
 365         reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK,
 366                                   GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT,
 367                                   vgic_sanitise_outer_cacheability);
 368
 369         reg &= ~PENDBASER_RES0_MASK;
 370
 371         return reg;
 372 }
 373
 374 static u64 vgic_sanitise_propbaser(u64 reg)
 375 {
 376         reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK,
 377                                   GICR_PROPBASER_SHAREABILITY_SHIFT,
 378                                   vgic_sanitise_shareability);
 379         reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK,
 380                                   GICR_PROPBASER_INNER_CACHEABILITY_SHIFT,
 381                                   vgic_sanitise_inner_cacheability);
 382         reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK,
 383                                   GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT,
 384                                   vgic_sanitise_outer_cacheability);
 385
 386         reg &= ~PROPBASER_RES0_MASK;
 387         return reg;
 388 }
 389
 390 static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu,
 391                                              gpa_t addr, unsigned int len)
 392 {
 393         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 394
 395         return extract_bytes(dist->propbaser, addr & 7, len);
 396 }
 397
 398 static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu,
 399                                      gpa_t addr, unsigned int len,
 400                                      unsigned long val)
 401 {
 402         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 403         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 404         u64 old_propbaser, propbaser;
 405
 406         /* Storing a value with LPIs already enabled is undefined */
 407         if (vgic_cpu->lpis_enabled)
 408                 return;
 409
 410         do {
 411                 old_propbaser = READ_ONCE(dist->propbaser);
 412                 propbaser = old_propbaser;
 413                 propbaser = update_64bit_reg(propbaser, addr & 4, len, val);
 414                 propbaser = vgic_sanitise_propbaser(propbaser);
 415         } while (cmpxchg64(&dist->propbaser, old_propbaser,
 416                            propbaser) != old_propbaser);
 417 }
 418
 419 static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu,
 420                                              gpa_t addr, unsigned int len)
 421 {
 422         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 423
 424         return extract_bytes(vgic_cpu->pendbaser, addr & 7, len);
 425 }
 426
 427 static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
 428                                      gpa_t addr, unsigned int len,
 429                                      unsigned long val)
 430 {
 431         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 432         u64 old_pendbaser, pendbaser;
 433
 434         /* Storing a value with LPIs already enabled is undefined */
 435         if (vgic_cpu->lpis_enabled)
 436                 return;
 437
 438         do {
 439                 old_pendbaser = READ_ONCE(vgic_cpu->pendbaser);
 440                 pendbaser = old_pendbaser;
 441                 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);
 442                 pendbaser = vgic_sanitise_pendbaser(pendbaser);
 443         } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser,
 444                            pendbaser) != old_pendbaser);
 445 }
 446
 447 /*
 448  * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
 449  * redistributors, while SPIs are covered by registers in the distributor
 450  * block. Trying to set private IRQs in this block gets ignored.
 451  * We take some special care here to fix the calculation of the register
 452  * offset.
 453  */
 454 #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \
 455         {                                                               \
 456                 .reg_offset = off,                                      \
 457                 .bits_per_irq = bpi,                                    \
 458                 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8,                \
 459                 .access_flags = acc,                                    \
 460                 .read = vgic_mmio_read_raz,                             \
 461                 .write = vgic_mmio_write_wi,                            \
 462         }, {                                                            \
 463                 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8,   \
 464                 .bits_per_irq = bpi,                                    \
 465                 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8,       \
 466                 .access_flags = acc,                                    \
 467                 .read = rd,                                             \
 468                 .write = wr,                                            \
 469                 .uaccess_read = ur,                                     \
 470                 .uaccess_write = uw,                                    \
 471         }
 472
 473 static const struct vgic_register_region vgic_v3_dist_registers[] = {
 474         REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR,
 475                 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc,
 476                 NULL, vgic_mmio_uaccess_write_v3_misc,
 477                 16, VGIC_ACCESS_32bit),
 478         REGISTER_DESC_WITH_LENGTH(GICD_STATUSR,
 479                 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
 480                 VGIC_ACCESS_32bit),
 481         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
 482                 vgic_mmio_read_group, vgic_mmio_write_group, NULL, NULL, 1,
 483                 VGIC_ACCESS_32bit),
 484         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
 485                 vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,
 486                 VGIC_ACCESS_32bit),
 487         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
 488                 vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,
 489                 VGIC_ACCESS_32bit),
 490         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
 491                 vgic_mmio_read_pending, vgic_mmio_write_spending,
 492                 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
 493                 VGIC_ACCESS_32bit),
 494         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
 495                 vgic_mmio_read_pending, vgic_mmio_write_cpending,
 496                 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 1,
 497                 VGIC_ACCESS_32bit),
 498         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
 499                 vgic_mmio_read_active, vgic_mmio_write_sactive,
 500                 NULL, vgic_mmio_uaccess_write_sactive, 1,
 501                 VGIC_ACCESS_32bit),
 502         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
 503                 vgic_mmio_read_active, vgic_mmio_write_cactive,
 504                 NULL, vgic_mmio_uaccess_write_cactive,
 505                 1, VGIC_ACCESS_32bit),
 506         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
 507                 vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
 508                 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 509         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
 510                 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8,
 511                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 512         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
 513                 vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
 514                 VGIC_ACCESS_32bit),
 515         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
 516                 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
 517                 VGIC_ACCESS_32bit),
 518         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
 519                 vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64,
 520                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 521         REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
 522                 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
 523                 VGIC_ACCESS_32bit),
 524 };
 525
 526 static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
 527         REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
 528                 vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
 529                 VGIC_ACCESS_32bit),
 530         REGISTER_DESC_WITH_LENGTH(GICR_STATUSR,
 531                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 532                 VGIC_ACCESS_32bit),
 533         REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
 534                 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
 535                 VGIC_ACCESS_32bit),
 536         REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
 537                 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
 538                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 539         REGISTER_DESC_WITH_LENGTH(GICR_WAKER,
 540                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 541                 VGIC_ACCESS_32bit),
 542         REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
 543                 vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
 544                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 545         REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
 546                 vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
 547                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 548         REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
 549                 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
 550                 VGIC_ACCESS_32bit),
 551 };
 552
 553 static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
 554         REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
 555                 vgic_mmio_read_group, vgic_mmio_write_group, 4,
 556                 VGIC_ACCESS_32bit),
 557         REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
 558                 vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
 559                 VGIC_ACCESS_32bit),
 560         REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
 561                 vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
 562                 VGIC_ACCESS_32bit),
 563         REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISPENDR0,
 564                 vgic_mmio_read_pending, vgic_mmio_write_spending,
 565                 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
 566                 VGIC_ACCESS_32bit),
 567         REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICPENDR0,
 568                 vgic_mmio_read_pending, vgic_mmio_write_cpending,
 569                 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 4,
 570                 VGIC_ACCESS_32bit),
 571         REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISACTIVER0,
 572                 vgic_mmio_read_active, vgic_mmio_write_sactive,
 573                 NULL, vgic_mmio_uaccess_write_sactive,
 574                 4, VGIC_ACCESS_32bit),
 575         REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICACTIVER0,
 576                 vgic_mmio_read_active, vgic_mmio_write_cactive,
 577                 NULL, vgic_mmio_uaccess_write_cactive,
 578                 4, VGIC_ACCESS_32bit),
 579         REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
 580                 vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
 581                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 582         REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
 583                 vgic_mmio_read_config, vgic_mmio_write_config, 8,
 584                 VGIC_ACCESS_32bit),
 585         REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
 586                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 587                 VGIC_ACCESS_32bit),
 588         REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
 589                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 590                 VGIC_ACCESS_32bit),
 591 };
 592
 593 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
 594 {
 595         dev->regions = vgic_v3_dist_registers;
 596         dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
 597
 598         kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
 599
 600         return SZ_64K;
 601 }
 602
 603 /**
 604  * vgic_register_redist_iodev - register a single redist iodev
 605  * @vcpu:    The VCPU to which the redistributor belongs
 606  *
 607  * Register a KVM iodev for this VCPU's redistributor using the address
 608  * provided.
 609  *
 610  * Return 0 on success, -ERRNO otherwise.
 611  */
 612 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu)
 613 {
 614         struct kvm *kvm = vcpu->kvm;
 615         struct vgic_dist *vgic = &kvm->arch.vgic;
 616         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 617         struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
 618         struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev;
 619         struct vgic_redist_region *rdreg;
 620         gpa_t rd_base, sgi_base;
 621         int ret;
 622
 623         if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr))
 624                 return 0;
 625
 626         /*
 627          * We may be creating VCPUs before having set the base address for the
 628          * redistributor region, in which case we will come back to this
 629          * function for all VCPUs when the base address is set.  Just return
 630          * without doing any work for now.
 631          */
 632         rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions);
 633         if (!rdreg)
 634                 return 0;
 635
 636         if (!vgic_v3_check_base(kvm))
 637                 return -EINVAL;
 638
 639         vgic_cpu->rdreg = rdreg;
 640
 641         rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE;
 642         sgi_base = rd_base + SZ_64K;
 643
 644         kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
 645         rd_dev->base_addr = rd_base;
 646         rd_dev->iodev_type = IODEV_REDIST;
 647         rd_dev->regions = vgic_v3_rdbase_registers;
 648         rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
 649         rd_dev->redist_vcpu = vcpu;
 650
 651         mutex_lock(&kvm->slots_lock);
 652         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
 653                                       SZ_64K, &rd_dev->dev);
 654         mutex_unlock(&kvm->slots_lock);
 655
 656         if (ret)
 657                 return ret;
 658
 659         kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
 660         sgi_dev->base_addr = sgi_base;
 661         sgi_dev->iodev_type = IODEV_REDIST;
 662         sgi_dev->regions = vgic_v3_sgibase_registers;
 663         sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
 664         sgi_dev->redist_vcpu = vcpu;
 665
 666         mutex_lock(&kvm->slots_lock);
 667         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
 668                                       SZ_64K, &sgi_dev->dev);
 669         if (ret) {
 670                 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
 671                                           &rd_dev->dev);
 672                 goto out;
 673         }
 674
 675         rdreg->free_index++;
 676 out:
 677         mutex_unlock(&kvm->slots_lock);
 678         return ret;
 679 }
 680
 681 static void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu)
 682 {
 683         struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
 684         struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev;
 685
 686         kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev);
 687         kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &sgi_dev->dev);
 688 }
 689
 690 static int vgic_register_all_redist_iodevs(struct kvm *kvm)
 691 {
 692         struct kvm_vcpu *vcpu;
 693         int c, ret = 0;
 694
 695         kvm_for_each_vcpu(c, vcpu, kvm) {
 696                 ret = vgic_register_redist_iodev(vcpu);
 697                 if (ret)
 698                         break;
 699         }
 700
 701         if (ret) {
 702                 /* The current c failed, so we start with the previous one. */
 703                 mutex_lock(&kvm->slots_lock);
 704                 for (c--; c >= 0; c--) {
 705                         vcpu = kvm_get_vcpu(kvm, c);
 706                         vgic_unregister_redist_iodev(vcpu);
 707                 }
 708                 mutex_unlock(&kvm->slots_lock);
 709         }
 710
 711         return ret;
 712 }
 713
 714 /**
 715  * vgic_v3_insert_redist_region - Insert a new redistributor region
 716  *
 717  * Performs various checks before inserting the rdist region in the list.
 718  * Those tests depend on whether the size of the rdist region is known
 719  * (ie. count != 0). The list is sorted by rdist region index.
 720  *
 721  * @kvm: kvm handle
 722  * @index: redist region index
 723  * @base: base of the new rdist region
 724  * @count: number of redistributors the region is made of (0 in the old style
 725  * single region, whose size is induced from the number of vcpus)
 726  *
 727  * Return 0 on success, < 0 otherwise
 728  */
 729 static int vgic_v3_insert_redist_region(struct kvm *kvm, uint32_t index,
 730                                         gpa_t base, uint32_t count)
 731 {
 732         struct vgic_dist *d = &kvm->arch.vgic;
 733         struct vgic_redist_region *rdreg;
 734         struct list_head *rd_regions = &d->rd_regions;
 735         size_t size = count * KVM_VGIC_V3_REDIST_SIZE;
 736         int ret;
 737
 738         /* single rdist region already set ?*/
 739         if (!count && !list_empty(rd_regions))
 740                 return -EINVAL;
 741
 742         /* cross the end of memory ? */
 743         if (base + size < base)
 744                 return -EINVAL;
 745
 746         if (list_empty(rd_regions)) {
 747                 if (index != 0)
 748                         return -EINVAL;
 749         } else {
 750                 rdreg = list_last_entry(rd_regions,
 751                                         struct vgic_redist_region, list);
 752                 if (index != rdreg->index + 1)
 753                         return -EINVAL;
 754
 755                 /* Cannot add an explicitly sized regions after legacy region */
 756                 if (!rdreg->count)
 757                         return -EINVAL;
 758         }
 759
 760         /*
 761          * For legacy single-region redistributor regions (!count),
 762          * check that the redistributor region does not overlap with the
 763          * distributor's address space.
 764          */
 765         if (!count && !IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
 766                 vgic_dist_overlap(kvm, base, size))
 767                 return -EINVAL;
 768
 769         /* collision with any other rdist region? */
 770         if (vgic_v3_rdist_overlap(kvm, base, size))
 771                 return -EINVAL;
 772
 773         rdreg = kzalloc(sizeof(*rdreg), GFP_KERNEL);
 774         if (!rdreg)
 775                 return -ENOMEM;
 776
 777         rdreg->base = VGIC_ADDR_UNDEF;
 778
 779         ret = vgic_check_ioaddr(kvm, &rdreg->base, base, SZ_64K);
 780         if (ret)
 781                 goto free;
 782
 783         rdreg->base = base;
 784         rdreg->count = count;
 785         rdreg->free_index = 0;
 786         rdreg->index = index;
 787
 788         list_add_tail(&rdreg->list, rd_regions);
 789         return 0;
 790 free:
 791         kfree(rdreg);
 792         return ret;
 793 }
 794
 795 int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count)
 796 {
 797         int ret;
 798
 799         ret = vgic_v3_insert_redist_region(kvm, index, addr, count);
 800         if (ret)
 801                 return ret;
 802
 803         /*
 804          * Register iodevs for each existing VCPU.  Adding more VCPUs
 805          * afterwards will register the iodevs when needed.
 806          */
 807         ret = vgic_register_all_redist_iodevs(kvm);
 808         if (ret)
 809                 return ret;
 810
 811         return 0;
 812 }
 813
 814 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
 815 {
 816         const struct vgic_register_region *region;
 817         struct vgic_io_device iodev;
 818         struct vgic_reg_attr reg_attr;
 819         struct kvm_vcpu *vcpu;
 820         gpa_t addr;
 821         int ret;
 822
 823         ret = vgic_v3_parse_attr(dev, attr, &reg_attr);
 824         if (ret)
 825                 return ret;
 826
 827         vcpu = reg_attr.vcpu;
 828         addr = reg_attr.addr;
 829
 830         switch (attr->group) {
 831         case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
 832                 iodev.regions = vgic_v3_dist_registers;
 833                 iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
 834                 iodev.base_addr = 0;
 835                 break;
 836         case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{
 837                 iodev.regions = vgic_v3_rdbase_registers;
 838                 iodev.nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
 839                 iodev.base_addr = 0;
 840                 break;
 841         }
 842         case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
 843                 u64 reg, id;
 844
 845                 id = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK);
 846                 return vgic_v3_has_cpu_sysregs_attr(vcpu, 0, id, &reg);
 847         }
 848         default:
 849                 return -ENXIO;
 850         }
 851
 852         /* We only support aligned 32-bit accesses. */
 853         if (addr & 3)
 854                 return -ENXIO;
 855
 856         region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
 857         if (!region)
 858                 return -ENXIO;
 859
 860         return 0;
 861 }
 862 /*
 863  * Compare a given affinity (level 1-3 and a level 0 mask, from the SGI
 864  * generation register ICC_SGI1R_EL1) with a given VCPU.
 865  * If the VCPU's MPIDR matches, return the level0 affinity, otherwise
 866  * return -1.
 867  */
 868 static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu)
 869 {
 870         unsigned long affinity;
 871         int level0;
 872
 873         /*
 874          * Split the current VCPU's MPIDR into affinity level 0 and the
 875          * rest as this is what we have to compare against.
 876          */
 877         affinity = kvm_vcpu_get_mpidr_aff(vcpu);
 878         level0 = MPIDR_AFFINITY_LEVEL(affinity, 0);
 879         affinity &= ~MPIDR_LEVEL_MASK;
 880
 881         /* bail out if the upper three levels don't match */
 882         if (sgi_aff != affinity)
 883                 return -1;
 884
 885         /* Is this VCPU's bit set in the mask ? */
 886         if (!(sgi_cpu_mask & BIT(level0)))
 887                 return -1;
 888
 889         return level0;
 890 }
 891
 892 /*
 893  * The ICC_SGI* registers encode the affinity differently from the MPIDR,
 894  * so provide a wrapper to use the existing defines to isolate a certain
 895  * affinity level.
 896  */
 897 #define SGI_AFFINITY_LEVEL(reg, level) \
 898         ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
 899         >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
 900
 901 /**
 902  * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs
 903  * @vcpu: The VCPU requesting a SGI
 904  * @reg: The value written into ICC_{ASGI1,SGI0,SGI1}R by that VCPU
 905  * @allow_group1: Does the sysreg access allow generation of G1 SGIs
 906  *
 907  * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
 908  * This will trap in sys_regs.c and call this function.
 909  * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the
 910  * target processors as well as a bitmask of 16 Aff0 CPUs.
 911  * If the interrupt routing mode bit is not set, we iterate over all VCPUs to
 912  * check for matching ones. If this bit is set, we signal all, but not the
 913  * calling VCPU.
 914  */
 915 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1)
 916 {
 917         struct kvm *kvm = vcpu->kvm;
 918         struct kvm_vcpu *c_vcpu;
 919         u16 target_cpus;
 920         u64 mpidr;
 921         int sgi, c;
 922         int vcpu_id = vcpu->vcpu_id;
 923         bool broadcast;
 924         unsigned long flags;
 925
 926         sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;
 927         broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
 928         target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;
 929         mpidr = SGI_AFFINITY_LEVEL(reg, 3);
 930         mpidr |= SGI_AFFINITY_LEVEL(reg, 2);
 931         mpidr |= SGI_AFFINITY_LEVEL(reg, 1);
 932
 933         /*
 934          * We iterate over all VCPUs to find the MPIDRs matching the request.
 935          * If we have handled one CPU, we clear its bit to detect early
 936          * if we are already finished. This avoids iterating through all
 937          * VCPUs when most of the times we just signal a single VCPU.
 938          */
 939         kvm_for_each_vcpu(c, c_vcpu, kvm) {
 940                 struct vgic_irq *irq;
 941
 942                 /* Exit early if we have dealt with all requested CPUs */
 943                 if (!broadcast && target_cpus == 0)
 944                         break;
 945
 946                 /* Don't signal the calling VCPU */
 947                 if (broadcast && c == vcpu_id)
 948                         continue;
 949
 950                 if (!broadcast) {
 951                         int level0;
 952
 953                         level0 = match_mpidr(mpidr, target_cpus, c_vcpu);
 954                         if (level0 == -1)
 955                                 continue;
 956
 957                         /* remove this matching VCPU from the mask */
 958                         target_cpus &= ~BIT(level0);
 959                 }
 960
 961                 irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
 962
 963                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 964
 965                 /*
 966                  * An access targetting Group0 SGIs can only generate
 967                  * those, while an access targetting Group1 SGIs can
 968                  * generate interrupts of either group.
 969                  */
 970                 if (!irq->group || allow_group1) {
 971                         irq->pending_latch = true;
 972                         vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 973                 } else {
 974                         raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 975                 }
 976
 977                 vgic_put_irq(vcpu->kvm, irq);
 978         }
 979 }
 980
 981 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 982                          int offset, u32 *val)
 983 {
 984         struct vgic_io_device dev = {
 985                 .regions = vgic_v3_dist_registers,
 986                 .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers),
 987         };
 988
 989         return vgic_uaccess(vcpu, &dev, is_write, offset, val);
 990 }
 991
 992 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 993                            int offset, u32 *val)
 994 {
 995         struct vgic_io_device rd_dev = {
 996                 .regions = vgic_v3_rdbase_registers,
 997                 .nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers),
 998         };
 999
1000         struct vgic_io_device sgi_dev = {
1001                 .regions = vgic_v3_sgibase_registers,
1002                 .nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers),
1003         };
1004
1005         /* SGI_base is the next 64K frame after RD_base */
1006         if (offset >= SZ_64K)
1007                 return vgic_uaccess(vcpu, &sgi_dev, is_write, offset - SZ_64K,
1008                                     val);
1009         else
1010                 return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val);
1011 }
1012
1013 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
1014                                     u32 intid, u64 *val)
1015 {
1016         if (intid % 32)
1017                 return -EINVAL;
1018
1019         if (is_write)
1020                 vgic_write_irq_line_level_info(vcpu, intid, *val);
1021         else
1022                 *val = vgic_read_irq_line_level_info(vcpu, intid);
1023
1024         return 0;
1025 }