1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * tools/testing/selftests/kvm/include/x86_64/processor.h
5 * Copyright (C) 2018, Google LLC.
8 #ifndef SELFTEST_KVM_PROCESSOR_H
9 #define SELFTEST_KVM_PROCESSOR_H
14 #include <asm/msr-index.h>
16 #define X86_EFLAGS_FIXED (1u << 1)
18 #define X86_CR4_VME (1ul << 0)
19 #define X86_CR4_PVI (1ul << 1)
20 #define X86_CR4_TSD (1ul << 2)
21 #define X86_CR4_DE (1ul << 3)
22 #define X86_CR4_PSE (1ul << 4)
23 #define X86_CR4_PAE (1ul << 5)
24 #define X86_CR4_MCE (1ul << 6)
25 #define X86_CR4_PGE (1ul << 7)
26 #define X86_CR4_PCE (1ul << 8)
27 #define X86_CR4_OSFXSR (1ul << 9)
28 #define X86_CR4_OSXMMEXCPT (1ul << 10)
29 #define X86_CR4_UMIP (1ul << 11)
30 #define X86_CR4_VMXE (1ul << 13)
31 #define X86_CR4_SMXE (1ul << 14)
32 #define X86_CR4_FSGSBASE (1ul << 16)
33 #define X86_CR4_PCIDE (1ul << 17)
34 #define X86_CR4_OSXSAVE (1ul << 18)
35 #define X86_CR4_SMEP (1ul << 20)
36 #define X86_CR4_SMAP (1ul << 21)
37 #define X86_CR4_PKE (1ul << 22)
39 /* The enum values match the intruction encoding of each register */
62 unsigned base1:8, s:1, type:4, dpl:2, p:1;
63 unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8;
66 } __attribute__((packed));
71 } __attribute__((packed));
73 static inline uint64_t get_desc64_base(const struct desc64 *desc)
75 return ((uint64_t)desc->base3 << 32) |
76 (desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
79 static inline uint64_t rdtsc(void)
84 * The lfence is to wait (on Intel CPUs) until all previous
85 * instructions have been executed.
87 __asm__ __volatile__("lfence; rdtsc" : "=a"(eax), "=d"(edx));
88 return ((uint64_t)edx) << 32 | eax;
91 static inline uint64_t rdtscp(uint32_t *aux)
95 __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux));
96 return ((uint64_t)edx) << 32 | eax;
99 static inline uint64_t rdmsr(uint32_t msr)
103 __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory");
105 return a | ((uint64_t) d << 32);
108 static inline void wrmsr(uint32_t msr, uint64_t value)
111 uint32_t d = value >> 32;
113 __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory");
117 static inline uint16_t inw(uint16_t port)
121 __asm__ __volatile__("in %%dx, %%ax"
122 : /* output */ "=a" (tmp)
123 : /* input */ "d" (port));
128 static inline uint16_t get_es(void)
132 __asm__ __volatile__("mov %%es, %[es]"
133 : /* output */ [es]"=rm"(es));
137 static inline uint16_t get_cs(void)
141 __asm__ __volatile__("mov %%cs, %[cs]"
142 : /* output */ [cs]"=rm"(cs));
146 static inline uint16_t get_ss(void)
150 __asm__ __volatile__("mov %%ss, %[ss]"
151 : /* output */ [ss]"=rm"(ss));
155 static inline uint16_t get_ds(void)
159 __asm__ __volatile__("mov %%ds, %[ds]"
160 : /* output */ [ds]"=rm"(ds));
164 static inline uint16_t get_fs(void)
168 __asm__ __volatile__("mov %%fs, %[fs]"
169 : /* output */ [fs]"=rm"(fs));
173 static inline uint16_t get_gs(void)
177 __asm__ __volatile__("mov %%gs, %[gs]"
178 : /* output */ [gs]"=rm"(gs));
182 static inline uint16_t get_tr(void)
186 __asm__ __volatile__("str %[tr]"
187 : /* output */ [tr]"=rm"(tr));
191 static inline uint64_t get_cr0(void)
195 __asm__ __volatile__("mov %%cr0, %[cr0]"
196 : /* output */ [cr0]"=r"(cr0));
200 static inline uint64_t get_cr3(void)
204 __asm__ __volatile__("mov %%cr3, %[cr3]"
205 : /* output */ [cr3]"=r"(cr3));
209 static inline uint64_t get_cr4(void)
213 __asm__ __volatile__("mov %%cr4, %[cr4]"
214 : /* output */ [cr4]"=r"(cr4));
218 static inline void set_cr4(uint64_t val)
220 __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory");
223 static inline uint64_t get_gdt_base(void)
226 __asm__ __volatile__("sgdt %[gdt]"
227 : /* output */ [gdt]"=m"(gdt));
231 static inline uint64_t get_idt_base(void)
234 __asm__ __volatile__("sidt %[idt]"
235 : /* output */ [idt]"=m"(idt));
239 #define SET_XMM(__var, __xmm) \
240 asm volatile("movq %0, %%"#__xmm : : "r"(__var) : #__xmm)
242 static inline void set_xmm(int n, unsigned long val)
272 typedef unsigned long v1di __attribute__ ((vector_size (8)));
273 static inline unsigned long get_xmm(int n)
275 assert(n >= 0 && n <= 7);
277 register v1di xmm0 __asm__("%xmm0");
278 register v1di xmm1 __asm__("%xmm1");
279 register v1di xmm2 __asm__("%xmm2");
280 register v1di xmm3 __asm__("%xmm3");
281 register v1di xmm4 __asm__("%xmm4");
282 register v1di xmm5 __asm__("%xmm5");
283 register v1di xmm6 __asm__("%xmm6");
284 register v1di xmm7 __asm__("%xmm7");
287 return (unsigned long)xmm0;
289 return (unsigned long)xmm1;
291 return (unsigned long)xmm2;
293 return (unsigned long)xmm3;
295 return (unsigned long)xmm4;
297 return (unsigned long)xmm5;
299 return (unsigned long)xmm6;
301 return (unsigned long)xmm7;
306 bool is_intel_cpu(void);
308 struct kvm_x86_state;
309 struct kvm_x86_state *vcpu_save_state(struct kvm_vm *vm, uint32_t vcpuid);
310 void vcpu_load_state(struct kvm_vm *vm, uint32_t vcpuid,
311 struct kvm_x86_state *state);
313 struct kvm_msr_list *kvm_get_msr_index_list(void);
315 struct kvm_cpuid2 *kvm_get_supported_cpuid(void);
316 void vcpu_set_cpuid(struct kvm_vm *vm, uint32_t vcpuid,
317 struct kvm_cpuid2 *cpuid);
319 struct kvm_cpuid_entry2 *
320 kvm_get_supported_cpuid_index(uint32_t function, uint32_t index);
322 static inline struct kvm_cpuid_entry2 *
323 kvm_get_supported_cpuid_entry(uint32_t function)
325 return kvm_get_supported_cpuid_index(function, 0);
328 uint64_t vcpu_get_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index);
329 int _vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index,
331 void vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index,
334 uint32_t kvm_get_cpuid_max_basic(void);
335 uint32_t kvm_get_cpuid_max_extended(void);
336 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits);
339 * Basic CPU control in CR0
341 #define X86_CR0_PE (1UL<<0) /* Protection Enable */
342 #define X86_CR0_MP (1UL<<1) /* Monitor Coprocessor */
343 #define X86_CR0_EM (1UL<<2) /* Emulation */
344 #define X86_CR0_TS (1UL<<3) /* Task Switched */
345 #define X86_CR0_ET (1UL<<4) /* Extension Type */
346 #define X86_CR0_NE (1UL<<5) /* Numeric Error */
347 #define X86_CR0_WP (1UL<<16) /* Write Protect */
348 #define X86_CR0_AM (1UL<<18) /* Alignment Mask */
349 #define X86_CR0_NW (1UL<<29) /* Not Write-through */
350 #define X86_CR0_CD (1UL<<30) /* Cache Disable */
351 #define X86_CR0_PG (1UL<<31) /* Paging */
353 #define APIC_BASE_MSR 0x800
354 #define X2APIC_ENABLE (1UL << 10)
355 #define APIC_ICR 0x300
356 #define APIC_DEST_SELF 0x40000
357 #define APIC_DEST_ALLINC 0x80000
358 #define APIC_DEST_ALLBUT 0xC0000
359 #define APIC_ICR_RR_MASK 0x30000
360 #define APIC_ICR_RR_INVALID 0x00000
361 #define APIC_ICR_RR_INPROG 0x10000
362 #define APIC_ICR_RR_VALID 0x20000
363 #define APIC_INT_LEVELTRIG 0x08000
364 #define APIC_INT_ASSERT 0x04000
365 #define APIC_ICR_BUSY 0x01000
366 #define APIC_DEST_LOGICAL 0x00800
367 #define APIC_DEST_PHYSICAL 0x00000
368 #define APIC_DM_FIXED 0x00000
369 #define APIC_DM_FIXED_MASK 0x00700
370 #define APIC_DM_LOWEST 0x00100
371 #define APIC_DM_SMI 0x00200
372 #define APIC_DM_REMRD 0x00300
373 #define APIC_DM_NMI 0x00400
374 #define APIC_DM_INIT 0x00500
375 #define APIC_DM_STARTUP 0x00600
376 #define APIC_DM_EXTINT 0x00700
377 #define APIC_VECTOR_MASK 0x000FF
378 #define APIC_ICR2 0x310
380 /* VMX_EPT_VPID_CAP bits */
381 #define VMX_EPT_VPID_CAP_AD_BITS (1ULL << 21)
383 #endif /* SELFTEST_KVM_PROCESSOR_H */