1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * tools/testing/selftests/kvm/include/x86_64/processor.h
5 * Copyright (C) 2018, Google LLC.
8 #ifndef SELFTEST_KVM_PROCESSOR_H
9 #define SELFTEST_KVM_PROCESSOR_H
14 #include <asm/msr-index.h>
16 #define X86_EFLAGS_FIXED (1u << 1)
18 #define X86_CR4_VME (1ul << 0)
19 #define X86_CR4_PVI (1ul << 1)
20 #define X86_CR4_TSD (1ul << 2)
21 #define X86_CR4_DE (1ul << 3)
22 #define X86_CR4_PSE (1ul << 4)
23 #define X86_CR4_PAE (1ul << 5)
24 #define X86_CR4_MCE (1ul << 6)
25 #define X86_CR4_PGE (1ul << 7)
26 #define X86_CR4_PCE (1ul << 8)
27 #define X86_CR4_OSFXSR (1ul << 9)
28 #define X86_CR4_OSXMMEXCPT (1ul << 10)
29 #define X86_CR4_UMIP (1ul << 11)
30 #define X86_CR4_LA57 (1ul << 12)
31 #define X86_CR4_VMXE (1ul << 13)
32 #define X86_CR4_SMXE (1ul << 14)
33 #define X86_CR4_FSGSBASE (1ul << 16)
34 #define X86_CR4_PCIDE (1ul << 17)
35 #define X86_CR4_OSXSAVE (1ul << 18)
36 #define X86_CR4_SMEP (1ul << 20)
37 #define X86_CR4_SMAP (1ul << 21)
38 #define X86_CR4_PKE (1ul << 22)
41 #define CPUID_VMX (1ul << 5)
42 #define CPUID_SMX (1ul << 6)
43 #define CPUID_PCID (1ul << 17)
44 #define CPUID_XSAVE (1ul << 26)
47 #define CPUID_FSGSBASE (1ul << 0)
48 #define CPUID_SMEP (1ul << 7)
49 #define CPUID_SMAP (1ul << 20)
52 #define CPUID_UMIP (1ul << 2)
53 #define CPUID_PKU (1ul << 3)
54 #define CPUID_LA57 (1ul << 16)
56 #define UNEXPECTED_VECTOR_PORT 0xfff0u
58 /* General Registers in 64-Bit Mode */
81 unsigned base1:8, type:4, s:1, dpl:2, p:1;
82 unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8;
85 } __attribute__((packed));
90 } __attribute__((packed));
92 static inline uint64_t get_desc64_base(const struct desc64 *desc)
94 return ((uint64_t)desc->base3 << 32) |
95 (desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
98 static inline uint64_t rdtsc(void)
103 * The lfence is to wait (on Intel CPUs) until all previous
104 * instructions have been executed. If software requires RDTSC to be
105 * executed prior to execution of any subsequent instruction, it can
106 * execute LFENCE immediately after RDTSC
108 __asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx));
109 tsc_val = ((uint64_t)edx) << 32 | eax;
113 static inline uint64_t rdtscp(uint32_t *aux)
117 __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux));
118 return ((uint64_t)edx) << 32 | eax;
121 static inline uint64_t rdmsr(uint32_t msr)
125 __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory");
127 return a | ((uint64_t) d << 32);
130 static inline void wrmsr(uint32_t msr, uint64_t value)
133 uint32_t d = value >> 32;
135 __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory");
139 static inline uint16_t inw(uint16_t port)
143 __asm__ __volatile__("in %%dx, %%ax"
144 : /* output */ "=a" (tmp)
145 : /* input */ "d" (port));
150 static inline uint16_t get_es(void)
154 __asm__ __volatile__("mov %%es, %[es]"
155 : /* output */ [es]"=rm"(es));
159 static inline uint16_t get_cs(void)
163 __asm__ __volatile__("mov %%cs, %[cs]"
164 : /* output */ [cs]"=rm"(cs));
168 static inline uint16_t get_ss(void)
172 __asm__ __volatile__("mov %%ss, %[ss]"
173 : /* output */ [ss]"=rm"(ss));
177 static inline uint16_t get_ds(void)
181 __asm__ __volatile__("mov %%ds, %[ds]"
182 : /* output */ [ds]"=rm"(ds));
186 static inline uint16_t get_fs(void)
190 __asm__ __volatile__("mov %%fs, %[fs]"
191 : /* output */ [fs]"=rm"(fs));
195 static inline uint16_t get_gs(void)
199 __asm__ __volatile__("mov %%gs, %[gs]"
200 : /* output */ [gs]"=rm"(gs));
204 static inline uint16_t get_tr(void)
208 __asm__ __volatile__("str %[tr]"
209 : /* output */ [tr]"=rm"(tr));
213 static inline uint64_t get_cr0(void)
217 __asm__ __volatile__("mov %%cr0, %[cr0]"
218 : /* output */ [cr0]"=r"(cr0));
222 static inline uint64_t get_cr3(void)
226 __asm__ __volatile__("mov %%cr3, %[cr3]"
227 : /* output */ [cr3]"=r"(cr3));
231 static inline uint64_t get_cr4(void)
235 __asm__ __volatile__("mov %%cr4, %[cr4]"
236 : /* output */ [cr4]"=r"(cr4));
240 static inline void set_cr4(uint64_t val)
242 __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory");
245 static inline struct desc_ptr get_gdt(void)
248 __asm__ __volatile__("sgdt %[gdt]"
249 : /* output */ [gdt]"=m"(gdt));
253 static inline struct desc_ptr get_idt(void)
256 __asm__ __volatile__("sidt %[idt]"
257 : /* output */ [idt]"=m"(idt));
261 static inline void outl(uint16_t port, uint32_t value)
263 __asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value));
266 #define SET_XMM(__var, __xmm) \
267 asm volatile("movq %0, %%"#__xmm : : "r"(__var) : #__xmm)
269 static inline void set_xmm(int n, unsigned long val)
299 typedef unsigned long v1di __attribute__ ((vector_size (8)));
300 static inline unsigned long get_xmm(int n)
302 assert(n >= 0 && n <= 7);
304 register v1di xmm0 __asm__("%xmm0");
305 register v1di xmm1 __asm__("%xmm1");
306 register v1di xmm2 __asm__("%xmm2");
307 register v1di xmm3 __asm__("%xmm3");
308 register v1di xmm4 __asm__("%xmm4");
309 register v1di xmm5 __asm__("%xmm5");
310 register v1di xmm6 __asm__("%xmm6");
311 register v1di xmm7 __asm__("%xmm7");
314 return (unsigned long)xmm0;
316 return (unsigned long)xmm1;
318 return (unsigned long)xmm2;
320 return (unsigned long)xmm3;
322 return (unsigned long)xmm4;
324 return (unsigned long)xmm5;
326 return (unsigned long)xmm6;
328 return (unsigned long)xmm7;
333 bool is_intel_cpu(void);
335 struct kvm_x86_state;
336 struct kvm_x86_state *vcpu_save_state(struct kvm_vm *vm, uint32_t vcpuid);
337 void vcpu_load_state(struct kvm_vm *vm, uint32_t vcpuid,
338 struct kvm_x86_state *state);
340 struct kvm_msr_list *kvm_get_msr_index_list(void);
342 struct kvm_cpuid2 *kvm_get_supported_cpuid(void);
343 void vcpu_set_cpuid(struct kvm_vm *vm, uint32_t vcpuid,
344 struct kvm_cpuid2 *cpuid);
346 struct kvm_cpuid_entry2 *
347 kvm_get_supported_cpuid_index(uint32_t function, uint32_t index);
349 static inline struct kvm_cpuid_entry2 *
350 kvm_get_supported_cpuid_entry(uint32_t function)
352 return kvm_get_supported_cpuid_index(function, 0);
355 uint64_t vcpu_get_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index);
356 int _vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index,
358 void vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index,
361 uint32_t kvm_get_cpuid_max_basic(void);
362 uint32_t kvm_get_cpuid_max_extended(void);
363 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits);
366 uint64_t rax, rcx, rdx, rbx;
367 uint64_t rbp, rsi, rdi;
368 uint64_t r8, r9, r10, r11;
369 uint64_t r12, r13, r14, r15;
377 void vm_init_descriptor_tables(struct kvm_vm *vm);
378 void vcpu_init_descriptor_tables(struct kvm_vm *vm, uint32_t vcpuid);
379 void vm_handle_exception(struct kvm_vm *vm, int vector,
380 void (*handler)(struct ex_regs *));
383 * set_cpuid() - overwrites a matching cpuid entry with the provided value.
384 * matches based on ent->function && ent->index. returns true
385 * if a match was found and successfully overwritten.
386 * @cpuid: the kvm cpuid list to modify.
387 * @ent: cpuid entry to insert
389 bool set_cpuid(struct kvm_cpuid2 *cpuid, struct kvm_cpuid_entry2 *ent);
391 uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2,
395 * Basic CPU control in CR0
397 #define X86_CR0_PE (1UL<<0) /* Protection Enable */
398 #define X86_CR0_MP (1UL<<1) /* Monitor Coprocessor */
399 #define X86_CR0_EM (1UL<<2) /* Emulation */
400 #define X86_CR0_TS (1UL<<3) /* Task Switched */
401 #define X86_CR0_ET (1UL<<4) /* Extension Type */
402 #define X86_CR0_NE (1UL<<5) /* Numeric Error */
403 #define X86_CR0_WP (1UL<<16) /* Write Protect */
404 #define X86_CR0_AM (1UL<<18) /* Alignment Mask */
405 #define X86_CR0_NW (1UL<<29) /* Not Write-through */
406 #define X86_CR0_CD (1UL<<30) /* Cache Disable */
407 #define X86_CR0_PG (1UL<<31) /* Paging */
409 #define APIC_BASE_MSR 0x800
410 #define X2APIC_ENABLE (1UL << 10)
411 #define APIC_ICR 0x300
412 #define APIC_DEST_SELF 0x40000
413 #define APIC_DEST_ALLINC 0x80000
414 #define APIC_DEST_ALLBUT 0xC0000
415 #define APIC_ICR_RR_MASK 0x30000
416 #define APIC_ICR_RR_INVALID 0x00000
417 #define APIC_ICR_RR_INPROG 0x10000
418 #define APIC_ICR_RR_VALID 0x20000
419 #define APIC_INT_LEVELTRIG 0x08000
420 #define APIC_INT_ASSERT 0x04000
421 #define APIC_ICR_BUSY 0x01000
422 #define APIC_DEST_LOGICAL 0x00800
423 #define APIC_DEST_PHYSICAL 0x00000
424 #define APIC_DM_FIXED 0x00000
425 #define APIC_DM_FIXED_MASK 0x00700
426 #define APIC_DM_LOWEST 0x00100
427 #define APIC_DM_SMI 0x00200
428 #define APIC_DM_REMRD 0x00300
429 #define APIC_DM_NMI 0x00400
430 #define APIC_DM_INIT 0x00500
431 #define APIC_DM_STARTUP 0x00600
432 #define APIC_DM_EXTINT 0x00700
433 #define APIC_VECTOR_MASK 0x000FF
434 #define APIC_ICR2 0x310
436 /* VMX_EPT_VPID_CAP bits */
437 #define VMX_EPT_VPID_CAP_AD_BITS (1ULL << 21)
439 #endif /* SELFTEST_KVM_PROCESSOR_H */