1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * tools/testing/selftests/kvm/include/x86_64/processor.h
5 * Copyright (C) 2018, Google LLC.
8 #ifndef SELFTEST_KVM_PROCESSOR_H
9 #define SELFTEST_KVM_PROCESSOR_H
14 #include <asm/msr-index.h>
16 #include "../kvm_util.h"
18 #define X86_EFLAGS_FIXED (1u << 1)
20 #define X86_CR4_VME (1ul << 0)
21 #define X86_CR4_PVI (1ul << 1)
22 #define X86_CR4_TSD (1ul << 2)
23 #define X86_CR4_DE (1ul << 3)
24 #define X86_CR4_PSE (1ul << 4)
25 #define X86_CR4_PAE (1ul << 5)
26 #define X86_CR4_MCE (1ul << 6)
27 #define X86_CR4_PGE (1ul << 7)
28 #define X86_CR4_PCE (1ul << 8)
29 #define X86_CR4_OSFXSR (1ul << 9)
30 #define X86_CR4_OSXMMEXCPT (1ul << 10)
31 #define X86_CR4_UMIP (1ul << 11)
32 #define X86_CR4_LA57 (1ul << 12)
33 #define X86_CR4_VMXE (1ul << 13)
34 #define X86_CR4_SMXE (1ul << 14)
35 #define X86_CR4_FSGSBASE (1ul << 16)
36 #define X86_CR4_PCIDE (1ul << 17)
37 #define X86_CR4_OSXSAVE (1ul << 18)
38 #define X86_CR4_SMEP (1ul << 20)
39 #define X86_CR4_SMAP (1ul << 21)
40 #define X86_CR4_PKE (1ul << 22)
43 #define CPUID_VMX (1ul << 5)
44 #define CPUID_SMX (1ul << 6)
45 #define CPUID_PCID (1ul << 17)
46 #define CPUID_XSAVE (1ul << 26)
49 #define CPUID_FSGSBASE (1ul << 0)
50 #define CPUID_SMEP (1ul << 7)
51 #define CPUID_SMAP (1ul << 20)
54 #define CPUID_UMIP (1ul << 2)
55 #define CPUID_PKU (1ul << 3)
56 #define CPUID_LA57 (1ul << 16)
58 /* CPUID.0x8000_0001.EDX */
59 #define CPUID_GBPAGES (1ul << 26)
61 #define UNEXPECTED_VECTOR_PORT 0xfff0u
63 /* General Registers in 64-Bit Mode */
86 unsigned base1:8, type:4, s:1, dpl:2, p:1;
87 unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8;
90 } __attribute__((packed));
95 } __attribute__((packed));
97 static inline uint64_t get_desc64_base(const struct desc64 *desc)
99 return ((uint64_t)desc->base3 << 32) |
100 (desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
103 static inline uint64_t rdtsc(void)
108 * The lfence is to wait (on Intel CPUs) until all previous
109 * instructions have been executed. If software requires RDTSC to be
110 * executed prior to execution of any subsequent instruction, it can
111 * execute LFENCE immediately after RDTSC
113 __asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx));
114 tsc_val = ((uint64_t)edx) << 32 | eax;
118 static inline uint64_t rdtscp(uint32_t *aux)
122 __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux));
123 return ((uint64_t)edx) << 32 | eax;
126 static inline uint64_t rdmsr(uint32_t msr)
130 __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory");
132 return a | ((uint64_t) d << 32);
135 static inline void wrmsr(uint32_t msr, uint64_t value)
138 uint32_t d = value >> 32;
140 __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory");
144 static inline uint16_t inw(uint16_t port)
148 __asm__ __volatile__("in %%dx, %%ax"
149 : /* output */ "=a" (tmp)
150 : /* input */ "d" (port));
155 static inline uint16_t get_es(void)
159 __asm__ __volatile__("mov %%es, %[es]"
160 : /* output */ [es]"=rm"(es));
164 static inline uint16_t get_cs(void)
168 __asm__ __volatile__("mov %%cs, %[cs]"
169 : /* output */ [cs]"=rm"(cs));
173 static inline uint16_t get_ss(void)
177 __asm__ __volatile__("mov %%ss, %[ss]"
178 : /* output */ [ss]"=rm"(ss));
182 static inline uint16_t get_ds(void)
186 __asm__ __volatile__("mov %%ds, %[ds]"
187 : /* output */ [ds]"=rm"(ds));
191 static inline uint16_t get_fs(void)
195 __asm__ __volatile__("mov %%fs, %[fs]"
196 : /* output */ [fs]"=rm"(fs));
200 static inline uint16_t get_gs(void)
204 __asm__ __volatile__("mov %%gs, %[gs]"
205 : /* output */ [gs]"=rm"(gs));
209 static inline uint16_t get_tr(void)
213 __asm__ __volatile__("str %[tr]"
214 : /* output */ [tr]"=rm"(tr));
218 static inline uint64_t get_cr0(void)
222 __asm__ __volatile__("mov %%cr0, %[cr0]"
223 : /* output */ [cr0]"=r"(cr0));
227 static inline uint64_t get_cr3(void)
231 __asm__ __volatile__("mov %%cr3, %[cr3]"
232 : /* output */ [cr3]"=r"(cr3));
236 static inline uint64_t get_cr4(void)
240 __asm__ __volatile__("mov %%cr4, %[cr4]"
241 : /* output */ [cr4]"=r"(cr4));
245 static inline void set_cr4(uint64_t val)
247 __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory");
250 static inline struct desc_ptr get_gdt(void)
253 __asm__ __volatile__("sgdt %[gdt]"
254 : /* output */ [gdt]"=m"(gdt));
258 static inline struct desc_ptr get_idt(void)
261 __asm__ __volatile__("sidt %[idt]"
262 : /* output */ [idt]"=m"(idt));
266 static inline void outl(uint16_t port, uint32_t value)
268 __asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value));
271 static inline void cpuid(uint32_t *eax, uint32_t *ebx,
272 uint32_t *ecx, uint32_t *edx)
274 /* ecx is often an input as well as an output. */
280 : "0" (*eax), "2" (*ecx)
284 #define SET_XMM(__var, __xmm) \
285 asm volatile("movq %0, %%"#__xmm : : "r"(__var) : #__xmm)
287 static inline void set_xmm(int n, unsigned long val)
317 typedef unsigned long v1di __attribute__ ((vector_size (8)));
318 static inline unsigned long get_xmm(int n)
320 assert(n >= 0 && n <= 7);
322 register v1di xmm0 __asm__("%xmm0");
323 register v1di xmm1 __asm__("%xmm1");
324 register v1di xmm2 __asm__("%xmm2");
325 register v1di xmm3 __asm__("%xmm3");
326 register v1di xmm4 __asm__("%xmm4");
327 register v1di xmm5 __asm__("%xmm5");
328 register v1di xmm6 __asm__("%xmm6");
329 register v1di xmm7 __asm__("%xmm7");
332 return (unsigned long)xmm0;
334 return (unsigned long)xmm1;
336 return (unsigned long)xmm2;
338 return (unsigned long)xmm3;
340 return (unsigned long)xmm4;
342 return (unsigned long)xmm5;
344 return (unsigned long)xmm6;
346 return (unsigned long)xmm7;
351 bool is_intel_cpu(void);
353 struct kvm_x86_state;
354 struct kvm_x86_state *vcpu_save_state(struct kvm_vm *vm, uint32_t vcpuid);
355 void vcpu_load_state(struct kvm_vm *vm, uint32_t vcpuid,
356 struct kvm_x86_state *state);
358 struct kvm_msr_list *kvm_get_msr_index_list(void);
359 uint64_t kvm_get_feature_msr(uint64_t msr_index);
360 struct kvm_cpuid2 *kvm_get_supported_cpuid(void);
362 struct kvm_cpuid2 *vcpu_get_cpuid(struct kvm_vm *vm, uint32_t vcpuid);
363 void vcpu_set_cpuid(struct kvm_vm *vm, uint32_t vcpuid,
364 struct kvm_cpuid2 *cpuid);
366 struct kvm_cpuid_entry2 *
367 kvm_get_supported_cpuid_index(uint32_t function, uint32_t index);
369 static inline struct kvm_cpuid_entry2 *
370 kvm_get_supported_cpuid_entry(uint32_t function)
372 return kvm_get_supported_cpuid_index(function, 0);
375 uint64_t vcpu_get_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index);
376 int _vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index,
378 void vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index,
381 uint32_t kvm_get_cpuid_max_basic(void);
382 uint32_t kvm_get_cpuid_max_extended(void);
383 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits);
386 uint64_t rax, rcx, rdx, rbx;
387 uint64_t rbp, rsi, rdi;
388 uint64_t r8, r9, r10, r11;
389 uint64_t r12, r13, r14, r15;
397 void vm_init_descriptor_tables(struct kvm_vm *vm);
398 void vcpu_init_descriptor_tables(struct kvm_vm *vm, uint32_t vcpuid);
399 void vm_handle_exception(struct kvm_vm *vm, int vector,
400 void (*handler)(struct ex_regs *));
402 uint64_t vm_get_page_table_entry(struct kvm_vm *vm, int vcpuid, uint64_t vaddr);
403 void vm_set_page_table_entry(struct kvm_vm *vm, int vcpuid, uint64_t vaddr,
407 * set_cpuid() - overwrites a matching cpuid entry with the provided value.
408 * matches based on ent->function && ent->index. returns true
409 * if a match was found and successfully overwritten.
410 * @cpuid: the kvm cpuid list to modify.
411 * @ent: cpuid entry to insert
413 bool set_cpuid(struct kvm_cpuid2 *cpuid, struct kvm_cpuid_entry2 *ent);
415 uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2,
418 struct kvm_cpuid2 *kvm_get_supported_hv_cpuid(void);
419 void vcpu_set_hv_cpuid(struct kvm_vm *vm, uint32_t vcpuid);
420 struct kvm_cpuid2 *vcpu_get_supported_hv_cpuid(struct kvm_vm *vm, uint32_t vcpuid);
423 X86_PAGE_SIZE_4K = 0,
427 void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
428 enum x86_page_size page_size);
431 * Basic CPU control in CR0
433 #define X86_CR0_PE (1UL<<0) /* Protection Enable */
434 #define X86_CR0_MP (1UL<<1) /* Monitor Coprocessor */
435 #define X86_CR0_EM (1UL<<2) /* Emulation */
436 #define X86_CR0_TS (1UL<<3) /* Task Switched */
437 #define X86_CR0_ET (1UL<<4) /* Extension Type */
438 #define X86_CR0_NE (1UL<<5) /* Numeric Error */
439 #define X86_CR0_WP (1UL<<16) /* Write Protect */
440 #define X86_CR0_AM (1UL<<18) /* Alignment Mask */
441 #define X86_CR0_NW (1UL<<29) /* Not Write-through */
442 #define X86_CR0_CD (1UL<<30) /* Cache Disable */
443 #define X86_CR0_PG (1UL<<31) /* Paging */
445 /* VMX_EPT_VPID_CAP bits */
446 #define VMX_EPT_VPID_CAP_AD_BITS (1ULL << 21)
448 #endif /* SELFTEST_KVM_PROCESSOR_H */