2 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of version 2 of the GNU General Public License as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/workqueue.h>
17 #include <linux/libnvdimm.h>
18 #include <linux/vmalloc.h>
19 #include <linux/device.h>
20 #include <linux/module.h>
21 #include <linux/mutex.h>
22 #include <linux/ndctl.h>
23 #include <linux/sizes.h>
24 #include <linux/list.h>
25 #include <linux/slab.h>
29 #include "nfit_test.h"
30 #include "../watermark.h"
32 #include <asm/mcsafe_test.h>
35 * Generate an NFIT table to describe the following topology:
37 * BUS0: Interleaved PMEM regions, and aliasing with BLK regions
39 * (a) (b) DIMM BLK-REGION
40 * +----------+--------------+----------+---------+
41 * +------+ | blk2.0 | pm0.0 | blk2.1 | pm1.0 | 0 region2
42 * | imc0 +--+- - - - - region0 - - - -+----------+ +
43 * +--+---+ | blk3.0 | pm0.0 | blk3.1 | pm1.0 | 1 region3
44 * | +----------+--------------v----------v v
48 * | +-------------------------^----------^ ^
49 * +--+---+ | blk4.0 | pm1.0 | 2 region4
50 * | imc1 +--+-------------------------+----------+ +
51 * +------+ | blk5.0 | pm1.0 | 3 region5
52 * +-------------------------+----------+-+-------+
56 * +--+---+ (Hotplug DIMM)
57 * | +----------------------------------------------+
58 * +--+---+ | blk6.0/pm7.0 | 4 region6/7
59 * | imc0 +--+----------------------------------------------+
63 * *) In this layout we have four dimms and two memory controllers in one
64 * socket. Each unique interface (BLK or PMEM) to DPA space
65 * is identified by a region device with a dynamically assigned id.
67 * *) The first portion of dimm0 and dimm1 are interleaved as REGION0.
68 * A single PMEM namespace "pm0.0" is created using half of the
69 * REGION0 SPA-range. REGION0 spans dimm0 and dimm1. PMEM namespace
70 * allocate from from the bottom of a region. The unallocated
71 * portion of REGION0 aliases with REGION2 and REGION3. That
72 * unallacted capacity is reclaimed as BLK namespaces ("blk2.0" and
73 * "blk3.0") starting at the base of each DIMM to offset (a) in those
74 * DIMMs. "pm0.0", "blk2.0" and "blk3.0" are free-form readable
75 * names that can be assigned to a namespace.
77 * *) In the last portion of dimm0 and dimm1 we have an interleaved
78 * SPA range, REGION1, that spans those two dimms as well as dimm2
79 * and dimm3. Some of REGION1 allocated to a PMEM namespace named
80 * "pm1.0" the rest is reclaimed in 4 BLK namespaces (for each
81 * dimm in the interleave set), "blk2.1", "blk3.1", "blk4.0", and
84 * *) The portion of dimm2 and dimm3 that do not participate in the
85 * REGION1 interleaved SPA range (i.e. the DPA address below offset
86 * (b) are also included in the "blk4.0" and "blk5.0" namespaces.
87 * Note, that BLK namespaces need not be contiguous in DPA-space, and
88 * can consume aliased capacity from multiple interleave sets.
90 * BUS1: Legacy NVDIMM (single contiguous range)
93 * +---------------------+
94 * |---------------------|
96 * |---------------------|
97 * +---------------------+
99 * *) A NFIT-table may describe a simple system-physical-address range
100 * with no BLK aliasing. This type of region may optionally
101 * reference an NVDIMM.
108 NUM_SPA = NUM_PM + NUM_DCR + NUM_BDW,
109 NUM_MEM = NUM_DCR + NUM_BDW + 2 /* spa0 iset */
110 + 4 /* spa1 iset */ + 1 /* spa11 iset */,
112 LABEL_SIZE = SZ_128K,
113 SPA_VCD_SIZE = SZ_4M,
114 SPA0_SIZE = DIMM_SIZE,
115 SPA1_SIZE = DIMM_SIZE*2,
116 SPA2_SIZE = DIMM_SIZE,
119 NUM_NFITS = 2, /* permit testing multiple NFITs per system */
122 struct nfit_test_dcr {
125 __u8 aperature[BDW_SIZE];
128 #define NFIT_DIMM_HANDLE(node, socket, imc, chan, dimm) \
129 (((node & 0xfff) << 16) | ((socket & 0xf) << 12) \
130 | ((imc & 0xf) << 8) | ((chan & 0xf) << 4) | (dimm & 0xf))
132 static u32 handle[] = {
133 [0] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 0),
134 [1] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 1),
135 [2] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 0),
136 [3] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 1),
137 [4] = NFIT_DIMM_HANDLE(0, 1, 0, 0, 0),
138 [5] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 0),
139 [6] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 1),
142 static unsigned long dimm_fail_cmd_flags[NUM_DCR];
143 static int dimm_fail_cmd_code[NUM_DCR];
145 struct nfit_test_fw {
146 enum intel_fw_update_state state;
154 struct acpi_nfit_desc acpi_desc;
155 struct platform_device pdev;
156 struct list_head resources;
165 dma_addr_t *dimm_dma;
167 dma_addr_t *flush_dma;
169 dma_addr_t *label_dma;
171 dma_addr_t *spa_set_dma;
172 struct nfit_test_dcr **dcr;
174 int (*alloc)(struct nfit_test *t);
175 void (*setup)(struct nfit_test *t);
177 union acpi_object **_fit;
180 struct nd_cmd_ars_status *ars_status;
181 unsigned long deadline;
184 struct device *dimm_dev[NUM_DCR];
185 struct nd_intel_smart *smart;
186 struct nd_intel_smart_threshold *smart_threshold;
187 struct badrange badrange;
188 struct work_struct work;
189 struct nfit_test_fw *fw;
192 static struct workqueue_struct *nfit_wq;
194 static struct nfit_test *to_nfit_test(struct device *dev)
196 struct platform_device *pdev = to_platform_device(dev);
198 return container_of(pdev, struct nfit_test, pdev);
201 static int nd_intel_test_get_fw_info(struct nfit_test *t,
202 struct nd_intel_fw_info *nd_cmd, unsigned int buf_len,
205 struct device *dev = &t->pdev.dev;
206 struct nfit_test_fw *fw = &t->fw[idx];
208 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p, buf_len: %u, idx: %d\n",
209 __func__, t, nd_cmd, buf_len, idx);
211 if (buf_len < sizeof(*nd_cmd))
215 nd_cmd->storage_size = INTEL_FW_STORAGE_SIZE;
216 nd_cmd->max_send_len = INTEL_FW_MAX_SEND_LEN;
217 nd_cmd->query_interval = INTEL_FW_QUERY_INTERVAL;
218 nd_cmd->max_query_time = INTEL_FW_QUERY_MAX_TIME;
219 nd_cmd->update_cap = 0;
220 nd_cmd->fis_version = INTEL_FW_FIS_VERSION;
221 nd_cmd->run_version = 0;
222 nd_cmd->updated_version = fw->version;
227 static int nd_intel_test_start_update(struct nfit_test *t,
228 struct nd_intel_fw_start *nd_cmd, unsigned int buf_len,
231 struct device *dev = &t->pdev.dev;
232 struct nfit_test_fw *fw = &t->fw[idx];
234 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
235 __func__, t, nd_cmd, buf_len, idx);
237 if (buf_len < sizeof(*nd_cmd))
240 if (fw->state != FW_STATE_NEW) {
241 /* extended status, FW update in progress */
242 nd_cmd->status = 0x10007;
246 fw->state = FW_STATE_IN_PROGRESS;
248 fw->size_received = 0;
250 nd_cmd->context = fw->context;
252 dev_dbg(dev, "%s: context issued: %#x\n", __func__, nd_cmd->context);
257 static int nd_intel_test_send_data(struct nfit_test *t,
258 struct nd_intel_fw_send_data *nd_cmd, unsigned int buf_len,
261 struct device *dev = &t->pdev.dev;
262 struct nfit_test_fw *fw = &t->fw[idx];
263 u32 *status = (u32 *)&nd_cmd->data[nd_cmd->length];
265 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
266 __func__, t, nd_cmd, buf_len, idx);
268 if (buf_len < sizeof(*nd_cmd))
272 dev_dbg(dev, "%s: cmd->status: %#x\n", __func__, *status);
273 dev_dbg(dev, "%s: cmd->data[0]: %#x\n", __func__, nd_cmd->data[0]);
274 dev_dbg(dev, "%s: cmd->data[%u]: %#x\n", __func__, nd_cmd->length-1,
275 nd_cmd->data[nd_cmd->length-1]);
277 if (fw->state != FW_STATE_IN_PROGRESS) {
278 dev_dbg(dev, "%s: not in IN_PROGRESS state\n", __func__);
283 if (nd_cmd->context != fw->context) {
284 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
285 __func__, nd_cmd->context, fw->context);
291 * check offset + len > size of fw storage
292 * check length is > max send length
294 if (nd_cmd->offset + nd_cmd->length > INTEL_FW_STORAGE_SIZE ||
295 nd_cmd->length > INTEL_FW_MAX_SEND_LEN) {
297 dev_dbg(dev, "%s: buffer boundary violation\n", __func__);
301 fw->size_received += nd_cmd->length;
302 dev_dbg(dev, "%s: copying %u bytes, %u bytes so far\n",
303 __func__, nd_cmd->length, fw->size_received);
308 static int nd_intel_test_finish_fw(struct nfit_test *t,
309 struct nd_intel_fw_finish_update *nd_cmd,
310 unsigned int buf_len, int idx)
312 struct device *dev = &t->pdev.dev;
313 struct nfit_test_fw *fw = &t->fw[idx];
315 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
316 __func__, t, nd_cmd, buf_len, idx);
318 if (fw->state == FW_STATE_UPDATED) {
319 /* update already done, need cold boot */
320 nd_cmd->status = 0x20007;
324 dev_dbg(dev, "%s: context: %#x ctrl_flags: %#x\n",
325 __func__, nd_cmd->context, nd_cmd->ctrl_flags);
327 switch (nd_cmd->ctrl_flags) {
329 if (nd_cmd->context != fw->context) {
330 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
331 __func__, nd_cmd->context,
333 nd_cmd->status = 0x10007;
337 fw->state = FW_STATE_VERIFY;
338 /* set 1 second of time for firmware "update" */
339 fw->end_time = jiffies + HZ;
343 fw->size_received = 0;
344 /* successfully aborted status */
345 nd_cmd->status = 0x40007;
346 fw->state = FW_STATE_NEW;
347 dev_dbg(dev, "%s: abort successful\n", __func__);
350 default: /* bad control flag */
351 dev_warn(dev, "%s: unknown control flag: %#x\n",
352 __func__, nd_cmd->ctrl_flags);
359 static int nd_intel_test_finish_query(struct nfit_test *t,
360 struct nd_intel_fw_finish_query *nd_cmd,
361 unsigned int buf_len, int idx)
363 struct device *dev = &t->pdev.dev;
364 struct nfit_test_fw *fw = &t->fw[idx];
366 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
367 __func__, t, nd_cmd, buf_len, idx);
369 if (buf_len < sizeof(*nd_cmd))
372 if (nd_cmd->context != fw->context) {
373 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
374 __func__, nd_cmd->context, fw->context);
375 nd_cmd->status = 0x10007;
379 dev_dbg(dev, "%s context: %#x\n", __func__, nd_cmd->context);
383 nd_cmd->updated_fw_rev = 0;
385 dev_dbg(dev, "%s: new state\n", __func__);
388 case FW_STATE_IN_PROGRESS:
389 /* sequencing error */
390 nd_cmd->status = 0x40007;
391 nd_cmd->updated_fw_rev = 0;
392 dev_dbg(dev, "%s: sequence error\n", __func__);
395 case FW_STATE_VERIFY:
396 if (time_is_after_jiffies64(fw->end_time)) {
397 nd_cmd->updated_fw_rev = 0;
398 nd_cmd->status = 0x20007;
399 dev_dbg(dev, "%s: still verifying\n", __func__);
403 dev_dbg(dev, "%s: transition out verify\n", __func__);
404 fw->state = FW_STATE_UPDATED;
405 /* we are going to fall through if it's "done" */
406 case FW_STATE_UPDATED:
408 /* bogus test version */
409 fw->version = nd_cmd->updated_fw_rev =
410 INTEL_FW_FAKE_VERSION;
411 dev_dbg(dev, "%s: updated\n", __func__);
414 default: /* we should never get here */
421 static int nfit_test_cmd_get_config_size(struct nd_cmd_get_config_size *nd_cmd,
422 unsigned int buf_len)
424 if (buf_len < sizeof(*nd_cmd))
428 nd_cmd->config_size = LABEL_SIZE;
429 nd_cmd->max_xfer = SZ_4K;
434 static int nfit_test_cmd_get_config_data(struct nd_cmd_get_config_data_hdr
435 *nd_cmd, unsigned int buf_len, void *label)
437 unsigned int len, offset = nd_cmd->in_offset;
440 if (buf_len < sizeof(*nd_cmd))
442 if (offset >= LABEL_SIZE)
444 if (nd_cmd->in_length + sizeof(*nd_cmd) > buf_len)
448 len = min(nd_cmd->in_length, LABEL_SIZE - offset);
449 memcpy(nd_cmd->out_buf, label + offset, len);
450 rc = buf_len - sizeof(*nd_cmd) - len;
455 static int nfit_test_cmd_set_config_data(struct nd_cmd_set_config_hdr *nd_cmd,
456 unsigned int buf_len, void *label)
458 unsigned int len, offset = nd_cmd->in_offset;
462 if (buf_len < sizeof(*nd_cmd))
464 if (offset >= LABEL_SIZE)
466 if (nd_cmd->in_length + sizeof(*nd_cmd) + 4 > buf_len)
469 status = (void *)nd_cmd + nd_cmd->in_length + sizeof(*nd_cmd);
471 len = min(nd_cmd->in_length, LABEL_SIZE - offset);
472 memcpy(label + offset, nd_cmd->in_buf, len);
473 rc = buf_len - sizeof(*nd_cmd) - (len + 4);
478 #define NFIT_TEST_CLEAR_ERR_UNIT 256
480 static int nfit_test_cmd_ars_cap(struct nd_cmd_ars_cap *nd_cmd,
481 unsigned int buf_len)
485 if (buf_len < sizeof(*nd_cmd))
488 /* for testing, only store up to n records that fit within 4k */
489 ars_recs = SZ_4K / sizeof(struct nd_ars_record);
491 nd_cmd->max_ars_out = sizeof(struct nd_cmd_ars_status)
492 + ars_recs * sizeof(struct nd_ars_record);
493 nd_cmd->status = (ND_ARS_PERSISTENT | ND_ARS_VOLATILE) << 16;
494 nd_cmd->clear_err_unit = NFIT_TEST_CLEAR_ERR_UNIT;
499 static void post_ars_status(struct ars_state *ars_state,
500 struct badrange *badrange, u64 addr, u64 len)
502 struct nd_cmd_ars_status *ars_status;
503 struct nd_ars_record *ars_record;
504 struct badrange_entry *be;
505 u64 end = addr + len - 1;
508 ars_state->deadline = jiffies + 1*HZ;
509 ars_status = ars_state->ars_status;
510 ars_status->status = 0;
511 ars_status->address = addr;
512 ars_status->length = len;
513 ars_status->type = ND_ARS_PERSISTENT;
515 spin_lock(&badrange->lock);
516 list_for_each_entry(be, &badrange->list, list) {
517 u64 be_end = be->start + be->length - 1;
520 /* skip entries outside the range */
521 if (be_end < addr || be->start > end)
524 rstart = (be->start < addr) ? addr : be->start;
525 rend = (be_end < end) ? be_end : end;
526 ars_record = &ars_status->records[i];
527 ars_record->handle = 0;
528 ars_record->err_address = rstart;
529 ars_record->length = rend - rstart + 1;
532 spin_unlock(&badrange->lock);
533 ars_status->num_records = i;
534 ars_status->out_length = sizeof(struct nd_cmd_ars_status)
535 + i * sizeof(struct nd_ars_record);
538 static int nfit_test_cmd_ars_start(struct nfit_test *t,
539 struct ars_state *ars_state,
540 struct nd_cmd_ars_start *ars_start, unsigned int buf_len,
543 if (buf_len < sizeof(*ars_start))
546 spin_lock(&ars_state->lock);
547 if (time_before(jiffies, ars_state->deadline)) {
548 ars_start->status = NFIT_ARS_START_BUSY;
551 ars_start->status = 0;
552 ars_start->scrub_time = 1;
553 post_ars_status(ars_state, &t->badrange, ars_start->address,
557 spin_unlock(&ars_state->lock);
562 static int nfit_test_cmd_ars_status(struct ars_state *ars_state,
563 struct nd_cmd_ars_status *ars_status, unsigned int buf_len,
566 if (buf_len < ars_state->ars_status->out_length)
569 spin_lock(&ars_state->lock);
570 if (time_before(jiffies, ars_state->deadline)) {
571 memset(ars_status, 0, buf_len);
572 ars_status->status = NFIT_ARS_STATUS_BUSY;
573 ars_status->out_length = sizeof(*ars_status);
576 memcpy(ars_status, ars_state->ars_status,
577 ars_state->ars_status->out_length);
580 spin_unlock(&ars_state->lock);
584 static int nfit_test_cmd_clear_error(struct nfit_test *t,
585 struct nd_cmd_clear_error *clear_err,
586 unsigned int buf_len, int *cmd_rc)
588 const u64 mask = NFIT_TEST_CLEAR_ERR_UNIT - 1;
589 if (buf_len < sizeof(*clear_err))
592 if ((clear_err->address & mask) || (clear_err->length & mask))
595 badrange_forget(&t->badrange, clear_err->address, clear_err->length);
596 clear_err->status = 0;
597 clear_err->cleared = clear_err->length;
602 struct region_search_spa {
604 struct nd_region *region;
607 static int is_region_device(struct device *dev)
609 return !strncmp(dev->kobj.name, "region", 6);
612 static int nfit_test_search_region_spa(struct device *dev, void *data)
614 struct region_search_spa *ctx = data;
615 struct nd_region *nd_region;
616 resource_size_t ndr_end;
618 if (!is_region_device(dev))
621 nd_region = to_nd_region(dev);
622 ndr_end = nd_region->ndr_start + nd_region->ndr_size;
624 if (ctx->addr >= nd_region->ndr_start && ctx->addr < ndr_end) {
625 ctx->region = nd_region;
632 static int nfit_test_search_spa(struct nvdimm_bus *bus,
633 struct nd_cmd_translate_spa *spa)
636 struct nd_region *nd_region = NULL;
637 struct nvdimm *nvdimm = NULL;
638 struct nd_mapping *nd_mapping = NULL;
639 struct region_search_spa ctx = {
645 ret = device_for_each_child(&bus->dev, &ctx,
646 nfit_test_search_region_spa);
651 nd_region = ctx.region;
653 dpa = ctx.addr - nd_region->ndr_start;
656 * last dimm is selected for test
658 nd_mapping = &nd_region->mapping[nd_region->ndr_mappings - 1];
659 nvdimm = nd_mapping->nvdimm;
661 spa->devices[0].nfit_device_handle = handle[nvdimm->id];
662 spa->num_nvdimms = 1;
663 spa->devices[0].dpa = dpa;
668 static int nfit_test_cmd_translate_spa(struct nvdimm_bus *bus,
669 struct nd_cmd_translate_spa *spa, unsigned int buf_len)
671 if (buf_len < spa->translate_length)
674 if (nfit_test_search_spa(bus, spa) < 0 || !spa->num_nvdimms)
680 static int nfit_test_cmd_smart(struct nd_intel_smart *smart, unsigned int buf_len,
681 struct nd_intel_smart *smart_data)
683 if (buf_len < sizeof(*smart))
685 memcpy(smart, smart_data, sizeof(*smart));
689 static int nfit_test_cmd_smart_threshold(
690 struct nd_intel_smart_threshold *out,
691 unsigned int buf_len,
692 struct nd_intel_smart_threshold *smart_t)
694 if (buf_len < sizeof(*smart_t))
696 memcpy(out, smart_t, sizeof(*smart_t));
700 static void smart_notify(struct device *bus_dev,
701 struct device *dimm_dev, struct nd_intel_smart *smart,
702 struct nd_intel_smart_threshold *thresh)
704 dev_dbg(dimm_dev, "%s: alarm: %#x spares: %d (%d) mtemp: %d (%d) ctemp: %d (%d)\n",
705 __func__, thresh->alarm_control, thresh->spares,
706 smart->spares, thresh->media_temperature,
707 smart->media_temperature, thresh->ctrl_temperature,
708 smart->ctrl_temperature);
709 if (((thresh->alarm_control & ND_INTEL_SMART_SPARE_TRIP)
712 || ((thresh->alarm_control & ND_INTEL_SMART_TEMP_TRIP)
713 && smart->media_temperature
714 >= thresh->media_temperature)
715 || ((thresh->alarm_control & ND_INTEL_SMART_CTEMP_TRIP)
716 && smart->ctrl_temperature
717 >= thresh->ctrl_temperature)
718 || (smart->health != ND_INTEL_SMART_NON_CRITICAL_HEALTH)
719 || (smart->shutdown_state != 0)) {
720 device_lock(bus_dev);
721 __acpi_nvdimm_notify(dimm_dev, 0x81);
722 device_unlock(bus_dev);
726 static int nfit_test_cmd_smart_set_threshold(
727 struct nd_intel_smart_set_threshold *in,
728 unsigned int buf_len,
729 struct nd_intel_smart_threshold *thresh,
730 struct nd_intel_smart *smart,
731 struct device *bus_dev, struct device *dimm_dev)
735 size = sizeof(*in) - 4;
738 memcpy(thresh->data, in, size);
740 smart_notify(bus_dev, dimm_dev, smart, thresh);
745 static int nfit_test_cmd_smart_inject(
746 struct nd_intel_smart_inject *inj,
747 unsigned int buf_len,
748 struct nd_intel_smart_threshold *thresh,
749 struct nd_intel_smart *smart,
750 struct device *bus_dev, struct device *dimm_dev)
752 if (buf_len != sizeof(*inj))
755 if (inj->mtemp_enable)
756 smart->media_temperature = inj->media_temperature;
757 if (inj->spare_enable)
758 smart->spares = inj->spares;
759 if (inj->fatal_enable)
760 smart->health = ND_INTEL_SMART_FATAL_HEALTH;
761 if (inj->unsafe_shutdown_enable) {
762 smart->shutdown_state = 1;
763 smart->shutdown_count++;
766 smart_notify(bus_dev, dimm_dev, smart, thresh);
771 static void uc_error_notify(struct work_struct *work)
773 struct nfit_test *t = container_of(work, typeof(*t), work);
775 __acpi_nfit_notify(&t->pdev.dev, t, NFIT_NOTIFY_UC_MEMORY_ERROR);
778 static int nfit_test_cmd_ars_error_inject(struct nfit_test *t,
779 struct nd_cmd_ars_err_inj *err_inj, unsigned int buf_len)
783 if (buf_len != sizeof(*err_inj)) {
788 if (err_inj->err_inj_spa_range_length <= 0) {
793 rc = badrange_add(&t->badrange, err_inj->err_inj_spa_range_base,
794 err_inj->err_inj_spa_range_length);
798 if (err_inj->err_inj_options & (1 << ND_ARS_ERR_INJ_OPT_NOTIFY))
799 queue_work(nfit_wq, &t->work);
805 err_inj->status = NFIT_ARS_INJECT_INVALID;
809 static int nfit_test_cmd_ars_inject_clear(struct nfit_test *t,
810 struct nd_cmd_ars_err_inj_clr *err_clr, unsigned int buf_len)
814 if (buf_len != sizeof(*err_clr)) {
819 if (err_clr->err_inj_clr_spa_range_length <= 0) {
824 badrange_forget(&t->badrange, err_clr->err_inj_clr_spa_range_base,
825 err_clr->err_inj_clr_spa_range_length);
831 err_clr->status = NFIT_ARS_INJECT_INVALID;
835 static int nfit_test_cmd_ars_inject_status(struct nfit_test *t,
836 struct nd_cmd_ars_err_inj_stat *err_stat,
837 unsigned int buf_len)
839 struct badrange_entry *be;
840 int max = SZ_4K / sizeof(struct nd_error_stat_query_record);
843 err_stat->status = 0;
844 spin_lock(&t->badrange.lock);
845 list_for_each_entry(be, &t->badrange.list, list) {
846 err_stat->record[i].err_inj_stat_spa_range_base = be->start;
847 err_stat->record[i].err_inj_stat_spa_range_length = be->length;
852 spin_unlock(&t->badrange.lock);
853 err_stat->inj_err_rec_count = i;
858 static int nd_intel_test_cmd_set_lss_status(struct nfit_test *t,
859 struct nd_intel_lss *nd_cmd, unsigned int buf_len)
861 struct device *dev = &t->pdev.dev;
863 if (buf_len < sizeof(*nd_cmd))
866 switch (nd_cmd->enable) {
869 dev_dbg(dev, "%s: Latch System Shutdown Status disabled\n",
874 dev_dbg(dev, "%s: Latch System Shutdown Status enabled\n",
878 dev_warn(dev, "Unknown enable value: %#x\n", nd_cmd->enable);
879 nd_cmd->status = 0x3;
887 static int get_dimm(struct nfit_mem *nfit_mem, unsigned int func)
891 /* lookup per-dimm data */
892 for (i = 0; i < ARRAY_SIZE(handle); i++)
893 if (__to_nfit_memdev(nfit_mem)->device_handle == handle[i])
895 if (i >= ARRAY_SIZE(handle))
898 if ((1 << func) & dimm_fail_cmd_flags[i]) {
899 if (dimm_fail_cmd_code[i])
900 return dimm_fail_cmd_code[i];
907 static int nfit_test_ctl(struct nvdimm_bus_descriptor *nd_desc,
908 struct nvdimm *nvdimm, unsigned int cmd, void *buf,
909 unsigned int buf_len, int *cmd_rc)
911 struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
912 struct nfit_test *t = container_of(acpi_desc, typeof(*t), acpi_desc);
913 unsigned int func = cmd;
914 int i, rc = 0, __cmd_rc;
921 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
922 unsigned long cmd_mask = nvdimm_cmd_mask(nvdimm);
927 if (cmd == ND_CMD_CALL) {
928 struct nd_cmd_pkg *call_pkg = buf;
930 buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
931 buf = (void *) call_pkg->nd_payload;
932 func = call_pkg->nd_command;
933 if (call_pkg->nd_family != nfit_mem->family)
936 i = get_dimm(nfit_mem, func);
941 case ND_INTEL_ENABLE_LSS_STATUS:
942 return nd_intel_test_cmd_set_lss_status(t,
944 case ND_INTEL_FW_GET_INFO:
945 return nd_intel_test_get_fw_info(t, buf,
946 buf_len, i - t->dcr_idx);
947 case ND_INTEL_FW_START_UPDATE:
948 return nd_intel_test_start_update(t, buf,
949 buf_len, i - t->dcr_idx);
950 case ND_INTEL_FW_SEND_DATA:
951 return nd_intel_test_send_data(t, buf,
952 buf_len, i - t->dcr_idx);
953 case ND_INTEL_FW_FINISH_UPDATE:
954 return nd_intel_test_finish_fw(t, buf,
955 buf_len, i - t->dcr_idx);
956 case ND_INTEL_FW_FINISH_QUERY:
957 return nd_intel_test_finish_query(t, buf,
958 buf_len, i - t->dcr_idx);
960 return nfit_test_cmd_smart(buf, buf_len,
961 &t->smart[i - t->dcr_idx]);
962 case ND_INTEL_SMART_THRESHOLD:
963 return nfit_test_cmd_smart_threshold(buf,
965 &t->smart_threshold[i -
967 case ND_INTEL_SMART_SET_THRESHOLD:
968 return nfit_test_cmd_smart_set_threshold(buf,
970 &t->smart_threshold[i -
972 &t->smart[i - t->dcr_idx],
973 &t->pdev.dev, t->dimm_dev[i]);
974 case ND_INTEL_SMART_INJECT:
975 return nfit_test_cmd_smart_inject(buf,
977 &t->smart_threshold[i -
979 &t->smart[i - t->dcr_idx],
980 &t->pdev.dev, t->dimm_dev[i]);
986 if (!test_bit(cmd, &cmd_mask)
987 || !test_bit(func, &nfit_mem->dsm_mask))
990 i = get_dimm(nfit_mem, func);
995 case ND_CMD_GET_CONFIG_SIZE:
996 rc = nfit_test_cmd_get_config_size(buf, buf_len);
998 case ND_CMD_GET_CONFIG_DATA:
999 rc = nfit_test_cmd_get_config_data(buf, buf_len,
1000 t->label[i - t->dcr_idx]);
1002 case ND_CMD_SET_CONFIG_DATA:
1003 rc = nfit_test_cmd_set_config_data(buf, buf_len,
1004 t->label[i - t->dcr_idx]);
1010 struct ars_state *ars_state = &t->ars_state;
1011 struct nd_cmd_pkg *call_pkg = buf;
1016 if (cmd == ND_CMD_CALL) {
1017 func = call_pkg->nd_command;
1019 buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
1020 buf = (void *) call_pkg->nd_payload;
1023 case NFIT_CMD_TRANSLATE_SPA:
1024 rc = nfit_test_cmd_translate_spa(
1025 acpi_desc->nvdimm_bus, buf, buf_len);
1027 case NFIT_CMD_ARS_INJECT_SET:
1028 rc = nfit_test_cmd_ars_error_inject(t, buf,
1031 case NFIT_CMD_ARS_INJECT_CLEAR:
1032 rc = nfit_test_cmd_ars_inject_clear(t, buf,
1035 case NFIT_CMD_ARS_INJECT_GET:
1036 rc = nfit_test_cmd_ars_inject_status(t, buf,
1044 if (!nd_desc || !test_bit(cmd, &nd_desc->cmd_mask))
1048 case ND_CMD_ARS_CAP:
1049 rc = nfit_test_cmd_ars_cap(buf, buf_len);
1051 case ND_CMD_ARS_START:
1052 rc = nfit_test_cmd_ars_start(t, ars_state, buf,
1055 case ND_CMD_ARS_STATUS:
1056 rc = nfit_test_cmd_ars_status(ars_state, buf, buf_len,
1059 case ND_CMD_CLEAR_ERROR:
1060 rc = nfit_test_cmd_clear_error(t, buf, buf_len, cmd_rc);
1070 static DEFINE_SPINLOCK(nfit_test_lock);
1071 static struct nfit_test *instances[NUM_NFITS];
1073 static void release_nfit_res(void *data)
1075 struct nfit_test_resource *nfit_res = data;
1077 spin_lock(&nfit_test_lock);
1078 list_del(&nfit_res->list);
1079 spin_unlock(&nfit_test_lock);
1081 vfree(nfit_res->buf);
1085 static void *__test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma,
1088 struct device *dev = &t->pdev.dev;
1089 struct nfit_test_resource *nfit_res = kzalloc(sizeof(*nfit_res),
1093 if (!buf || !nfit_res)
1095 rc = devm_add_action(dev, release_nfit_res, nfit_res);
1098 INIT_LIST_HEAD(&nfit_res->list);
1099 memset(buf, 0, size);
1100 nfit_res->dev = dev;
1101 nfit_res->buf = buf;
1102 nfit_res->res.start = *dma;
1103 nfit_res->res.end = *dma + size - 1;
1104 nfit_res->res.name = "NFIT";
1105 spin_lock_init(&nfit_res->lock);
1106 INIT_LIST_HEAD(&nfit_res->requests);
1107 spin_lock(&nfit_test_lock);
1108 list_add(&nfit_res->list, &t->resources);
1109 spin_unlock(&nfit_test_lock);
1111 return nfit_res->buf;
1119 static void *test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma)
1121 void *buf = vmalloc(size);
1123 *dma = (unsigned long) buf;
1124 return __test_alloc(t, size, dma, buf);
1127 static struct nfit_test_resource *nfit_test_lookup(resource_size_t addr)
1131 for (i = 0; i < ARRAY_SIZE(instances); i++) {
1132 struct nfit_test_resource *n, *nfit_res = NULL;
1133 struct nfit_test *t = instances[i];
1137 spin_lock(&nfit_test_lock);
1138 list_for_each_entry(n, &t->resources, list) {
1139 if (addr >= n->res.start && (addr < n->res.start
1140 + resource_size(&n->res))) {
1143 } else if (addr >= (unsigned long) n->buf
1144 && (addr < (unsigned long) n->buf
1145 + resource_size(&n->res))) {
1150 spin_unlock(&nfit_test_lock);
1158 static int ars_state_init(struct device *dev, struct ars_state *ars_state)
1160 /* for testing, only store up to n records that fit within 4k */
1161 ars_state->ars_status = devm_kzalloc(dev,
1162 sizeof(struct nd_cmd_ars_status) + SZ_4K, GFP_KERNEL);
1163 if (!ars_state->ars_status)
1165 spin_lock_init(&ars_state->lock);
1169 static void put_dimms(void *data)
1171 struct nfit_test *t = data;
1174 for (i = 0; i < t->num_dcr; i++)
1176 device_unregister(t->dimm_dev[i]);
1179 static struct class *nfit_test_dimm;
1181 static int dimm_name_to_id(struct device *dev)
1185 if (sscanf(dev_name(dev), "test_dimm%d", &dimm) != 1)
1190 static ssize_t handle_show(struct device *dev, struct device_attribute *attr,
1193 int dimm = dimm_name_to_id(dev);
1198 return sprintf(buf, "%#x\n", handle[dimm]);
1200 DEVICE_ATTR_RO(handle);
1202 static ssize_t fail_cmd_show(struct device *dev, struct device_attribute *attr,
1205 int dimm = dimm_name_to_id(dev);
1210 return sprintf(buf, "%#lx\n", dimm_fail_cmd_flags[dimm]);
1213 static ssize_t fail_cmd_store(struct device *dev, struct device_attribute *attr,
1214 const char *buf, size_t size)
1216 int dimm = dimm_name_to_id(dev);
1223 rc = kstrtol(buf, 0, &val);
1227 dimm_fail_cmd_flags[dimm] = val;
1230 static DEVICE_ATTR_RW(fail_cmd);
1232 static ssize_t fail_cmd_code_show(struct device *dev, struct device_attribute *attr,
1235 int dimm = dimm_name_to_id(dev);
1240 return sprintf(buf, "%d\n", dimm_fail_cmd_code[dimm]);
1243 static ssize_t fail_cmd_code_store(struct device *dev, struct device_attribute *attr,
1244 const char *buf, size_t size)
1246 int dimm = dimm_name_to_id(dev);
1253 rc = kstrtol(buf, 0, &val);
1257 dimm_fail_cmd_code[dimm] = val;
1260 static DEVICE_ATTR_RW(fail_cmd_code);
1262 static struct attribute *nfit_test_dimm_attributes[] = {
1263 &dev_attr_fail_cmd.attr,
1264 &dev_attr_fail_cmd_code.attr,
1265 &dev_attr_handle.attr,
1269 static struct attribute_group nfit_test_dimm_attribute_group = {
1270 .attrs = nfit_test_dimm_attributes,
1273 static const struct attribute_group *nfit_test_dimm_attribute_groups[] = {
1274 &nfit_test_dimm_attribute_group,
1278 static int nfit_test_dimm_init(struct nfit_test *t)
1282 if (devm_add_action_or_reset(&t->pdev.dev, put_dimms, t))
1284 for (i = 0; i < t->num_dcr; i++) {
1285 t->dimm_dev[i] = device_create_with_groups(nfit_test_dimm,
1286 &t->pdev.dev, 0, NULL,
1287 nfit_test_dimm_attribute_groups,
1288 "test_dimm%d", i + t->dcr_idx);
1289 if (!t->dimm_dev[i])
1295 static void smart_init(struct nfit_test *t)
1298 const struct nd_intel_smart_threshold smart_t_data = {
1299 .alarm_control = ND_INTEL_SMART_SPARE_TRIP
1300 | ND_INTEL_SMART_TEMP_TRIP,
1301 .media_temperature = 40 * 16,
1302 .ctrl_temperature = 30 * 16,
1305 const struct nd_intel_smart smart_data = {
1306 .flags = ND_INTEL_SMART_HEALTH_VALID
1307 | ND_INTEL_SMART_SPARES_VALID
1308 | ND_INTEL_SMART_ALARM_VALID
1309 | ND_INTEL_SMART_USED_VALID
1310 | ND_INTEL_SMART_SHUTDOWN_VALID
1311 | ND_INTEL_SMART_MTEMP_VALID,
1312 .health = ND_INTEL_SMART_NON_CRITICAL_HEALTH,
1313 .media_temperature = 23 * 16,
1314 .ctrl_temperature = 25 * 16,
1315 .pmic_temperature = 40 * 16,
1317 .alarm_flags = ND_INTEL_SMART_SPARE_TRIP
1318 | ND_INTEL_SMART_TEMP_TRIP,
1321 .shutdown_state = 0,
1323 .shutdown_count = 100,
1326 for (i = 0; i < t->num_dcr; i++) {
1327 memcpy(&t->smart[i], &smart_data, sizeof(smart_data));
1328 memcpy(&t->smart_threshold[i], &smart_t_data,
1329 sizeof(smart_t_data));
1333 static int nfit_test0_alloc(struct nfit_test *t)
1335 size_t nfit_size = sizeof(struct acpi_nfit_system_address) * NUM_SPA
1336 + sizeof(struct acpi_nfit_memory_map) * NUM_MEM
1337 + sizeof(struct acpi_nfit_control_region) * NUM_DCR
1338 + offsetof(struct acpi_nfit_control_region,
1339 window_size) * NUM_DCR
1340 + sizeof(struct acpi_nfit_data_region) * NUM_BDW
1341 + (sizeof(struct acpi_nfit_flush_address)
1342 + sizeof(u64) * NUM_HINTS) * NUM_DCR
1343 + sizeof(struct acpi_nfit_capabilities);
1346 t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
1349 t->nfit_size = nfit_size;
1351 t->spa_set[0] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[0]);
1355 t->spa_set[1] = test_alloc(t, SPA1_SIZE, &t->spa_set_dma[1]);
1359 t->spa_set[2] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[2]);
1363 for (i = 0; i < t->num_dcr; i++) {
1364 t->dimm[i] = test_alloc(t, DIMM_SIZE, &t->dimm_dma[i]);
1368 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]);
1371 sprintf(t->label[i], "label%d", i);
1373 t->flush[i] = test_alloc(t, max(PAGE_SIZE,
1374 sizeof(u64) * NUM_HINTS),
1380 for (i = 0; i < t->num_dcr; i++) {
1381 t->dcr[i] = test_alloc(t, LABEL_SIZE, &t->dcr_dma[i]);
1386 t->_fit = test_alloc(t, sizeof(union acpi_object **), &t->_fit_dma);
1390 if (nfit_test_dimm_init(t))
1393 return ars_state_init(&t->pdev.dev, &t->ars_state);
1396 static int nfit_test1_alloc(struct nfit_test *t)
1398 size_t nfit_size = sizeof(struct acpi_nfit_system_address) * 2
1399 + sizeof(struct acpi_nfit_memory_map) * 2
1400 + offsetof(struct acpi_nfit_control_region, window_size) * 2;
1403 t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
1406 t->nfit_size = nfit_size;
1408 t->spa_set[0] = test_alloc(t, SPA2_SIZE, &t->spa_set_dma[0]);
1412 for (i = 0; i < t->num_dcr; i++) {
1413 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]);
1416 sprintf(t->label[i], "label%d", i);
1419 t->spa_set[1] = test_alloc(t, SPA_VCD_SIZE, &t->spa_set_dma[1]);
1423 if (nfit_test_dimm_init(t))
1426 return ars_state_init(&t->pdev.dev, &t->ars_state);
1429 static void dcr_common_init(struct acpi_nfit_control_region *dcr)
1431 dcr->vendor_id = 0xabcd;
1433 dcr->revision_id = 1;
1434 dcr->valid_fields = 1;
1435 dcr->manufacturing_location = 0xa;
1436 dcr->manufacturing_date = cpu_to_be16(2016);
1439 static void nfit_test0_setup(struct nfit_test *t)
1441 const int flush_hint_size = sizeof(struct acpi_nfit_flush_address)
1442 + (sizeof(u64) * NUM_HINTS);
1443 struct acpi_nfit_desc *acpi_desc;
1444 struct acpi_nfit_memory_map *memdev;
1445 void *nfit_buf = t->nfit_buf;
1446 struct acpi_nfit_system_address *spa;
1447 struct acpi_nfit_control_region *dcr;
1448 struct acpi_nfit_data_region *bdw;
1449 struct acpi_nfit_flush_address *flush;
1450 struct acpi_nfit_capabilities *pcap;
1451 unsigned int offset = 0, i;
1454 * spa0 (interleave first half of dimm0 and dimm1, note storage
1455 * does not actually alias the related block-data-window
1459 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1460 spa->header.length = sizeof(*spa);
1461 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
1462 spa->range_index = 0+1;
1463 spa->address = t->spa_set_dma[0];
1464 spa->length = SPA0_SIZE;
1465 offset += spa->header.length;
1468 * spa1 (interleave last half of the 4 DIMMS, note storage
1469 * does not actually alias the related block-data-window
1472 spa = nfit_buf + offset;
1473 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1474 spa->header.length = sizeof(*spa);
1475 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
1476 spa->range_index = 1+1;
1477 spa->address = t->spa_set_dma[1];
1478 spa->length = SPA1_SIZE;
1479 offset += spa->header.length;
1481 /* spa2 (dcr0) dimm0 */
1482 spa = nfit_buf + offset;
1483 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1484 spa->header.length = sizeof(*spa);
1485 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1486 spa->range_index = 2+1;
1487 spa->address = t->dcr_dma[0];
1488 spa->length = DCR_SIZE;
1489 offset += spa->header.length;
1491 /* spa3 (dcr1) dimm1 */
1492 spa = nfit_buf + offset;
1493 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1494 spa->header.length = sizeof(*spa);
1495 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1496 spa->range_index = 3+1;
1497 spa->address = t->dcr_dma[1];
1498 spa->length = DCR_SIZE;
1499 offset += spa->header.length;
1501 /* spa4 (dcr2) dimm2 */
1502 spa = nfit_buf + offset;
1503 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1504 spa->header.length = sizeof(*spa);
1505 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1506 spa->range_index = 4+1;
1507 spa->address = t->dcr_dma[2];
1508 spa->length = DCR_SIZE;
1509 offset += spa->header.length;
1511 /* spa5 (dcr3) dimm3 */
1512 spa = nfit_buf + offset;
1513 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1514 spa->header.length = sizeof(*spa);
1515 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1516 spa->range_index = 5+1;
1517 spa->address = t->dcr_dma[3];
1518 spa->length = DCR_SIZE;
1519 offset += spa->header.length;
1521 /* spa6 (bdw for dcr0) dimm0 */
1522 spa = nfit_buf + offset;
1523 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1524 spa->header.length = sizeof(*spa);
1525 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1526 spa->range_index = 6+1;
1527 spa->address = t->dimm_dma[0];
1528 spa->length = DIMM_SIZE;
1529 offset += spa->header.length;
1531 /* spa7 (bdw for dcr1) dimm1 */
1532 spa = nfit_buf + offset;
1533 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1534 spa->header.length = sizeof(*spa);
1535 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1536 spa->range_index = 7+1;
1537 spa->address = t->dimm_dma[1];
1538 spa->length = DIMM_SIZE;
1539 offset += spa->header.length;
1541 /* spa8 (bdw for dcr2) dimm2 */
1542 spa = nfit_buf + offset;
1543 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1544 spa->header.length = sizeof(*spa);
1545 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1546 spa->range_index = 8+1;
1547 spa->address = t->dimm_dma[2];
1548 spa->length = DIMM_SIZE;
1549 offset += spa->header.length;
1551 /* spa9 (bdw for dcr3) dimm3 */
1552 spa = nfit_buf + offset;
1553 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1554 spa->header.length = sizeof(*spa);
1555 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1556 spa->range_index = 9+1;
1557 spa->address = t->dimm_dma[3];
1558 spa->length = DIMM_SIZE;
1559 offset += spa->header.length;
1561 /* mem-region0 (spa0, dimm0) */
1562 memdev = nfit_buf + offset;
1563 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1564 memdev->header.length = sizeof(*memdev);
1565 memdev->device_handle = handle[0];
1566 memdev->physical_id = 0;
1567 memdev->region_id = 0;
1568 memdev->range_index = 0+1;
1569 memdev->region_index = 4+1;
1570 memdev->region_size = SPA0_SIZE/2;
1571 memdev->region_offset = 1;
1572 memdev->address = 0;
1573 memdev->interleave_index = 0;
1574 memdev->interleave_ways = 2;
1575 offset += memdev->header.length;
1577 /* mem-region1 (spa0, dimm1) */
1578 memdev = nfit_buf + offset;
1579 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1580 memdev->header.length = sizeof(*memdev);
1581 memdev->device_handle = handle[1];
1582 memdev->physical_id = 1;
1583 memdev->region_id = 0;
1584 memdev->range_index = 0+1;
1585 memdev->region_index = 5+1;
1586 memdev->region_size = SPA0_SIZE/2;
1587 memdev->region_offset = (1 << 8);
1588 memdev->address = 0;
1589 memdev->interleave_index = 0;
1590 memdev->interleave_ways = 2;
1591 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
1592 offset += memdev->header.length;
1594 /* mem-region2 (spa1, dimm0) */
1595 memdev = nfit_buf + offset;
1596 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1597 memdev->header.length = sizeof(*memdev);
1598 memdev->device_handle = handle[0];
1599 memdev->physical_id = 0;
1600 memdev->region_id = 1;
1601 memdev->range_index = 1+1;
1602 memdev->region_index = 4+1;
1603 memdev->region_size = SPA1_SIZE/4;
1604 memdev->region_offset = (1 << 16);
1605 memdev->address = SPA0_SIZE/2;
1606 memdev->interleave_index = 0;
1607 memdev->interleave_ways = 4;
1608 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
1609 offset += memdev->header.length;
1611 /* mem-region3 (spa1, dimm1) */
1612 memdev = nfit_buf + offset;
1613 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1614 memdev->header.length = sizeof(*memdev);
1615 memdev->device_handle = handle[1];
1616 memdev->physical_id = 1;
1617 memdev->region_id = 1;
1618 memdev->range_index = 1+1;
1619 memdev->region_index = 5+1;
1620 memdev->region_size = SPA1_SIZE/4;
1621 memdev->region_offset = (1 << 24);
1622 memdev->address = SPA0_SIZE/2;
1623 memdev->interleave_index = 0;
1624 memdev->interleave_ways = 4;
1625 offset += memdev->header.length;
1627 /* mem-region4 (spa1, dimm2) */
1628 memdev = nfit_buf + offset;
1629 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1630 memdev->header.length = sizeof(*memdev);
1631 memdev->device_handle = handle[2];
1632 memdev->physical_id = 2;
1633 memdev->region_id = 0;
1634 memdev->range_index = 1+1;
1635 memdev->region_index = 6+1;
1636 memdev->region_size = SPA1_SIZE/4;
1637 memdev->region_offset = (1ULL << 32);
1638 memdev->address = SPA0_SIZE/2;
1639 memdev->interleave_index = 0;
1640 memdev->interleave_ways = 4;
1641 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
1642 offset += memdev->header.length;
1644 /* mem-region5 (spa1, dimm3) */
1645 memdev = nfit_buf + offset;
1646 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1647 memdev->header.length = sizeof(*memdev);
1648 memdev->device_handle = handle[3];
1649 memdev->physical_id = 3;
1650 memdev->region_id = 0;
1651 memdev->range_index = 1+1;
1652 memdev->region_index = 7+1;
1653 memdev->region_size = SPA1_SIZE/4;
1654 memdev->region_offset = (1ULL << 40);
1655 memdev->address = SPA0_SIZE/2;
1656 memdev->interleave_index = 0;
1657 memdev->interleave_ways = 4;
1658 offset += memdev->header.length;
1660 /* mem-region6 (spa/dcr0, dimm0) */
1661 memdev = nfit_buf + offset;
1662 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1663 memdev->header.length = sizeof(*memdev);
1664 memdev->device_handle = handle[0];
1665 memdev->physical_id = 0;
1666 memdev->region_id = 0;
1667 memdev->range_index = 2+1;
1668 memdev->region_index = 0+1;
1669 memdev->region_size = 0;
1670 memdev->region_offset = 0;
1671 memdev->address = 0;
1672 memdev->interleave_index = 0;
1673 memdev->interleave_ways = 1;
1674 offset += memdev->header.length;
1676 /* mem-region7 (spa/dcr1, dimm1) */
1677 memdev = nfit_buf + offset;
1678 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1679 memdev->header.length = sizeof(*memdev);
1680 memdev->device_handle = handle[1];
1681 memdev->physical_id = 1;
1682 memdev->region_id = 0;
1683 memdev->range_index = 3+1;
1684 memdev->region_index = 1+1;
1685 memdev->region_size = 0;
1686 memdev->region_offset = 0;
1687 memdev->address = 0;
1688 memdev->interleave_index = 0;
1689 memdev->interleave_ways = 1;
1690 offset += memdev->header.length;
1692 /* mem-region8 (spa/dcr2, dimm2) */
1693 memdev = nfit_buf + offset;
1694 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1695 memdev->header.length = sizeof(*memdev);
1696 memdev->device_handle = handle[2];
1697 memdev->physical_id = 2;
1698 memdev->region_id = 0;
1699 memdev->range_index = 4+1;
1700 memdev->region_index = 2+1;
1701 memdev->region_size = 0;
1702 memdev->region_offset = 0;
1703 memdev->address = 0;
1704 memdev->interleave_index = 0;
1705 memdev->interleave_ways = 1;
1706 offset += memdev->header.length;
1708 /* mem-region9 (spa/dcr3, dimm3) */
1709 memdev = nfit_buf + offset;
1710 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1711 memdev->header.length = sizeof(*memdev);
1712 memdev->device_handle = handle[3];
1713 memdev->physical_id = 3;
1714 memdev->region_id = 0;
1715 memdev->range_index = 5+1;
1716 memdev->region_index = 3+1;
1717 memdev->region_size = 0;
1718 memdev->region_offset = 0;
1719 memdev->address = 0;
1720 memdev->interleave_index = 0;
1721 memdev->interleave_ways = 1;
1722 offset += memdev->header.length;
1724 /* mem-region10 (spa/bdw0, dimm0) */
1725 memdev = nfit_buf + offset;
1726 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1727 memdev->header.length = sizeof(*memdev);
1728 memdev->device_handle = handle[0];
1729 memdev->physical_id = 0;
1730 memdev->region_id = 0;
1731 memdev->range_index = 6+1;
1732 memdev->region_index = 0+1;
1733 memdev->region_size = 0;
1734 memdev->region_offset = 0;
1735 memdev->address = 0;
1736 memdev->interleave_index = 0;
1737 memdev->interleave_ways = 1;
1738 offset += memdev->header.length;
1740 /* mem-region11 (spa/bdw1, dimm1) */
1741 memdev = nfit_buf + offset;
1742 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1743 memdev->header.length = sizeof(*memdev);
1744 memdev->device_handle = handle[1];
1745 memdev->physical_id = 1;
1746 memdev->region_id = 0;
1747 memdev->range_index = 7+1;
1748 memdev->region_index = 1+1;
1749 memdev->region_size = 0;
1750 memdev->region_offset = 0;
1751 memdev->address = 0;
1752 memdev->interleave_index = 0;
1753 memdev->interleave_ways = 1;
1754 offset += memdev->header.length;
1756 /* mem-region12 (spa/bdw2, dimm2) */
1757 memdev = nfit_buf + offset;
1758 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1759 memdev->header.length = sizeof(*memdev);
1760 memdev->device_handle = handle[2];
1761 memdev->physical_id = 2;
1762 memdev->region_id = 0;
1763 memdev->range_index = 8+1;
1764 memdev->region_index = 2+1;
1765 memdev->region_size = 0;
1766 memdev->region_offset = 0;
1767 memdev->address = 0;
1768 memdev->interleave_index = 0;
1769 memdev->interleave_ways = 1;
1770 offset += memdev->header.length;
1772 /* mem-region13 (spa/dcr3, dimm3) */
1773 memdev = nfit_buf + offset;
1774 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1775 memdev->header.length = sizeof(*memdev);
1776 memdev->device_handle = handle[3];
1777 memdev->physical_id = 3;
1778 memdev->region_id = 0;
1779 memdev->range_index = 9+1;
1780 memdev->region_index = 3+1;
1781 memdev->region_size = 0;
1782 memdev->region_offset = 0;
1783 memdev->address = 0;
1784 memdev->interleave_index = 0;
1785 memdev->interleave_ways = 1;
1786 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
1787 offset += memdev->header.length;
1789 /* dcr-descriptor0: blk */
1790 dcr = nfit_buf + offset;
1791 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1792 dcr->header.length = sizeof(*dcr);
1793 dcr->region_index = 0+1;
1794 dcr_common_init(dcr);
1795 dcr->serial_number = ~handle[0];
1796 dcr->code = NFIT_FIC_BLK;
1798 dcr->window_size = DCR_SIZE;
1799 dcr->command_offset = 0;
1800 dcr->command_size = 8;
1801 dcr->status_offset = 8;
1802 dcr->status_size = 4;
1803 offset += dcr->header.length;
1805 /* dcr-descriptor1: blk */
1806 dcr = nfit_buf + offset;
1807 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1808 dcr->header.length = sizeof(*dcr);
1809 dcr->region_index = 1+1;
1810 dcr_common_init(dcr);
1811 dcr->serial_number = ~handle[1];
1812 dcr->code = NFIT_FIC_BLK;
1814 dcr->window_size = DCR_SIZE;
1815 dcr->command_offset = 0;
1816 dcr->command_size = 8;
1817 dcr->status_offset = 8;
1818 dcr->status_size = 4;
1819 offset += dcr->header.length;
1821 /* dcr-descriptor2: blk */
1822 dcr = nfit_buf + offset;
1823 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1824 dcr->header.length = sizeof(*dcr);
1825 dcr->region_index = 2+1;
1826 dcr_common_init(dcr);
1827 dcr->serial_number = ~handle[2];
1828 dcr->code = NFIT_FIC_BLK;
1830 dcr->window_size = DCR_SIZE;
1831 dcr->command_offset = 0;
1832 dcr->command_size = 8;
1833 dcr->status_offset = 8;
1834 dcr->status_size = 4;
1835 offset += dcr->header.length;
1837 /* dcr-descriptor3: blk */
1838 dcr = nfit_buf + offset;
1839 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1840 dcr->header.length = sizeof(*dcr);
1841 dcr->region_index = 3+1;
1842 dcr_common_init(dcr);
1843 dcr->serial_number = ~handle[3];
1844 dcr->code = NFIT_FIC_BLK;
1846 dcr->window_size = DCR_SIZE;
1847 dcr->command_offset = 0;
1848 dcr->command_size = 8;
1849 dcr->status_offset = 8;
1850 dcr->status_size = 4;
1851 offset += dcr->header.length;
1853 /* dcr-descriptor0: pmem */
1854 dcr = nfit_buf + offset;
1855 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1856 dcr->header.length = offsetof(struct acpi_nfit_control_region,
1858 dcr->region_index = 4+1;
1859 dcr_common_init(dcr);
1860 dcr->serial_number = ~handle[0];
1861 dcr->code = NFIT_FIC_BYTEN;
1863 offset += dcr->header.length;
1865 /* dcr-descriptor1: pmem */
1866 dcr = nfit_buf + offset;
1867 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1868 dcr->header.length = offsetof(struct acpi_nfit_control_region,
1870 dcr->region_index = 5+1;
1871 dcr_common_init(dcr);
1872 dcr->serial_number = ~handle[1];
1873 dcr->code = NFIT_FIC_BYTEN;
1875 offset += dcr->header.length;
1877 /* dcr-descriptor2: pmem */
1878 dcr = nfit_buf + offset;
1879 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1880 dcr->header.length = offsetof(struct acpi_nfit_control_region,
1882 dcr->region_index = 6+1;
1883 dcr_common_init(dcr);
1884 dcr->serial_number = ~handle[2];
1885 dcr->code = NFIT_FIC_BYTEN;
1887 offset += dcr->header.length;
1889 /* dcr-descriptor3: pmem */
1890 dcr = nfit_buf + offset;
1891 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1892 dcr->header.length = offsetof(struct acpi_nfit_control_region,
1894 dcr->region_index = 7+1;
1895 dcr_common_init(dcr);
1896 dcr->serial_number = ~handle[3];
1897 dcr->code = NFIT_FIC_BYTEN;
1899 offset += dcr->header.length;
1901 /* bdw0 (spa/dcr0, dimm0) */
1902 bdw = nfit_buf + offset;
1903 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1904 bdw->header.length = sizeof(*bdw);
1905 bdw->region_index = 0+1;
1908 bdw->size = BDW_SIZE;
1909 bdw->capacity = DIMM_SIZE;
1910 bdw->start_address = 0;
1911 offset += bdw->header.length;
1913 /* bdw1 (spa/dcr1, dimm1) */
1914 bdw = nfit_buf + offset;
1915 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1916 bdw->header.length = sizeof(*bdw);
1917 bdw->region_index = 1+1;
1920 bdw->size = BDW_SIZE;
1921 bdw->capacity = DIMM_SIZE;
1922 bdw->start_address = 0;
1923 offset += bdw->header.length;
1925 /* bdw2 (spa/dcr2, dimm2) */
1926 bdw = nfit_buf + offset;
1927 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1928 bdw->header.length = sizeof(*bdw);
1929 bdw->region_index = 2+1;
1932 bdw->size = BDW_SIZE;
1933 bdw->capacity = DIMM_SIZE;
1934 bdw->start_address = 0;
1935 offset += bdw->header.length;
1937 /* bdw3 (spa/dcr3, dimm3) */
1938 bdw = nfit_buf + offset;
1939 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1940 bdw->header.length = sizeof(*bdw);
1941 bdw->region_index = 3+1;
1944 bdw->size = BDW_SIZE;
1945 bdw->capacity = DIMM_SIZE;
1946 bdw->start_address = 0;
1947 offset += bdw->header.length;
1949 /* flush0 (dimm0) */
1950 flush = nfit_buf + offset;
1951 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
1952 flush->header.length = flush_hint_size;
1953 flush->device_handle = handle[0];
1954 flush->hint_count = NUM_HINTS;
1955 for (i = 0; i < NUM_HINTS; i++)
1956 flush->hint_address[i] = t->flush_dma[0] + i * sizeof(u64);
1957 offset += flush->header.length;
1959 /* flush1 (dimm1) */
1960 flush = nfit_buf + offset;
1961 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
1962 flush->header.length = flush_hint_size;
1963 flush->device_handle = handle[1];
1964 flush->hint_count = NUM_HINTS;
1965 for (i = 0; i < NUM_HINTS; i++)
1966 flush->hint_address[i] = t->flush_dma[1] + i * sizeof(u64);
1967 offset += flush->header.length;
1969 /* flush2 (dimm2) */
1970 flush = nfit_buf + offset;
1971 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
1972 flush->header.length = flush_hint_size;
1973 flush->device_handle = handle[2];
1974 flush->hint_count = NUM_HINTS;
1975 for (i = 0; i < NUM_HINTS; i++)
1976 flush->hint_address[i] = t->flush_dma[2] + i * sizeof(u64);
1977 offset += flush->header.length;
1979 /* flush3 (dimm3) */
1980 flush = nfit_buf + offset;
1981 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
1982 flush->header.length = flush_hint_size;
1983 flush->device_handle = handle[3];
1984 flush->hint_count = NUM_HINTS;
1985 for (i = 0; i < NUM_HINTS; i++)
1986 flush->hint_address[i] = t->flush_dma[3] + i * sizeof(u64);
1987 offset += flush->header.length;
1989 /* platform capabilities */
1990 pcap = nfit_buf + offset;
1991 pcap->header.type = ACPI_NFIT_TYPE_CAPABILITIES;
1992 pcap->header.length = sizeof(*pcap);
1993 pcap->highest_capability = 1;
1994 pcap->capabilities = ACPI_NFIT_CAPABILITY_MEM_FLUSH;
1995 offset += pcap->header.length;
1997 if (t->setup_hotplug) {
1998 /* dcr-descriptor4: blk */
1999 dcr = nfit_buf + offset;
2000 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2001 dcr->header.length = sizeof(*dcr);
2002 dcr->region_index = 8+1;
2003 dcr_common_init(dcr);
2004 dcr->serial_number = ~handle[4];
2005 dcr->code = NFIT_FIC_BLK;
2007 dcr->window_size = DCR_SIZE;
2008 dcr->command_offset = 0;
2009 dcr->command_size = 8;
2010 dcr->status_offset = 8;
2011 dcr->status_size = 4;
2012 offset += dcr->header.length;
2014 /* dcr-descriptor4: pmem */
2015 dcr = nfit_buf + offset;
2016 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2017 dcr->header.length = offsetof(struct acpi_nfit_control_region,
2019 dcr->region_index = 9+1;
2020 dcr_common_init(dcr);
2021 dcr->serial_number = ~handle[4];
2022 dcr->code = NFIT_FIC_BYTEN;
2024 offset += dcr->header.length;
2026 /* bdw4 (spa/dcr4, dimm4) */
2027 bdw = nfit_buf + offset;
2028 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2029 bdw->header.length = sizeof(*bdw);
2030 bdw->region_index = 8+1;
2033 bdw->size = BDW_SIZE;
2034 bdw->capacity = DIMM_SIZE;
2035 bdw->start_address = 0;
2036 offset += bdw->header.length;
2038 /* spa10 (dcr4) dimm4 */
2039 spa = nfit_buf + offset;
2040 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2041 spa->header.length = sizeof(*spa);
2042 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
2043 spa->range_index = 10+1;
2044 spa->address = t->dcr_dma[4];
2045 spa->length = DCR_SIZE;
2046 offset += spa->header.length;
2049 * spa11 (single-dimm interleave for hotplug, note storage
2050 * does not actually alias the related block-data-window
2053 spa = nfit_buf + offset;
2054 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2055 spa->header.length = sizeof(*spa);
2056 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
2057 spa->range_index = 11+1;
2058 spa->address = t->spa_set_dma[2];
2059 spa->length = SPA0_SIZE;
2060 offset += spa->header.length;
2062 /* spa12 (bdw for dcr4) dimm4 */
2063 spa = nfit_buf + offset;
2064 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2065 spa->header.length = sizeof(*spa);
2066 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
2067 spa->range_index = 12+1;
2068 spa->address = t->dimm_dma[4];
2069 spa->length = DIMM_SIZE;
2070 offset += spa->header.length;
2072 /* mem-region14 (spa/dcr4, dimm4) */
2073 memdev = nfit_buf + offset;
2074 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2075 memdev->header.length = sizeof(*memdev);
2076 memdev->device_handle = handle[4];
2077 memdev->physical_id = 4;
2078 memdev->region_id = 0;
2079 memdev->range_index = 10+1;
2080 memdev->region_index = 8+1;
2081 memdev->region_size = 0;
2082 memdev->region_offset = 0;
2083 memdev->address = 0;
2084 memdev->interleave_index = 0;
2085 memdev->interleave_ways = 1;
2086 offset += memdev->header.length;
2088 /* mem-region15 (spa11, dimm4) */
2089 memdev = nfit_buf + offset;
2090 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2091 memdev->header.length = sizeof(*memdev);
2092 memdev->device_handle = handle[4];
2093 memdev->physical_id = 4;
2094 memdev->region_id = 0;
2095 memdev->range_index = 11+1;
2096 memdev->region_index = 9+1;
2097 memdev->region_size = SPA0_SIZE;
2098 memdev->region_offset = (1ULL << 48);
2099 memdev->address = 0;
2100 memdev->interleave_index = 0;
2101 memdev->interleave_ways = 1;
2102 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
2103 offset += memdev->header.length;
2105 /* mem-region16 (spa/bdw4, dimm4) */
2106 memdev = nfit_buf + offset;
2107 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2108 memdev->header.length = sizeof(*memdev);
2109 memdev->device_handle = handle[4];
2110 memdev->physical_id = 4;
2111 memdev->region_id = 0;
2112 memdev->range_index = 12+1;
2113 memdev->region_index = 8+1;
2114 memdev->region_size = 0;
2115 memdev->region_offset = 0;
2116 memdev->address = 0;
2117 memdev->interleave_index = 0;
2118 memdev->interleave_ways = 1;
2119 offset += memdev->header.length;
2121 /* flush3 (dimm4) */
2122 flush = nfit_buf + offset;
2123 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2124 flush->header.length = flush_hint_size;
2125 flush->device_handle = handle[4];
2126 flush->hint_count = NUM_HINTS;
2127 for (i = 0; i < NUM_HINTS; i++)
2128 flush->hint_address[i] = t->flush_dma[4]
2130 offset += flush->header.length;
2132 /* sanity check to make sure we've filled the buffer */
2133 WARN_ON(offset != t->nfit_size);
2136 t->nfit_filled = offset;
2138 post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0],
2141 acpi_desc = &t->acpi_desc;
2142 set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en);
2143 set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2144 set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2145 set_bit(ND_INTEL_SMART, &acpi_desc->dimm_cmd_force_en);
2146 set_bit(ND_INTEL_SMART_THRESHOLD, &acpi_desc->dimm_cmd_force_en);
2147 set_bit(ND_INTEL_SMART_SET_THRESHOLD, &acpi_desc->dimm_cmd_force_en);
2148 set_bit(ND_INTEL_SMART_INJECT, &acpi_desc->dimm_cmd_force_en);
2149 set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
2150 set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
2151 set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
2152 set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
2153 set_bit(ND_CMD_CALL, &acpi_desc->bus_cmd_force_en);
2154 set_bit(NFIT_CMD_TRANSLATE_SPA, &acpi_desc->bus_nfit_cmd_force_en);
2155 set_bit(NFIT_CMD_ARS_INJECT_SET, &acpi_desc->bus_nfit_cmd_force_en);
2156 set_bit(NFIT_CMD_ARS_INJECT_CLEAR, &acpi_desc->bus_nfit_cmd_force_en);
2157 set_bit(NFIT_CMD_ARS_INJECT_GET, &acpi_desc->bus_nfit_cmd_force_en);
2158 set_bit(ND_INTEL_FW_GET_INFO, &acpi_desc->dimm_cmd_force_en);
2159 set_bit(ND_INTEL_FW_START_UPDATE, &acpi_desc->dimm_cmd_force_en);
2160 set_bit(ND_INTEL_FW_SEND_DATA, &acpi_desc->dimm_cmd_force_en);
2161 set_bit(ND_INTEL_FW_FINISH_UPDATE, &acpi_desc->dimm_cmd_force_en);
2162 set_bit(ND_INTEL_FW_FINISH_QUERY, &acpi_desc->dimm_cmd_force_en);
2163 set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en);
2166 static void nfit_test1_setup(struct nfit_test *t)
2169 void *nfit_buf = t->nfit_buf;
2170 struct acpi_nfit_memory_map *memdev;
2171 struct acpi_nfit_control_region *dcr;
2172 struct acpi_nfit_system_address *spa;
2173 struct acpi_nfit_desc *acpi_desc;
2176 /* spa0 (flat range with no bdw aliasing) */
2177 spa = nfit_buf + offset;
2178 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2179 spa->header.length = sizeof(*spa);
2180 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
2181 spa->range_index = 0+1;
2182 spa->address = t->spa_set_dma[0];
2183 spa->length = SPA2_SIZE;
2184 offset += spa->header.length;
2186 /* virtual cd region */
2187 spa = nfit_buf + offset;
2188 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2189 spa->header.length = sizeof(*spa);
2190 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_VCD), 16);
2191 spa->range_index = 0;
2192 spa->address = t->spa_set_dma[1];
2193 spa->length = SPA_VCD_SIZE;
2194 offset += spa->header.length;
2196 /* mem-region0 (spa0, dimm0) */
2197 memdev = nfit_buf + offset;
2198 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2199 memdev->header.length = sizeof(*memdev);
2200 memdev->device_handle = handle[5];
2201 memdev->physical_id = 0;
2202 memdev->region_id = 0;
2203 memdev->range_index = 0+1;
2204 memdev->region_index = 0+1;
2205 memdev->region_size = SPA2_SIZE;
2206 memdev->region_offset = 0;
2207 memdev->address = 0;
2208 memdev->interleave_index = 0;
2209 memdev->interleave_ways = 1;
2210 memdev->flags = ACPI_NFIT_MEM_SAVE_FAILED | ACPI_NFIT_MEM_RESTORE_FAILED
2211 | ACPI_NFIT_MEM_FLUSH_FAILED | ACPI_NFIT_MEM_HEALTH_OBSERVED
2212 | ACPI_NFIT_MEM_NOT_ARMED;
2213 offset += memdev->header.length;
2215 /* dcr-descriptor0 */
2216 dcr = nfit_buf + offset;
2217 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2218 dcr->header.length = offsetof(struct acpi_nfit_control_region,
2220 dcr->region_index = 0+1;
2221 dcr_common_init(dcr);
2222 dcr->serial_number = ~handle[5];
2223 dcr->code = NFIT_FIC_BYTE;
2225 offset += dcr->header.length;
2227 memdev = nfit_buf + offset;
2228 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2229 memdev->header.length = sizeof(*memdev);
2230 memdev->device_handle = handle[6];
2231 memdev->physical_id = 0;
2232 memdev->region_id = 0;
2233 memdev->range_index = 0;
2234 memdev->region_index = 0+2;
2235 memdev->region_size = SPA2_SIZE;
2236 memdev->region_offset = 0;
2237 memdev->address = 0;
2238 memdev->interleave_index = 0;
2239 memdev->interleave_ways = 1;
2240 memdev->flags = ACPI_NFIT_MEM_MAP_FAILED;
2241 offset += memdev->header.length;
2243 /* dcr-descriptor1 */
2244 dcr = nfit_buf + offset;
2245 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2246 dcr->header.length = offsetof(struct acpi_nfit_control_region,
2248 dcr->region_index = 0+2;
2249 dcr_common_init(dcr);
2250 dcr->serial_number = ~handle[6];
2251 dcr->code = NFIT_FIC_BYTE;
2253 offset += dcr->header.length;
2255 /* sanity check to make sure we've filled the buffer */
2256 WARN_ON(offset != t->nfit_size);
2258 t->nfit_filled = offset;
2260 post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0],
2263 acpi_desc = &t->acpi_desc;
2264 set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
2265 set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
2266 set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
2267 set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
2268 set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en);
2269 set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en);
2270 set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2271 set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2274 static int nfit_test_blk_do_io(struct nd_blk_region *ndbr, resource_size_t dpa,
2275 void *iobuf, u64 len, int rw)
2277 struct nfit_blk *nfit_blk = ndbr->blk_provider_data;
2278 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW];
2279 struct nd_region *nd_region = &ndbr->nd_region;
2282 lane = nd_region_acquire_lane(nd_region);
2284 memcpy(mmio->addr.base + dpa, iobuf, len);
2286 memcpy(iobuf, mmio->addr.base + dpa, len);
2288 /* give us some some coverage of the arch_invalidate_pmem() API */
2289 arch_invalidate_pmem(mmio->addr.base + dpa, len);
2291 nd_region_release_lane(nd_region, lane);
2296 static unsigned long nfit_ctl_handle;
2298 union acpi_object *result;
2300 static union acpi_object *nfit_test_evaluate_dsm(acpi_handle handle,
2301 const guid_t *guid, u64 rev, u64 func, union acpi_object *argv4)
2303 if (handle != &nfit_ctl_handle)
2304 return ERR_PTR(-ENXIO);
2309 static int setup_result(void *buf, size_t size)
2311 result = kmalloc(sizeof(union acpi_object) + size, GFP_KERNEL);
2314 result->package.type = ACPI_TYPE_BUFFER,
2315 result->buffer.pointer = (void *) (result + 1);
2316 result->buffer.length = size;
2317 memcpy(result->buffer.pointer, buf, size);
2318 memset(buf, 0, size);
2322 static int nfit_ctl_test(struct device *dev)
2325 struct nvdimm *nvdimm;
2326 struct acpi_device *adev;
2327 struct nfit_mem *nfit_mem;
2328 struct nd_ars_record *record;
2329 struct acpi_nfit_desc *acpi_desc;
2330 const u64 test_val = 0x0123456789abcdefULL;
2331 unsigned long mask, cmd_size, offset;
2333 struct nd_cmd_get_config_size cfg_size;
2334 struct nd_cmd_clear_error clear_err;
2335 struct nd_cmd_ars_status ars_stat;
2336 struct nd_cmd_ars_cap ars_cap;
2337 char buf[sizeof(struct nd_cmd_ars_status)
2338 + sizeof(struct nd_ars_record)];
2341 adev = devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL);
2344 *adev = (struct acpi_device) {
2345 .handle = &nfit_ctl_handle,
2347 .init_name = "test-adev",
2351 acpi_desc = devm_kzalloc(dev, sizeof(*acpi_desc), GFP_KERNEL);
2354 *acpi_desc = (struct acpi_nfit_desc) {
2356 .cmd_mask = 1UL << ND_CMD_ARS_CAP
2357 | 1UL << ND_CMD_ARS_START
2358 | 1UL << ND_CMD_ARS_STATUS
2359 | 1UL << ND_CMD_CLEAR_ERROR
2360 | 1UL << ND_CMD_CALL,
2361 .module = THIS_MODULE,
2362 .provider_name = "ACPI.NFIT",
2363 .ndctl = acpi_nfit_ctl,
2364 .bus_dsm_mask = 1UL << NFIT_CMD_TRANSLATE_SPA
2365 | 1UL << NFIT_CMD_ARS_INJECT_SET
2366 | 1UL << NFIT_CMD_ARS_INJECT_CLEAR
2367 | 1UL << NFIT_CMD_ARS_INJECT_GET,
2372 nfit_mem = devm_kzalloc(dev, sizeof(*nfit_mem), GFP_KERNEL);
2376 mask = 1UL << ND_CMD_SMART | 1UL << ND_CMD_SMART_THRESHOLD
2377 | 1UL << ND_CMD_DIMM_FLAGS | 1UL << ND_CMD_GET_CONFIG_SIZE
2378 | 1UL << ND_CMD_GET_CONFIG_DATA | 1UL << ND_CMD_SET_CONFIG_DATA
2379 | 1UL << ND_CMD_VENDOR;
2380 *nfit_mem = (struct nfit_mem) {
2382 .family = NVDIMM_FAMILY_INTEL,
2386 nvdimm = devm_kzalloc(dev, sizeof(*nvdimm), GFP_KERNEL);
2389 *nvdimm = (struct nvdimm) {
2390 .provider_data = nfit_mem,
2393 .init_name = "test-dimm",
2398 /* basic checkout of a typical 'get config size' command */
2399 cmd_size = sizeof(cmds.cfg_size);
2400 cmds.cfg_size = (struct nd_cmd_get_config_size) {
2402 .config_size = SZ_128K,
2405 rc = setup_result(cmds.buf, cmd_size);
2408 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE,
2409 cmds.buf, cmd_size, &cmd_rc);
2411 if (rc < 0 || cmd_rc || cmds.cfg_size.status != 0
2412 || cmds.cfg_size.config_size != SZ_128K
2413 || cmds.cfg_size.max_xfer != SZ_4K) {
2414 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2415 __func__, __LINE__, rc, cmd_rc);
2420 /* test ars_status with zero output */
2421 cmd_size = offsetof(struct nd_cmd_ars_status, address);
2422 cmds.ars_stat = (struct nd_cmd_ars_status) {
2425 rc = setup_result(cmds.buf, cmd_size);
2428 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
2429 cmds.buf, cmd_size, &cmd_rc);
2431 if (rc < 0 || cmd_rc) {
2432 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2433 __func__, __LINE__, rc, cmd_rc);
2438 /* test ars_cap with benign extended status */
2439 cmd_size = sizeof(cmds.ars_cap);
2440 cmds.ars_cap = (struct nd_cmd_ars_cap) {
2441 .status = ND_ARS_PERSISTENT << 16,
2443 offset = offsetof(struct nd_cmd_ars_cap, status);
2444 rc = setup_result(cmds.buf + offset, cmd_size - offset);
2447 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_CAP,
2448 cmds.buf, cmd_size, &cmd_rc);
2450 if (rc < 0 || cmd_rc) {
2451 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2452 __func__, __LINE__, rc, cmd_rc);
2457 /* test ars_status with 'status' trimmed from 'out_length' */
2458 cmd_size = sizeof(cmds.ars_stat) + sizeof(struct nd_ars_record);
2459 cmds.ars_stat = (struct nd_cmd_ars_status) {
2460 .out_length = cmd_size - 4,
2462 record = &cmds.ars_stat.records[0];
2463 *record = (struct nd_ars_record) {
2466 rc = setup_result(cmds.buf, cmd_size);
2469 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
2470 cmds.buf, cmd_size, &cmd_rc);
2472 if (rc < 0 || cmd_rc || record->length != test_val) {
2473 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2474 __func__, __LINE__, rc, cmd_rc);
2479 /* test ars_status with 'Output (Size)' including 'status' */
2480 cmd_size = sizeof(cmds.ars_stat) + sizeof(struct nd_ars_record);
2481 cmds.ars_stat = (struct nd_cmd_ars_status) {
2482 .out_length = cmd_size,
2484 record = &cmds.ars_stat.records[0];
2485 *record = (struct nd_ars_record) {
2488 rc = setup_result(cmds.buf, cmd_size);
2491 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
2492 cmds.buf, cmd_size, &cmd_rc);
2494 if (rc < 0 || cmd_rc || record->length != test_val) {
2495 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2496 __func__, __LINE__, rc, cmd_rc);
2501 /* test extended status for get_config_size results in failure */
2502 cmd_size = sizeof(cmds.cfg_size);
2503 cmds.cfg_size = (struct nd_cmd_get_config_size) {
2506 rc = setup_result(cmds.buf, cmd_size);
2509 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE,
2510 cmds.buf, cmd_size, &cmd_rc);
2512 if (rc < 0 || cmd_rc >= 0) {
2513 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2514 __func__, __LINE__, rc, cmd_rc);
2518 /* test clear error */
2519 cmd_size = sizeof(cmds.clear_err);
2520 cmds.clear_err = (struct nd_cmd_clear_error) {
2524 rc = setup_result(cmds.buf, cmd_size);
2527 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_CLEAR_ERROR,
2528 cmds.buf, cmd_size, &cmd_rc);
2529 if (rc < 0 || cmd_rc) {
2530 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2531 __func__, __LINE__, rc, cmd_rc);
2538 static int nfit_test_probe(struct platform_device *pdev)
2540 struct nvdimm_bus_descriptor *nd_desc;
2541 struct acpi_nfit_desc *acpi_desc;
2542 struct device *dev = &pdev->dev;
2543 struct nfit_test *nfit_test;
2544 struct nfit_mem *nfit_mem;
2545 union acpi_object *obj;
2548 if (strcmp(dev_name(&pdev->dev), "nfit_test.0") == 0) {
2549 rc = nfit_ctl_test(&pdev->dev);
2554 nfit_test = to_nfit_test(&pdev->dev);
2557 if (nfit_test->num_dcr) {
2558 int num = nfit_test->num_dcr;
2560 nfit_test->dimm = devm_kcalloc(dev, num, sizeof(void *),
2562 nfit_test->dimm_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
2564 nfit_test->flush = devm_kcalloc(dev, num, sizeof(void *),
2566 nfit_test->flush_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
2568 nfit_test->label = devm_kcalloc(dev, num, sizeof(void *),
2570 nfit_test->label_dma = devm_kcalloc(dev, num,
2571 sizeof(dma_addr_t), GFP_KERNEL);
2572 nfit_test->dcr = devm_kcalloc(dev, num,
2573 sizeof(struct nfit_test_dcr *), GFP_KERNEL);
2574 nfit_test->dcr_dma = devm_kcalloc(dev, num,
2575 sizeof(dma_addr_t), GFP_KERNEL);
2576 nfit_test->smart = devm_kcalloc(dev, num,
2577 sizeof(struct nd_intel_smart), GFP_KERNEL);
2578 nfit_test->smart_threshold = devm_kcalloc(dev, num,
2579 sizeof(struct nd_intel_smart_threshold),
2581 nfit_test->fw = devm_kcalloc(dev, num,
2582 sizeof(struct nfit_test_fw), GFP_KERNEL);
2583 if (nfit_test->dimm && nfit_test->dimm_dma && nfit_test->label
2584 && nfit_test->label_dma && nfit_test->dcr
2585 && nfit_test->dcr_dma && nfit_test->flush
2586 && nfit_test->flush_dma
2593 if (nfit_test->num_pm) {
2594 int num = nfit_test->num_pm;
2596 nfit_test->spa_set = devm_kcalloc(dev, num, sizeof(void *),
2598 nfit_test->spa_set_dma = devm_kcalloc(dev, num,
2599 sizeof(dma_addr_t), GFP_KERNEL);
2600 if (nfit_test->spa_set && nfit_test->spa_set_dma)
2606 /* per-nfit specific alloc */
2607 if (nfit_test->alloc(nfit_test))
2610 nfit_test->setup(nfit_test);
2611 acpi_desc = &nfit_test->acpi_desc;
2612 acpi_nfit_desc_init(acpi_desc, &pdev->dev);
2613 acpi_desc->blk_do_io = nfit_test_blk_do_io;
2614 nd_desc = &acpi_desc->nd_desc;
2615 nd_desc->provider_name = NULL;
2616 nd_desc->module = THIS_MODULE;
2617 nd_desc->ndctl = nfit_test_ctl;
2619 rc = acpi_nfit_init(acpi_desc, nfit_test->nfit_buf,
2620 nfit_test->nfit_filled);
2624 rc = devm_add_action_or_reset(&pdev->dev, acpi_nfit_shutdown, acpi_desc);
2628 if (nfit_test->setup != nfit_test0_setup)
2631 nfit_test->setup_hotplug = 1;
2632 nfit_test->setup(nfit_test);
2634 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
2637 obj->type = ACPI_TYPE_BUFFER;
2638 obj->buffer.length = nfit_test->nfit_size;
2639 obj->buffer.pointer = nfit_test->nfit_buf;
2640 *(nfit_test->_fit) = obj;
2641 __acpi_nfit_notify(&pdev->dev, nfit_test, 0x80);
2643 /* associate dimm devices with nfit_mem data for notification testing */
2644 mutex_lock(&acpi_desc->init_mutex);
2645 list_for_each_entry(nfit_mem, &acpi_desc->dimms, list) {
2646 u32 nfit_handle = __to_nfit_memdev(nfit_mem)->device_handle;
2649 for (i = 0; i < NUM_DCR; i++)
2650 if (nfit_handle == handle[i])
2651 dev_set_drvdata(nfit_test->dimm_dev[i],
2654 mutex_unlock(&acpi_desc->init_mutex);
2659 static int nfit_test_remove(struct platform_device *pdev)
2664 static void nfit_test_release(struct device *dev)
2666 struct nfit_test *nfit_test = to_nfit_test(dev);
2671 static const struct platform_device_id nfit_test_id[] = {
2676 static struct platform_driver nfit_test_driver = {
2677 .probe = nfit_test_probe,
2678 .remove = nfit_test_remove,
2680 .name = KBUILD_MODNAME,
2682 .id_table = nfit_test_id,
2685 static char mcsafe_buf[PAGE_SIZE] __attribute__((__aligned__(PAGE_SIZE)));
2693 static void mcsafe_test_init(char *dst, char *src, size_t size)
2697 memset(dst, 0xff, size);
2698 for (i = 0; i < size; i++)
2702 static bool mcsafe_test_validate(unsigned char *dst, unsigned char *src,
2703 size_t size, unsigned long rem)
2707 for (i = 0; i < size - rem; i++)
2708 if (dst[i] != (unsigned char) i) {
2709 pr_info_once("%s:%d: offset: %zd got: %#x expect: %#x\n",
2710 __func__, __LINE__, i, dst[i],
2714 for (i = size - rem; i < size; i++)
2715 if (dst[i] != 0xffU) {
2716 pr_info_once("%s:%d: offset: %zd got: %#x expect: 0xff\n",
2717 __func__, __LINE__, i, dst[i]);
2723 void mcsafe_test(void)
2725 char *inject_desc[] = { "none", "source", "destination" };
2728 if (IS_ENABLED(CONFIG_MCSAFE_TEST)) {
2729 pr_info("%s: run...\n", __func__);
2731 pr_info("%s: disabled, skip.\n", __func__);
2735 for (inj = INJECT_NONE; inj <= INJECT_DST; inj++) {
2738 pr_info("%s: inject: %s\n", __func__, inject_desc[inj]);
2739 for (i = 0; i < 512; i++) {
2740 unsigned long expect, rem;
2746 mcsafe_inject_src(NULL);
2747 mcsafe_inject_dst(NULL);
2748 dst = &mcsafe_buf[2048];
2749 src = &mcsafe_buf[1024 - i];
2753 mcsafe_inject_src(&mcsafe_buf[1024]);
2754 mcsafe_inject_dst(NULL);
2755 dst = &mcsafe_buf[2048];
2756 src = &mcsafe_buf[1024 - i];
2760 mcsafe_inject_src(NULL);
2761 mcsafe_inject_dst(&mcsafe_buf[2048]);
2762 dst = &mcsafe_buf[2048 - i];
2763 src = &mcsafe_buf[1024];
2768 mcsafe_test_init(dst, src, 512);
2769 rem = __memcpy_mcsafe(dst, src, 512);
2770 valid = mcsafe_test_validate(dst, src, 512, expect);
2771 if (rem == expect && valid)
2773 pr_info("%s: copy(%#lx, %#lx, %d) off: %d rem: %ld %s expect: %ld\n",
2775 ((unsigned long) dst) & ~PAGE_MASK,
2776 ((unsigned long ) src) & ~PAGE_MASK,
2777 512, i, rem, valid ? "valid" : "bad",
2782 mcsafe_inject_src(NULL);
2783 mcsafe_inject_dst(NULL);
2786 static __init int nfit_test_init(void)
2796 nfit_test_setup(nfit_test_lookup, nfit_test_evaluate_dsm);
2798 nfit_wq = create_singlethread_workqueue("nfit");
2802 nfit_test_dimm = class_create(THIS_MODULE, "nfit_test_dimm");
2803 if (IS_ERR(nfit_test_dimm)) {
2804 rc = PTR_ERR(nfit_test_dimm);
2808 for (i = 0; i < NUM_NFITS; i++) {
2809 struct nfit_test *nfit_test;
2810 struct platform_device *pdev;
2812 nfit_test = kzalloc(sizeof(*nfit_test), GFP_KERNEL);
2817 INIT_LIST_HEAD(&nfit_test->resources);
2818 badrange_init(&nfit_test->badrange);
2821 nfit_test->num_pm = NUM_PM;
2822 nfit_test->dcr_idx = 0;
2823 nfit_test->num_dcr = NUM_DCR;
2824 nfit_test->alloc = nfit_test0_alloc;
2825 nfit_test->setup = nfit_test0_setup;
2828 nfit_test->num_pm = 2;
2829 nfit_test->dcr_idx = NUM_DCR;
2830 nfit_test->num_dcr = 2;
2831 nfit_test->alloc = nfit_test1_alloc;
2832 nfit_test->setup = nfit_test1_setup;
2838 pdev = &nfit_test->pdev;
2839 pdev->name = KBUILD_MODNAME;
2841 pdev->dev.release = nfit_test_release;
2842 rc = platform_device_register(pdev);
2844 put_device(&pdev->dev);
2847 get_device(&pdev->dev);
2849 rc = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2853 instances[i] = nfit_test;
2854 INIT_WORK(&nfit_test->work, uc_error_notify);
2857 rc = platform_driver_register(&nfit_test_driver);
2863 destroy_workqueue(nfit_wq);
2864 for (i = 0; i < NUM_NFITS; i++)
2866 platform_device_unregister(&instances[i]->pdev);
2867 nfit_test_teardown();
2868 for (i = 0; i < NUM_NFITS; i++)
2870 put_device(&instances[i]->pdev.dev);
2875 static __exit void nfit_test_exit(void)
2879 flush_workqueue(nfit_wq);
2880 destroy_workqueue(nfit_wq);
2881 for (i = 0; i < NUM_NFITS; i++)
2882 platform_device_unregister(&instances[i]->pdev);
2883 platform_driver_unregister(&nfit_test_driver);
2884 nfit_test_teardown();
2886 for (i = 0; i < NUM_NFITS; i++)
2887 put_device(&instances[i]->pdev.dev);
2888 class_destroy(nfit_test_dimm);
2891 module_init(nfit_test_init);
2892 module_exit(nfit_test_exit);
2893 MODULE_LICENSE("GPL v2");
2894 MODULE_AUTHOR("Intel Corporation");