tools/testing/nvdimm/test/nfit.c

   1 /*
   2  * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of version 2 of the GNU General Public License as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  */
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/workqueue.h>
  17 #include <linux/libnvdimm.h>
  18 #include <linux/genalloc.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/device.h>
  21 #include <linux/module.h>
  22 #include <linux/mutex.h>
  23 #include <linux/ndctl.h>
  24 #include <linux/sizes.h>
  25 #include <linux/list.h>
  26 #include <linux/slab.h>
  27 #include <nd-core.h>
  28 #include <intel.h>
  29 #include <nfit.h>
  30 #include <nd.h>
  31 #include "nfit_test.h"
  32 #include "../watermark.h"
  33
  34 #include <asm/mcsafe_test.h>
  35
  36 /*
  37  * Generate an NFIT table to describe the following topology:
  38  *
  39  * BUS0: Interleaved PMEM regions, and aliasing with BLK regions
  40  *
  41  *                     (a)                       (b)            DIMM   BLK-REGION
  42  *           +----------+--------------+----------+---------+
  43  * +------+  |  blk2.0  |     pm0.0    |  blk2.1  |  pm1.0  |    0      region2
  44  * | imc0 +--+- - - - - region0 - - - -+----------+         +
  45  * +--+---+  |  blk3.0  |     pm0.0    |  blk3.1  |  pm1.0  |    1      region3
  46  *    |      +----------+--------------v----------v         v
  47  * +--+---+                            |                    |
  48  * | cpu0 |                                    region1
  49  * +--+---+                            |                    |
  50  *    |      +-------------------------^----------^         ^
  51  * +--+---+  |                 blk4.0             |  pm1.0  |    2      region4
  52  * | imc1 +--+-------------------------+----------+         +
  53  * +------+  |                 blk5.0             |  pm1.0  |    3      region5
  54  *           +-------------------------+----------+-+-------+
  55  *
  56  * +--+---+
  57  * | cpu1 |
  58  * +--+---+                   (Hotplug DIMM)
  59  *    |      +----------------------------------------------+
  60  * +--+---+  |                 blk6.0/pm7.0                 |    4      region6/7
  61  * | imc0 +--+----------------------------------------------+
  62  * +------+
  63  *
  64  *
  65  * *) In this layout we have four dimms and two memory controllers in one
  66  *    socket.  Each unique interface (BLK or PMEM) to DPA space
  67  *    is identified by a region device with a dynamically assigned id.
  68  *
  69  * *) The first portion of dimm0 and dimm1 are interleaved as REGION0.
  70  *    A single PMEM namespace "pm0.0" is created using half of the
  71  *    REGION0 SPA-range.  REGION0 spans dimm0 and dimm1.  PMEM namespace
  72  *    allocate from from the bottom of a region.  The unallocated
  73  *    portion of REGION0 aliases with REGION2 and REGION3.  That
  74  *    unallacted capacity is reclaimed as BLK namespaces ("blk2.0" and
  75  *    "blk3.0") starting at the base of each DIMM to offset (a) in those
  76  *    DIMMs.  "pm0.0", "blk2.0" and "blk3.0" are free-form readable
  77  *    names that can be assigned to a namespace.
  78  *
  79  * *) In the last portion of dimm0 and dimm1 we have an interleaved
  80  *    SPA range, REGION1, that spans those two dimms as well as dimm2
  81  *    and dimm3.  Some of REGION1 allocated to a PMEM namespace named
  82  *    "pm1.0" the rest is reclaimed in 4 BLK namespaces (for each
  83  *    dimm in the interleave set), "blk2.1", "blk3.1", "blk4.0", and
  84  *    "blk5.0".
  85  *
  86  * *) The portion of dimm2 and dimm3 that do not participate in the
  87  *    REGION1 interleaved SPA range (i.e. the DPA address below offset
  88  *    (b) are also included in the "blk4.0" and "blk5.0" namespaces.
  89  *    Note, that BLK namespaces need not be contiguous in DPA-space, and
  90  *    can consume aliased capacity from multiple interleave sets.
  91  *
  92  * BUS1: Legacy NVDIMM (single contiguous range)
  93  *
  94  *  region2
  95  * +---------------------+
  96  * |---------------------|
  97  * ||       pm2.0       ||
  98  * |---------------------|
  99  * +---------------------+
 100  *
 101  * *) A NFIT-table may describe a simple system-physical-address range
 102  *    with no BLK aliasing.  This type of region may optionally
 103  *    reference an NVDIMM.
 104  */
 105 enum {
 106         NUM_PM  = 3,
 107         NUM_DCR = 5,
 108         NUM_HINTS = 8,
 109         NUM_BDW = NUM_DCR,
 110         NUM_SPA = NUM_PM + NUM_DCR + NUM_BDW,
 111         NUM_MEM = NUM_DCR + NUM_BDW + 2 /* spa0 iset */
 112                 + 4 /* spa1 iset */ + 1 /* spa11 iset */,
 113         DIMM_SIZE = SZ_32M,
 114         LABEL_SIZE = SZ_128K,
 115         SPA_VCD_SIZE = SZ_4M,
 116         SPA0_SIZE = DIMM_SIZE,
 117         SPA1_SIZE = DIMM_SIZE*2,
 118         SPA2_SIZE = DIMM_SIZE,
 119         BDW_SIZE = 64 << 8,
 120         DCR_SIZE = 12,
 121         NUM_NFITS = 2, /* permit testing multiple NFITs per system */
 122 };
 123
 124 struct nfit_test_dcr {
 125         __le64 bdw_addr;
 126         __le32 bdw_status;
 127         __u8 aperature[BDW_SIZE];
 128 };
 129
 130 #define NFIT_DIMM_HANDLE(node, socket, imc, chan, dimm) \
 131         (((node & 0xfff) << 16) | ((socket & 0xf) << 12) \
 132          | ((imc & 0xf) << 8) | ((chan & 0xf) << 4) | (dimm & 0xf))
 133
 134 static u32 handle[] = {
 135         [0] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 0),
 136         [1] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 1),
 137         [2] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 0),
 138         [3] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 1),
 139         [4] = NFIT_DIMM_HANDLE(0, 1, 0, 0, 0),
 140         [5] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 0),
 141         [6] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 1),
 142 };
 143
 144 static unsigned long dimm_fail_cmd_flags[ARRAY_SIZE(handle)];
 145 static int dimm_fail_cmd_code[ARRAY_SIZE(handle)];
 146 struct nfit_test_sec {
 147         u8 state;
 148         u8 ext_state;
 149         u8 old_state;
 150         u8 passphrase[32];
 151         u8 master_passphrase[32];
 152         u64 overwrite_end_time;
 153 } dimm_sec_info[NUM_DCR];
 154
 155 static const struct nd_intel_smart smart_def = {
 156         .flags = ND_INTEL_SMART_HEALTH_VALID
 157                 | ND_INTEL_SMART_SPARES_VALID
 158                 | ND_INTEL_SMART_ALARM_VALID
 159                 | ND_INTEL_SMART_USED_VALID
 160                 | ND_INTEL_SMART_SHUTDOWN_VALID
 161                 | ND_INTEL_SMART_SHUTDOWN_COUNT_VALID
 162                 | ND_INTEL_SMART_MTEMP_VALID
 163                 | ND_INTEL_SMART_CTEMP_VALID,
 164         .health = ND_INTEL_SMART_NON_CRITICAL_HEALTH,
 165         .media_temperature = 23 * 16,
 166         .ctrl_temperature = 25 * 16,
 167         .pmic_temperature = 40 * 16,
 168         .spares = 75,
 169         .alarm_flags = ND_INTEL_SMART_SPARE_TRIP
 170                 | ND_INTEL_SMART_TEMP_TRIP,
 171         .ait_status = 1,
 172         .life_used = 5,
 173         .shutdown_state = 0,
 174         .shutdown_count = 42,
 175         .vendor_size = 0,
 176 };
 177
 178 struct nfit_test_fw {
 179         enum intel_fw_update_state state;
 180         u32 context;
 181         u64 version;
 182         u32 size_received;
 183         u64 end_time;
 184 };
 185
 186 struct nfit_test {
 187         struct acpi_nfit_desc acpi_desc;
 188         struct platform_device pdev;
 189         struct list_head resources;
 190         void *nfit_buf;
 191         dma_addr_t nfit_dma;
 192         size_t nfit_size;
 193         size_t nfit_filled;
 194         int dcr_idx;
 195         int num_dcr;
 196         int num_pm;
 197         void **dimm;
 198         dma_addr_t *dimm_dma;
 199         void **flush;
 200         dma_addr_t *flush_dma;
 201         void **label;
 202         dma_addr_t *label_dma;
 203         void **spa_set;
 204         dma_addr_t *spa_set_dma;
 205         struct nfit_test_dcr **dcr;
 206         dma_addr_t *dcr_dma;
 207         int (*alloc)(struct nfit_test *t);
 208         void (*setup)(struct nfit_test *t);
 209         int setup_hotplug;
 210         union acpi_object **_fit;
 211         dma_addr_t _fit_dma;
 212         struct ars_state {
 213                 struct nd_cmd_ars_status *ars_status;
 214                 unsigned long deadline;
 215                 spinlock_t lock;
 216         } ars_state;
 217         struct device *dimm_dev[ARRAY_SIZE(handle)];
 218         struct nd_intel_smart *smart;
 219         struct nd_intel_smart_threshold *smart_threshold;
 220         struct badrange badrange;
 221         struct work_struct work;
 222         struct nfit_test_fw *fw;
 223 };
 224
 225 static struct workqueue_struct *nfit_wq;
 226
 227 static struct gen_pool *nfit_pool;
 228
 229 static const char zero_key[NVDIMM_PASSPHRASE_LEN];
 230
 231 static struct nfit_test *to_nfit_test(struct device *dev)
 232 {
 233         struct platform_device *pdev = to_platform_device(dev);
 234
 235         return container_of(pdev, struct nfit_test, pdev);
 236 }
 237
 238 static int nd_intel_test_get_fw_info(struct nfit_test *t,
 239                 struct nd_intel_fw_info *nd_cmd, unsigned int buf_len,
 240                 int idx)
 241 {
 242         struct device *dev = &t->pdev.dev;
 243         struct nfit_test_fw *fw = &t->fw[idx];
 244
 245         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p, buf_len: %u, idx: %d\n",
 246                         __func__, t, nd_cmd, buf_len, idx);
 247
 248         if (buf_len < sizeof(*nd_cmd))
 249                 return -EINVAL;
 250
 251         nd_cmd->status = 0;
 252         nd_cmd->storage_size = INTEL_FW_STORAGE_SIZE;
 253         nd_cmd->max_send_len = INTEL_FW_MAX_SEND_LEN;
 254         nd_cmd->query_interval = INTEL_FW_QUERY_INTERVAL;
 255         nd_cmd->max_query_time = INTEL_FW_QUERY_MAX_TIME;
 256         nd_cmd->update_cap = 0;
 257         nd_cmd->fis_version = INTEL_FW_FIS_VERSION;
 258         nd_cmd->run_version = 0;
 259         nd_cmd->updated_version = fw->version;
 260
 261         return 0;
 262 }
 263
 264 static int nd_intel_test_start_update(struct nfit_test *t,
 265                 struct nd_intel_fw_start *nd_cmd, unsigned int buf_len,
 266                 int idx)
 267 {
 268         struct device *dev = &t->pdev.dev;
 269         struct nfit_test_fw *fw = &t->fw[idx];
 270
 271         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
 272                         __func__, t, nd_cmd, buf_len, idx);
 273
 274         if (buf_len < sizeof(*nd_cmd))
 275                 return -EINVAL;
 276
 277         if (fw->state != FW_STATE_NEW) {
 278                 /* extended status, FW update in progress */
 279                 nd_cmd->status = 0x10007;
 280                 return 0;
 281         }
 282
 283         fw->state = FW_STATE_IN_PROGRESS;
 284         fw->context++;
 285         fw->size_received = 0;
 286         nd_cmd->status = 0;
 287         nd_cmd->context = fw->context;
 288
 289         dev_dbg(dev, "%s: context issued: %#x\n", __func__, nd_cmd->context);
 290
 291         return 0;
 292 }
 293
 294 static int nd_intel_test_send_data(struct nfit_test *t,
 295                 struct nd_intel_fw_send_data *nd_cmd, unsigned int buf_len,
 296                 int idx)
 297 {
 298         struct device *dev = &t->pdev.dev;
 299         struct nfit_test_fw *fw = &t->fw[idx];
 300         u32 *status = (u32 *)&nd_cmd->data[nd_cmd->length];
 301
 302         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
 303                         __func__, t, nd_cmd, buf_len, idx);
 304
 305         if (buf_len < sizeof(*nd_cmd))
 306                 return -EINVAL;
 307
 308
 309         dev_dbg(dev, "%s: cmd->status: %#x\n", __func__, *status);
 310         dev_dbg(dev, "%s: cmd->data[0]: %#x\n", __func__, nd_cmd->data[0]);
 311         dev_dbg(dev, "%s: cmd->data[%u]: %#x\n", __func__, nd_cmd->length-1,
 312                         nd_cmd->data[nd_cmd->length-1]);
 313
 314         if (fw->state != FW_STATE_IN_PROGRESS) {
 315                 dev_dbg(dev, "%s: not in IN_PROGRESS state\n", __func__);
 316                 *status = 0x5;
 317                 return 0;
 318         }
 319
 320         if (nd_cmd->context != fw->context) {
 321                 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
 322                                 __func__, nd_cmd->context, fw->context);
 323                 *status = 0x10007;
 324                 return 0;
 325         }
 326
 327         /*
 328          * check offset + len > size of fw storage
 329          * check length is > max send length
 330          */
 331         if (nd_cmd->offset + nd_cmd->length > INTEL_FW_STORAGE_SIZE ||
 332                         nd_cmd->length > INTEL_FW_MAX_SEND_LEN) {
 333                 *status = 0x3;
 334                 dev_dbg(dev, "%s: buffer boundary violation\n", __func__);
 335                 return 0;
 336         }
 337
 338         fw->size_received += nd_cmd->length;
 339         dev_dbg(dev, "%s: copying %u bytes, %u bytes so far\n",
 340                         __func__, nd_cmd->length, fw->size_received);
 341         *status = 0;
 342         return 0;
 343 }
 344
 345 static int nd_intel_test_finish_fw(struct nfit_test *t,
 346                 struct nd_intel_fw_finish_update *nd_cmd,
 347                 unsigned int buf_len, int idx)
 348 {
 349         struct device *dev = &t->pdev.dev;
 350         struct nfit_test_fw *fw = &t->fw[idx];
 351
 352         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
 353                         __func__, t, nd_cmd, buf_len, idx);
 354
 355         if (fw->state == FW_STATE_UPDATED) {
 356                 /* update already done, need cold boot */
 357                 nd_cmd->status = 0x20007;
 358                 return 0;
 359         }
 360
 361         dev_dbg(dev, "%s: context: %#x  ctrl_flags: %#x\n",
 362                         __func__, nd_cmd->context, nd_cmd->ctrl_flags);
 363
 364         switch (nd_cmd->ctrl_flags) {
 365         case 0: /* finish */
 366                 if (nd_cmd->context != fw->context) {
 367                         dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
 368                                         __func__, nd_cmd->context,
 369                                         fw->context);
 370                         nd_cmd->status = 0x10007;
 371                         return 0;
 372                 }
 373                 nd_cmd->status = 0;
 374                 fw->state = FW_STATE_VERIFY;
 375                 /* set 1 second of time for firmware "update" */
 376                 fw->end_time = jiffies + HZ;
 377                 break;
 378
 379         case 1: /* abort */
 380                 fw->size_received = 0;
 381                 /* successfully aborted status */
 382                 nd_cmd->status = 0x40007;
 383                 fw->state = FW_STATE_NEW;
 384                 dev_dbg(dev, "%s: abort successful\n", __func__);
 385                 break;
 386
 387         default: /* bad control flag */
 388                 dev_warn(dev, "%s: unknown control flag: %#x\n",
 389                                 __func__, nd_cmd->ctrl_flags);
 390                 return -EINVAL;
 391         }
 392
 393         return 0;
 394 }
 395
 396 static int nd_intel_test_finish_query(struct nfit_test *t,
 397                 struct nd_intel_fw_finish_query *nd_cmd,
 398                 unsigned int buf_len, int idx)
 399 {
 400         struct device *dev = &t->pdev.dev;
 401         struct nfit_test_fw *fw = &t->fw[idx];
 402
 403         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
 404                         __func__, t, nd_cmd, buf_len, idx);
 405
 406         if (buf_len < sizeof(*nd_cmd))
 407                 return -EINVAL;
 408
 409         if (nd_cmd->context != fw->context) {
 410                 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
 411                                 __func__, nd_cmd->context, fw->context);
 412                 nd_cmd->status = 0x10007;
 413                 return 0;
 414         }
 415
 416         dev_dbg(dev, "%s context: %#x\n", __func__, nd_cmd->context);
 417
 418         switch (fw->state) {
 419         case FW_STATE_NEW:
 420                 nd_cmd->updated_fw_rev = 0;
 421                 nd_cmd->status = 0;
 422                 dev_dbg(dev, "%s: new state\n", __func__);
 423                 break;
 424
 425         case FW_STATE_IN_PROGRESS:
 426                 /* sequencing error */
 427                 nd_cmd->status = 0x40007;
 428                 nd_cmd->updated_fw_rev = 0;
 429                 dev_dbg(dev, "%s: sequence error\n", __func__);
 430                 break;
 431
 432         case FW_STATE_VERIFY:
 433                 if (time_is_after_jiffies64(fw->end_time)) {
 434                         nd_cmd->updated_fw_rev = 0;
 435                         nd_cmd->status = 0x20007;
 436                         dev_dbg(dev, "%s: still verifying\n", __func__);
 437                         break;
 438                 }
 439
 440                 dev_dbg(dev, "%s: transition out verify\n", __func__);
 441                 fw->state = FW_STATE_UPDATED;
 442                 /* we are going to fall through if it's "done" */
 443         case FW_STATE_UPDATED:
 444                 nd_cmd->status = 0;
 445                 /* bogus test version */
 446                 fw->version = nd_cmd->updated_fw_rev =
 447                         INTEL_FW_FAKE_VERSION;
 448                 dev_dbg(dev, "%s: updated\n", __func__);
 449                 break;
 450
 451         default: /* we should never get here */
 452                 return -EINVAL;
 453         }
 454
 455         return 0;
 456 }
 457
 458 static int nfit_test_cmd_get_config_size(struct nd_cmd_get_config_size *nd_cmd,
 459                 unsigned int buf_len)
 460 {
 461         if (buf_len < sizeof(*nd_cmd))
 462                 return -EINVAL;
 463
 464         nd_cmd->status = 0;
 465         nd_cmd->config_size = LABEL_SIZE;
 466         nd_cmd->max_xfer = SZ_4K;
 467
 468         return 0;
 469 }
 470
 471 static int nfit_test_cmd_get_config_data(struct nd_cmd_get_config_data_hdr
 472                 *nd_cmd, unsigned int buf_len, void *label)
 473 {
 474         unsigned int len, offset = nd_cmd->in_offset;
 475         int rc;
 476
 477         if (buf_len < sizeof(*nd_cmd))
 478                 return -EINVAL;
 479         if (offset >= LABEL_SIZE)
 480                 return -EINVAL;
 481         if (nd_cmd->in_length + sizeof(*nd_cmd) > buf_len)
 482                 return -EINVAL;
 483
 484         nd_cmd->status = 0;
 485         len = min(nd_cmd->in_length, LABEL_SIZE - offset);
 486         memcpy(nd_cmd->out_buf, label + offset, len);
 487         rc = buf_len - sizeof(*nd_cmd) - len;
 488
 489         return rc;
 490 }
 491
 492 static int nfit_test_cmd_set_config_data(struct nd_cmd_set_config_hdr *nd_cmd,
 493                 unsigned int buf_len, void *label)
 494 {
 495         unsigned int len, offset = nd_cmd->in_offset;
 496         u32 *status;
 497         int rc;
 498
 499         if (buf_len < sizeof(*nd_cmd))
 500                 return -EINVAL;
 501         if (offset >= LABEL_SIZE)
 502                 return -EINVAL;
 503         if (nd_cmd->in_length + sizeof(*nd_cmd) + 4 > buf_len)
 504                 return -EINVAL;
 505
 506         status = (void *)nd_cmd + nd_cmd->in_length + sizeof(*nd_cmd);
 507         *status = 0;
 508         len = min(nd_cmd->in_length, LABEL_SIZE - offset);
 509         memcpy(label + offset, nd_cmd->in_buf, len);
 510         rc = buf_len - sizeof(*nd_cmd) - (len + 4);
 511
 512         return rc;
 513 }
 514
 515 #define NFIT_TEST_CLEAR_ERR_UNIT 256
 516
 517 static int nfit_test_cmd_ars_cap(struct nd_cmd_ars_cap *nd_cmd,
 518                 unsigned int buf_len)
 519 {
 520         int ars_recs;
 521
 522         if (buf_len < sizeof(*nd_cmd))
 523                 return -EINVAL;
 524
 525         /* for testing, only store up to n records that fit within 4k */
 526         ars_recs = SZ_4K / sizeof(struct nd_ars_record);
 527
 528         nd_cmd->max_ars_out = sizeof(struct nd_cmd_ars_status)
 529                 + ars_recs * sizeof(struct nd_ars_record);
 530         nd_cmd->status = (ND_ARS_PERSISTENT | ND_ARS_VOLATILE) << 16;
 531         nd_cmd->clear_err_unit = NFIT_TEST_CLEAR_ERR_UNIT;
 532
 533         return 0;
 534 }
 535
 536 static void post_ars_status(struct ars_state *ars_state,
 537                 struct badrange *badrange, u64 addr, u64 len)
 538 {
 539         struct nd_cmd_ars_status *ars_status;
 540         struct nd_ars_record *ars_record;
 541         struct badrange_entry *be;
 542         u64 end = addr + len - 1;
 543         int i = 0;
 544
 545         ars_state->deadline = jiffies + 1*HZ;
 546         ars_status = ars_state->ars_status;
 547         ars_status->status = 0;
 548         ars_status->address = addr;
 549         ars_status->length = len;
 550         ars_status->type = ND_ARS_PERSISTENT;
 551
 552         spin_lock(&badrange->lock);
 553         list_for_each_entry(be, &badrange->list, list) {
 554                 u64 be_end = be->start + be->length - 1;
 555                 u64 rstart, rend;
 556
 557                 /* skip entries outside the range */
 558                 if (be_end < addr || be->start > end)
 559                         continue;
 560
 561                 rstart = (be->start < addr) ? addr : be->start;
 562                 rend = (be_end < end) ? be_end : end;
 563                 ars_record = &ars_status->records[i];
 564                 ars_record->handle = 0;
 565                 ars_record->err_address = rstart;
 566                 ars_record->length = rend - rstart + 1;
 567                 i++;
 568         }
 569         spin_unlock(&badrange->lock);
 570         ars_status->num_records = i;
 571         ars_status->out_length = sizeof(struct nd_cmd_ars_status)
 572                 + i * sizeof(struct nd_ars_record);
 573 }
 574
 575 static int nfit_test_cmd_ars_start(struct nfit_test *t,
 576                 struct ars_state *ars_state,
 577                 struct nd_cmd_ars_start *ars_start, unsigned int buf_len,
 578                 int *cmd_rc)
 579 {
 580         if (buf_len < sizeof(*ars_start))
 581                 return -EINVAL;
 582
 583         spin_lock(&ars_state->lock);
 584         if (time_before(jiffies, ars_state->deadline)) {
 585                 ars_start->status = NFIT_ARS_START_BUSY;
 586                 *cmd_rc = -EBUSY;
 587         } else {
 588                 ars_start->status = 0;
 589                 ars_start->scrub_time = 1;
 590                 post_ars_status(ars_state, &t->badrange, ars_start->address,
 591                                 ars_start->length);
 592                 *cmd_rc = 0;
 593         }
 594         spin_unlock(&ars_state->lock);
 595
 596         return 0;
 597 }
 598
 599 static int nfit_test_cmd_ars_status(struct ars_state *ars_state,
 600                 struct nd_cmd_ars_status *ars_status, unsigned int buf_len,
 601                 int *cmd_rc)
 602 {
 603         if (buf_len < ars_state->ars_status->out_length)
 604                 return -EINVAL;
 605
 606         spin_lock(&ars_state->lock);
 607         if (time_before(jiffies, ars_state->deadline)) {
 608                 memset(ars_status, 0, buf_len);
 609                 ars_status->status = NFIT_ARS_STATUS_BUSY;
 610                 ars_status->out_length = sizeof(*ars_status);
 611                 *cmd_rc = -EBUSY;
 612         } else {
 613                 memcpy(ars_status, ars_state->ars_status,
 614                                 ars_state->ars_status->out_length);
 615                 *cmd_rc = 0;
 616         }
 617         spin_unlock(&ars_state->lock);
 618         return 0;
 619 }
 620
 621 static int nfit_test_cmd_clear_error(struct nfit_test *t,
 622                 struct nd_cmd_clear_error *clear_err,
 623                 unsigned int buf_len, int *cmd_rc)
 624 {
 625         const u64 mask = NFIT_TEST_CLEAR_ERR_UNIT - 1;
 626         if (buf_len < sizeof(*clear_err))
 627                 return -EINVAL;
 628
 629         if ((clear_err->address & mask) || (clear_err->length & mask))
 630                 return -EINVAL;
 631
 632         badrange_forget(&t->badrange, clear_err->address, clear_err->length);
 633         clear_err->status = 0;
 634         clear_err->cleared = clear_err->length;
 635         *cmd_rc = 0;
 636         return 0;
 637 }
 638
 639 struct region_search_spa {
 640         u64 addr;
 641         struct nd_region *region;
 642 };
 643
 644 static int is_region_device(struct device *dev)
 645 {
 646         return !strncmp(dev->kobj.name, "region", 6);
 647 }
 648
 649 static int nfit_test_search_region_spa(struct device *dev, void *data)
 650 {
 651         struct region_search_spa *ctx = data;
 652         struct nd_region *nd_region;
 653         resource_size_t ndr_end;
 654
 655         if (!is_region_device(dev))
 656                 return 0;
 657
 658         nd_region = to_nd_region(dev);
 659         ndr_end = nd_region->ndr_start + nd_region->ndr_size;
 660
 661         if (ctx->addr >= nd_region->ndr_start && ctx->addr < ndr_end) {
 662                 ctx->region = nd_region;
 663                 return 1;
 664         }
 665
 666         return 0;
 667 }
 668
 669 static int nfit_test_search_spa(struct nvdimm_bus *bus,
 670                 struct nd_cmd_translate_spa *spa)
 671 {
 672         int ret;
 673         struct nd_region *nd_region = NULL;
 674         struct nvdimm *nvdimm = NULL;
 675         struct nd_mapping *nd_mapping = NULL;
 676         struct region_search_spa ctx = {
 677                 .addr = spa->spa,
 678                 .region = NULL,
 679         };
 680         u64 dpa;
 681
 682         ret = device_for_each_child(&bus->dev, &ctx,
 683                                 nfit_test_search_region_spa);
 684
 685         if (!ret)
 686                 return -ENODEV;
 687
 688         nd_region = ctx.region;
 689
 690         dpa = ctx.addr - nd_region->ndr_start;
 691
 692         /*
 693          * last dimm is selected for test
 694          */
 695         nd_mapping = &nd_region->mapping[nd_region->ndr_mappings - 1];
 696         nvdimm = nd_mapping->nvdimm;
 697
 698         spa->devices[0].nfit_device_handle = handle[nvdimm->id];
 699         spa->num_nvdimms = 1;
 700         spa->devices[0].dpa = dpa;
 701
 702         return 0;
 703 }
 704
 705 static int nfit_test_cmd_translate_spa(struct nvdimm_bus *bus,
 706                 struct nd_cmd_translate_spa *spa, unsigned int buf_len)
 707 {
 708         if (buf_len < spa->translate_length)
 709                 return -EINVAL;
 710
 711         if (nfit_test_search_spa(bus, spa) < 0 || !spa->num_nvdimms)
 712                 spa->status = 2;
 713
 714         return 0;
 715 }
 716
 717 static int nfit_test_cmd_smart(struct nd_intel_smart *smart, unsigned int buf_len,
 718                 struct nd_intel_smart *smart_data)
 719 {
 720         if (buf_len < sizeof(*smart))
 721                 return -EINVAL;
 722         memcpy(smart, smart_data, sizeof(*smart));
 723         return 0;
 724 }
 725
 726 static int nfit_test_cmd_smart_threshold(
 727                 struct nd_intel_smart_threshold *out,
 728                 unsigned int buf_len,
 729                 struct nd_intel_smart_threshold *smart_t)
 730 {
 731         if (buf_len < sizeof(*smart_t))
 732                 return -EINVAL;
 733         memcpy(out, smart_t, sizeof(*smart_t));
 734         return 0;
 735 }
 736
 737 static void smart_notify(struct device *bus_dev,
 738                 struct device *dimm_dev, struct nd_intel_smart *smart,
 739                 struct nd_intel_smart_threshold *thresh)
 740 {
 741         dev_dbg(dimm_dev, "%s: alarm: %#x spares: %d (%d) mtemp: %d (%d) ctemp: %d (%d)\n",
 742                         __func__, thresh->alarm_control, thresh->spares,
 743                         smart->spares, thresh->media_temperature,
 744                         smart->media_temperature, thresh->ctrl_temperature,
 745                         smart->ctrl_temperature);
 746         if (((thresh->alarm_control & ND_INTEL_SMART_SPARE_TRIP)
 747                                 && smart->spares
 748                                 <= thresh->spares)
 749                         || ((thresh->alarm_control & ND_INTEL_SMART_TEMP_TRIP)
 750                                 && smart->media_temperature
 751                                 >= thresh->media_temperature)
 752                         || ((thresh->alarm_control & ND_INTEL_SMART_CTEMP_TRIP)
 753                                 && smart->ctrl_temperature
 754                                 >= thresh->ctrl_temperature)
 755                         || (smart->health != ND_INTEL_SMART_NON_CRITICAL_HEALTH)
 756                         || (smart->shutdown_state != 0)) {
 757                 device_lock(bus_dev);
 758                 __acpi_nvdimm_notify(dimm_dev, 0x81);
 759                 device_unlock(bus_dev);
 760         }
 761 }
 762
 763 static int nfit_test_cmd_smart_set_threshold(
 764                 struct nd_intel_smart_set_threshold *in,
 765                 unsigned int buf_len,
 766                 struct nd_intel_smart_threshold *thresh,
 767                 struct nd_intel_smart *smart,
 768                 struct device *bus_dev, struct device *dimm_dev)
 769 {
 770         unsigned int size;
 771
 772         size = sizeof(*in) - 4;
 773         if (buf_len < size)
 774                 return -EINVAL;
 775         memcpy(thresh->data, in, size);
 776         in->status = 0;
 777         smart_notify(bus_dev, dimm_dev, smart, thresh);
 778
 779         return 0;
 780 }
 781
 782 static int nfit_test_cmd_smart_inject(
 783                 struct nd_intel_smart_inject *inj,
 784                 unsigned int buf_len,
 785                 struct nd_intel_smart_threshold *thresh,
 786                 struct nd_intel_smart *smart,
 787                 struct device *bus_dev, struct device *dimm_dev)
 788 {
 789         if (buf_len != sizeof(*inj))
 790                 return -EINVAL;
 791
 792         if (inj->flags & ND_INTEL_SMART_INJECT_MTEMP) {
 793                 if (inj->mtemp_enable)
 794                         smart->media_temperature = inj->media_temperature;
 795                 else
 796                         smart->media_temperature = smart_def.media_temperature;
 797         }
 798         if (inj->flags & ND_INTEL_SMART_INJECT_SPARE) {
 799                 if (inj->spare_enable)
 800                         smart->spares = inj->spares;
 801                 else
 802                         smart->spares = smart_def.spares;
 803         }
 804         if (inj->flags & ND_INTEL_SMART_INJECT_FATAL) {
 805                 if (inj->fatal_enable)
 806                         smart->health = ND_INTEL_SMART_FATAL_HEALTH;
 807                 else
 808                         smart->health = ND_INTEL_SMART_NON_CRITICAL_HEALTH;
 809         }
 810         if (inj->flags & ND_INTEL_SMART_INJECT_SHUTDOWN) {
 811                 if (inj->unsafe_shutdown_enable) {
 812                         smart->shutdown_state = 1;
 813                         smart->shutdown_count++;
 814                 } else
 815                         smart->shutdown_state = 0;
 816         }
 817         inj->status = 0;
 818         smart_notify(bus_dev, dimm_dev, smart, thresh);
 819
 820         return 0;
 821 }
 822
 823 static void uc_error_notify(struct work_struct *work)
 824 {
 825         struct nfit_test *t = container_of(work, typeof(*t), work);
 826
 827         __acpi_nfit_notify(&t->pdev.dev, t, NFIT_NOTIFY_UC_MEMORY_ERROR);
 828 }
 829
 830 static int nfit_test_cmd_ars_error_inject(struct nfit_test *t,
 831                 struct nd_cmd_ars_err_inj *err_inj, unsigned int buf_len)
 832 {
 833         int rc;
 834
 835         if (buf_len != sizeof(*err_inj)) {
 836                 rc = -EINVAL;
 837                 goto err;
 838         }
 839
 840         if (err_inj->err_inj_spa_range_length <= 0) {
 841                 rc = -EINVAL;
 842                 goto err;
 843         }
 844
 845         rc =  badrange_add(&t->badrange, err_inj->err_inj_spa_range_base,
 846                         err_inj->err_inj_spa_range_length);
 847         if (rc < 0)
 848                 goto err;
 849
 850         if (err_inj->err_inj_options & (1 << ND_ARS_ERR_INJ_OPT_NOTIFY))
 851                 queue_work(nfit_wq, &t->work);
 852
 853         err_inj->status = 0;
 854         return 0;
 855
 856 err:
 857         err_inj->status = NFIT_ARS_INJECT_INVALID;
 858         return rc;
 859 }
 860
 861 static int nfit_test_cmd_ars_inject_clear(struct nfit_test *t,
 862                 struct nd_cmd_ars_err_inj_clr *err_clr, unsigned int buf_len)
 863 {
 864         int rc;
 865
 866         if (buf_len != sizeof(*err_clr)) {
 867                 rc = -EINVAL;
 868                 goto err;
 869         }
 870
 871         if (err_clr->err_inj_clr_spa_range_length <= 0) {
 872                 rc = -EINVAL;
 873                 goto err;
 874         }
 875
 876         badrange_forget(&t->badrange, err_clr->err_inj_clr_spa_range_base,
 877                         err_clr->err_inj_clr_spa_range_length);
 878
 879         err_clr->status = 0;
 880         return 0;
 881
 882 err:
 883         err_clr->status = NFIT_ARS_INJECT_INVALID;
 884         return rc;
 885 }
 886
 887 static int nfit_test_cmd_ars_inject_status(struct nfit_test *t,
 888                 struct nd_cmd_ars_err_inj_stat *err_stat,
 889                 unsigned int buf_len)
 890 {
 891         struct badrange_entry *be;
 892         int max = SZ_4K / sizeof(struct nd_error_stat_query_record);
 893         int i = 0;
 894
 895         err_stat->status = 0;
 896         spin_lock(&t->badrange.lock);
 897         list_for_each_entry(be, &t->badrange.list, list) {
 898                 err_stat->record[i].err_inj_stat_spa_range_base = be->start;
 899                 err_stat->record[i].err_inj_stat_spa_range_length = be->length;
 900                 i++;
 901                 if (i > max)
 902                         break;
 903         }
 904         spin_unlock(&t->badrange.lock);
 905         err_stat->inj_err_rec_count = i;
 906
 907         return 0;
 908 }
 909
 910 static int nd_intel_test_cmd_set_lss_status(struct nfit_test *t,
 911                 struct nd_intel_lss *nd_cmd, unsigned int buf_len)
 912 {
 913         struct device *dev = &t->pdev.dev;
 914
 915         if (buf_len < sizeof(*nd_cmd))
 916                 return -EINVAL;
 917
 918         switch (nd_cmd->enable) {
 919         case 0:
 920                 nd_cmd->status = 0;
 921                 dev_dbg(dev, "%s: Latch System Shutdown Status disabled\n",
 922                                 __func__);
 923                 break;
 924         case 1:
 925                 nd_cmd->status = 0;
 926                 dev_dbg(dev, "%s: Latch System Shutdown Status enabled\n",
 927                                 __func__);
 928                 break;
 929         default:
 930                 dev_warn(dev, "Unknown enable value: %#x\n", nd_cmd->enable);
 931                 nd_cmd->status = 0x3;
 932                 break;
 933         }
 934
 935
 936         return 0;
 937 }
 938
 939 static int override_return_code(int dimm, unsigned int func, int rc)
 940 {
 941         if ((1 << func) & dimm_fail_cmd_flags[dimm]) {
 942                 if (dimm_fail_cmd_code[dimm])
 943                         return dimm_fail_cmd_code[dimm];
 944                 return -EIO;
 945         }
 946         return rc;
 947 }
 948
 949 static int nd_intel_test_cmd_security_status(struct nfit_test *t,
 950                 struct nd_intel_get_security_state *nd_cmd,
 951                 unsigned int buf_len, int dimm)
 952 {
 953         struct device *dev = &t->pdev.dev;
 954         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
 955
 956         nd_cmd->status = 0;
 957         nd_cmd->state = sec->state;
 958         nd_cmd->extended_state = sec->ext_state;
 959         dev_dbg(dev, "security state (%#x) returned\n", nd_cmd->state);
 960
 961         return 0;
 962 }
 963
 964 static int nd_intel_test_cmd_unlock_unit(struct nfit_test *t,
 965                 struct nd_intel_unlock_unit *nd_cmd,
 966                 unsigned int buf_len, int dimm)
 967 {
 968         struct device *dev = &t->pdev.dev;
 969         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
 970
 971         if (!(sec->state & ND_INTEL_SEC_STATE_LOCKED) ||
 972                         (sec->state & ND_INTEL_SEC_STATE_FROZEN)) {
 973                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
 974                 dev_dbg(dev, "unlock unit: invalid state: %#x\n",
 975                                 sec->state);
 976         } else if (memcmp(nd_cmd->passphrase, sec->passphrase,
 977                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
 978                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
 979                 dev_dbg(dev, "unlock unit: invalid passphrase\n");
 980         } else {
 981                 nd_cmd->status = 0;
 982                 sec->state = ND_INTEL_SEC_STATE_ENABLED;
 983                 dev_dbg(dev, "Unit unlocked\n");
 984         }
 985
 986         dev_dbg(dev, "unlocking status returned: %#x\n", nd_cmd->status);
 987         return 0;
 988 }
 989
 990 static int nd_intel_test_cmd_set_pass(struct nfit_test *t,
 991                 struct nd_intel_set_passphrase *nd_cmd,
 992                 unsigned int buf_len, int dimm)
 993 {
 994         struct device *dev = &t->pdev.dev;
 995         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
 996
 997         if (sec->state & ND_INTEL_SEC_STATE_FROZEN) {
 998                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
 999                 dev_dbg(dev, "set passphrase: wrong security state\n");
1000         } else if (memcmp(nd_cmd->old_pass, sec->passphrase,
1001                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1002                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1003                 dev_dbg(dev, "set passphrase: wrong passphrase\n");
1004         } else {
1005                 memcpy(sec->passphrase, nd_cmd->new_pass,
1006                                 ND_INTEL_PASSPHRASE_SIZE);
1007                 sec->state |= ND_INTEL_SEC_STATE_ENABLED;
1008                 nd_cmd->status = 0;
1009                 dev_dbg(dev, "passphrase updated\n");
1010         }
1011
1012         return 0;
1013 }
1014
1015 static int nd_intel_test_cmd_freeze_lock(struct nfit_test *t,
1016                 struct nd_intel_freeze_lock *nd_cmd,
1017                 unsigned int buf_len, int dimm)
1018 {
1019         struct device *dev = &t->pdev.dev;
1020         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1021
1022         if (!(sec->state & ND_INTEL_SEC_STATE_ENABLED)) {
1023                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1024                 dev_dbg(dev, "freeze lock: wrong security state\n");
1025         } else {
1026                 sec->state |= ND_INTEL_SEC_STATE_FROZEN;
1027                 nd_cmd->status = 0;
1028                 dev_dbg(dev, "security frozen\n");
1029         }
1030
1031         return 0;
1032 }
1033
1034 static int nd_intel_test_cmd_disable_pass(struct nfit_test *t,
1035                 struct nd_intel_disable_passphrase *nd_cmd,
1036                 unsigned int buf_len, int dimm)
1037 {
1038         struct device *dev = &t->pdev.dev;
1039         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1040
1041         if (!(sec->state & ND_INTEL_SEC_STATE_ENABLED) ||
1042                         (sec->state & ND_INTEL_SEC_STATE_FROZEN)) {
1043                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1044                 dev_dbg(dev, "disable passphrase: wrong security state\n");
1045         } else if (memcmp(nd_cmd->passphrase, sec->passphrase,
1046                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1047                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1048                 dev_dbg(dev, "disable passphrase: wrong passphrase\n");
1049         } else {
1050                 memset(sec->passphrase, 0, ND_INTEL_PASSPHRASE_SIZE);
1051                 sec->state = 0;
1052                 dev_dbg(dev, "disable passphrase: done\n");
1053         }
1054
1055         return 0;
1056 }
1057
1058 static int nd_intel_test_cmd_secure_erase(struct nfit_test *t,
1059                 struct nd_intel_secure_erase *nd_cmd,
1060                 unsigned int buf_len, int dimm)
1061 {
1062         struct device *dev = &t->pdev.dev;
1063         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1064
1065         if (sec->state & ND_INTEL_SEC_STATE_FROZEN) {
1066                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1067                 dev_dbg(dev, "secure erase: wrong security state\n");
1068         } else if (memcmp(nd_cmd->passphrase, sec->passphrase,
1069                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1070                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1071                 dev_dbg(dev, "secure erase: wrong passphrase\n");
1072         } else {
1073                 if (!(sec->state & ND_INTEL_SEC_STATE_ENABLED)
1074                                 && (memcmp(nd_cmd->passphrase, zero_key,
1075                                         ND_INTEL_PASSPHRASE_SIZE) != 0)) {
1076                         dev_dbg(dev, "invalid zero key\n");
1077                         return 0;
1078                 }
1079                 memset(sec->passphrase, 0, ND_INTEL_PASSPHRASE_SIZE);
1080                 memset(sec->master_passphrase, 0, ND_INTEL_PASSPHRASE_SIZE);
1081                 sec->state = 0;
1082                 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1083                 dev_dbg(dev, "secure erase: done\n");
1084         }
1085
1086         return 0;
1087 }
1088
1089 static int nd_intel_test_cmd_overwrite(struct nfit_test *t,
1090                 struct nd_intel_overwrite *nd_cmd,
1091                 unsigned int buf_len, int dimm)
1092 {
1093         struct device *dev = &t->pdev.dev;
1094         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1095
1096         if ((sec->state & ND_INTEL_SEC_STATE_ENABLED) &&
1097                         memcmp(nd_cmd->passphrase, sec->passphrase,
1098                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1099                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1100                 dev_dbg(dev, "overwrite: wrong passphrase\n");
1101                 return 0;
1102         }
1103
1104         sec->old_state = sec->state;
1105         sec->state = ND_INTEL_SEC_STATE_OVERWRITE;
1106         dev_dbg(dev, "overwrite progressing.\n");
1107         sec->overwrite_end_time = get_jiffies_64() + 5 * HZ;
1108
1109         return 0;
1110 }
1111
1112 static int nd_intel_test_cmd_query_overwrite(struct nfit_test *t,
1113                 struct nd_intel_query_overwrite *nd_cmd,
1114                 unsigned int buf_len, int dimm)
1115 {
1116         struct device *dev = &t->pdev.dev;
1117         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1118
1119         if (!(sec->state & ND_INTEL_SEC_STATE_OVERWRITE)) {
1120                 nd_cmd->status = ND_INTEL_STATUS_OQUERY_SEQUENCE_ERR;
1121                 return 0;
1122         }
1123
1124         if (time_is_before_jiffies64(sec->overwrite_end_time)) {
1125                 sec->overwrite_end_time = 0;
1126                 sec->state = sec->old_state;
1127                 sec->old_state = 0;
1128                 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1129                 dev_dbg(dev, "overwrite is complete\n");
1130         } else
1131                 nd_cmd->status = ND_INTEL_STATUS_OQUERY_INPROGRESS;
1132         return 0;
1133 }
1134
1135 static int nd_intel_test_cmd_master_set_pass(struct nfit_test *t,
1136                 struct nd_intel_set_master_passphrase *nd_cmd,
1137                 unsigned int buf_len, int dimm)
1138 {
1139         struct device *dev = &t->pdev.dev;
1140         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1141
1142         if (!(sec->ext_state & ND_INTEL_SEC_ESTATE_ENABLED)) {
1143                 nd_cmd->status = ND_INTEL_STATUS_NOT_SUPPORTED;
1144                 dev_dbg(dev, "master set passphrase: in wrong state\n");
1145         } else if (sec->ext_state & ND_INTEL_SEC_ESTATE_PLIMIT) {
1146                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1147                 dev_dbg(dev, "master set passphrase: in wrong security state\n");
1148         } else if (memcmp(nd_cmd->old_pass, sec->master_passphrase,
1149                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1150                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1151                 dev_dbg(dev, "master set passphrase: wrong passphrase\n");
1152         } else {
1153                 memcpy(sec->master_passphrase, nd_cmd->new_pass,
1154                                 ND_INTEL_PASSPHRASE_SIZE);
1155                 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1156                 dev_dbg(dev, "master passphrase: updated\n");
1157         }
1158
1159         return 0;
1160 }
1161
1162 static int nd_intel_test_cmd_master_secure_erase(struct nfit_test *t,
1163                 struct nd_intel_master_secure_erase *nd_cmd,
1164                 unsigned int buf_len, int dimm)
1165 {
1166         struct device *dev = &t->pdev.dev;
1167         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1168
1169         if (!(sec->ext_state & ND_INTEL_SEC_ESTATE_ENABLED)) {
1170                 nd_cmd->status = ND_INTEL_STATUS_NOT_SUPPORTED;
1171                 dev_dbg(dev, "master secure erase: in wrong state\n");
1172         } else if (sec->ext_state & ND_INTEL_SEC_ESTATE_PLIMIT) {
1173                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1174                 dev_dbg(dev, "master secure erase: in wrong security state\n");
1175         } else if (memcmp(nd_cmd->passphrase, sec->master_passphrase,
1176                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1177                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1178                 dev_dbg(dev, "master secure erase: wrong passphrase\n");
1179         } else {
1180                 /* we do not erase master state passphrase ever */
1181                 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1182                 memset(sec->passphrase, 0, ND_INTEL_PASSPHRASE_SIZE);
1183                 sec->state = 0;
1184                 dev_dbg(dev, "master secure erase: done\n");
1185         }
1186
1187         return 0;
1188 }
1189
1190
1191 static int get_dimm(struct nfit_mem *nfit_mem, unsigned int func)
1192 {
1193         int i;
1194
1195         /* lookup per-dimm data */
1196         for (i = 0; i < ARRAY_SIZE(handle); i++)
1197                 if (__to_nfit_memdev(nfit_mem)->device_handle == handle[i])
1198                         break;
1199         if (i >= ARRAY_SIZE(handle))
1200                 return -ENXIO;
1201         return i;
1202 }
1203
1204 static int nfit_test_ctl(struct nvdimm_bus_descriptor *nd_desc,
1205                 struct nvdimm *nvdimm, unsigned int cmd, void *buf,
1206                 unsigned int buf_len, int *cmd_rc)
1207 {
1208         struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
1209         struct nfit_test *t = container_of(acpi_desc, typeof(*t), acpi_desc);
1210         unsigned int func = cmd;
1211         int i, rc = 0, __cmd_rc;
1212
1213         if (!cmd_rc)
1214                 cmd_rc = &__cmd_rc;
1215         *cmd_rc = 0;
1216
1217         if (nvdimm) {
1218                 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
1219                 unsigned long cmd_mask = nvdimm_cmd_mask(nvdimm);
1220
1221                 if (!nfit_mem)
1222                         return -ENOTTY;
1223
1224                 if (cmd == ND_CMD_CALL) {
1225                         struct nd_cmd_pkg *call_pkg = buf;
1226
1227                         buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
1228                         buf = (void *) call_pkg->nd_payload;
1229                         func = call_pkg->nd_command;
1230                         if (call_pkg->nd_family != nfit_mem->family)
1231                                 return -ENOTTY;
1232
1233                         i = get_dimm(nfit_mem, func);
1234                         if (i < 0)
1235                                 return i;
1236
1237                         switch (func) {
1238                         case NVDIMM_INTEL_GET_SECURITY_STATE:
1239                                 rc = nd_intel_test_cmd_security_status(t,
1240                                                 buf, buf_len, i);
1241                                 break;
1242                         case NVDIMM_INTEL_UNLOCK_UNIT:
1243                                 rc = nd_intel_test_cmd_unlock_unit(t,
1244                                                 buf, buf_len, i);
1245                                 break;
1246                         case NVDIMM_INTEL_SET_PASSPHRASE:
1247                                 rc = nd_intel_test_cmd_set_pass(t,
1248                                                 buf, buf_len, i);
1249                                 break;
1250                         case NVDIMM_INTEL_DISABLE_PASSPHRASE:
1251                                 rc = nd_intel_test_cmd_disable_pass(t,
1252                                                 buf, buf_len, i);
1253                                 break;
1254                         case NVDIMM_INTEL_FREEZE_LOCK:
1255                                 rc = nd_intel_test_cmd_freeze_lock(t,
1256                                                 buf, buf_len, i);
1257                                 break;
1258                         case NVDIMM_INTEL_SECURE_ERASE:
1259                                 rc = nd_intel_test_cmd_secure_erase(t,
1260                                                 buf, buf_len, i);
1261                                 break;
1262                         case NVDIMM_INTEL_OVERWRITE:
1263                                 rc = nd_intel_test_cmd_overwrite(t,
1264                                                 buf, buf_len, i - t->dcr_idx);
1265                                 break;
1266                         case NVDIMM_INTEL_QUERY_OVERWRITE:
1267                                 rc = nd_intel_test_cmd_query_overwrite(t,
1268                                                 buf, buf_len, i - t->dcr_idx);
1269                                 break;
1270                         case NVDIMM_INTEL_SET_MASTER_PASSPHRASE:
1271                                 rc = nd_intel_test_cmd_master_set_pass(t,
1272                                                 buf, buf_len, i);
1273                                 break;
1274                         case NVDIMM_INTEL_MASTER_SECURE_ERASE:
1275                                 rc = nd_intel_test_cmd_master_secure_erase(t,
1276                                                 buf, buf_len, i);
1277                                 break;
1278                         case ND_INTEL_ENABLE_LSS_STATUS:
1279                                 rc = nd_intel_test_cmd_set_lss_status(t,
1280                                                 buf, buf_len);
1281                                 break;
1282                         case ND_INTEL_FW_GET_INFO:
1283                                 rc = nd_intel_test_get_fw_info(t, buf,
1284                                                 buf_len, i - t->dcr_idx);
1285                                 break;
1286                         case ND_INTEL_FW_START_UPDATE:
1287                                 rc = nd_intel_test_start_update(t, buf,
1288                                                 buf_len, i - t->dcr_idx);
1289                                 break;
1290                         case ND_INTEL_FW_SEND_DATA:
1291                                 rc = nd_intel_test_send_data(t, buf,
1292                                                 buf_len, i - t->dcr_idx);
1293                                 break;
1294                         case ND_INTEL_FW_FINISH_UPDATE:
1295                                 rc = nd_intel_test_finish_fw(t, buf,
1296                                                 buf_len, i - t->dcr_idx);
1297                                 break;
1298                         case ND_INTEL_FW_FINISH_QUERY:
1299                                 rc = nd_intel_test_finish_query(t, buf,
1300                                                 buf_len, i - t->dcr_idx);
1301                                 break;
1302                         case ND_INTEL_SMART:
1303                                 rc = nfit_test_cmd_smart(buf, buf_len,
1304                                                 &t->smart[i - t->dcr_idx]);
1305                                 break;
1306                         case ND_INTEL_SMART_THRESHOLD:
1307                                 rc = nfit_test_cmd_smart_threshold(buf,
1308                                                 buf_len,
1309                                                 &t->smart_threshold[i -
1310                                                         t->dcr_idx]);
1311                                 break;
1312                         case ND_INTEL_SMART_SET_THRESHOLD:
1313                                 rc = nfit_test_cmd_smart_set_threshold(buf,
1314                                                 buf_len,
1315                                                 &t->smart_threshold[i -
1316                                                         t->dcr_idx],
1317                                                 &t->smart[i - t->dcr_idx],
1318                                                 &t->pdev.dev, t->dimm_dev[i]);
1319                                 break;
1320                         case ND_INTEL_SMART_INJECT:
1321                                 rc = nfit_test_cmd_smart_inject(buf,
1322                                                 buf_len,
1323                                                 &t->smart_threshold[i -
1324                                                         t->dcr_idx],
1325                                                 &t->smart[i - t->dcr_idx],
1326                                                 &t->pdev.dev, t->dimm_dev[i]);
1327                                 break;
1328                         default:
1329                                 return -ENOTTY;
1330                         }
1331                         return override_return_code(i, func, rc);
1332                 }
1333
1334                 if (!test_bit(cmd, &cmd_mask)
1335                                 || !test_bit(func, &nfit_mem->dsm_mask))
1336                         return -ENOTTY;
1337
1338                 i = get_dimm(nfit_mem, func);
1339                 if (i < 0)
1340                         return i;
1341
1342                 switch (func) {
1343                 case ND_CMD_GET_CONFIG_SIZE:
1344                         rc = nfit_test_cmd_get_config_size(buf, buf_len);
1345                         break;
1346                 case ND_CMD_GET_CONFIG_DATA:
1347                         rc = nfit_test_cmd_get_config_data(buf, buf_len,
1348                                 t->label[i - t->dcr_idx]);
1349                         break;
1350                 case ND_CMD_SET_CONFIG_DATA:
1351                         rc = nfit_test_cmd_set_config_data(buf, buf_len,
1352                                 t->label[i - t->dcr_idx]);
1353                         break;
1354                 default:
1355                         return -ENOTTY;
1356                 }
1357                 return override_return_code(i, func, rc);
1358         } else {
1359                 struct ars_state *ars_state = &t->ars_state;
1360                 struct nd_cmd_pkg *call_pkg = buf;
1361
1362                 if (!nd_desc)
1363                         return -ENOTTY;
1364
1365                 if (cmd == ND_CMD_CALL) {
1366                         func = call_pkg->nd_command;
1367
1368                         buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
1369                         buf = (void *) call_pkg->nd_payload;
1370
1371                         switch (func) {
1372                         case NFIT_CMD_TRANSLATE_SPA:
1373                                 rc = nfit_test_cmd_translate_spa(
1374                                         acpi_desc->nvdimm_bus, buf, buf_len);
1375                                 return rc;
1376                         case NFIT_CMD_ARS_INJECT_SET:
1377                                 rc = nfit_test_cmd_ars_error_inject(t, buf,
1378                                         buf_len);
1379                                 return rc;
1380                         case NFIT_CMD_ARS_INJECT_CLEAR:
1381                                 rc = nfit_test_cmd_ars_inject_clear(t, buf,
1382                                         buf_len);
1383                                 return rc;
1384                         case NFIT_CMD_ARS_INJECT_GET:
1385                                 rc = nfit_test_cmd_ars_inject_status(t, buf,
1386                                         buf_len);
1387                                 return rc;
1388                         default:
1389                                 return -ENOTTY;
1390                         }
1391                 }
1392
1393                 if (!nd_desc || !test_bit(cmd, &nd_desc->cmd_mask))
1394                         return -ENOTTY;
1395
1396                 switch (func) {
1397                 case ND_CMD_ARS_CAP:
1398                         rc = nfit_test_cmd_ars_cap(buf, buf_len);
1399                         break;
1400                 case ND_CMD_ARS_START:
1401                         rc = nfit_test_cmd_ars_start(t, ars_state, buf,
1402                                         buf_len, cmd_rc);
1403                         break;
1404                 case ND_CMD_ARS_STATUS:
1405                         rc = nfit_test_cmd_ars_status(ars_state, buf, buf_len,
1406                                         cmd_rc);
1407                         break;
1408                 case ND_CMD_CLEAR_ERROR:
1409                         rc = nfit_test_cmd_clear_error(t, buf, buf_len, cmd_rc);
1410                         break;
1411                 default:
1412                         return -ENOTTY;
1413                 }
1414         }
1415
1416         return rc;
1417 }
1418
1419 static DEFINE_SPINLOCK(nfit_test_lock);
1420 static struct nfit_test *instances[NUM_NFITS];
1421
1422 static void release_nfit_res(void *data)
1423 {
1424         struct nfit_test_resource *nfit_res = data;
1425
1426         spin_lock(&nfit_test_lock);
1427         list_del(&nfit_res->list);
1428         spin_unlock(&nfit_test_lock);
1429
1430         if (resource_size(&nfit_res->res) >= DIMM_SIZE)
1431                 gen_pool_free(nfit_pool, nfit_res->res.start,
1432                                 resource_size(&nfit_res->res));
1433         vfree(nfit_res->buf);
1434         kfree(nfit_res);
1435 }
1436
1437 static void *__test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma,
1438                 void *buf)
1439 {
1440         struct device *dev = &t->pdev.dev;
1441         struct nfit_test_resource *nfit_res = kzalloc(sizeof(*nfit_res),
1442                         GFP_KERNEL);
1443         int rc;
1444
1445         if (!buf || !nfit_res || !*dma)
1446                 goto err;
1447         rc = devm_add_action(dev, release_nfit_res, nfit_res);
1448         if (rc)
1449                 goto err;
1450         INIT_LIST_HEAD(&nfit_res->list);
1451         memset(buf, 0, size);
1452         nfit_res->dev = dev;
1453         nfit_res->buf = buf;
1454         nfit_res->res.start = *dma;
1455         nfit_res->res.end = *dma + size - 1;
1456         nfit_res->res.name = "NFIT";
1457         spin_lock_init(&nfit_res->lock);
1458         INIT_LIST_HEAD(&nfit_res->requests);
1459         spin_lock(&nfit_test_lock);
1460         list_add(&nfit_res->list, &t->resources);
1461         spin_unlock(&nfit_test_lock);
1462
1463         return nfit_res->buf;
1464  err:
1465         if (*dma && size >= DIMM_SIZE)
1466                 gen_pool_free(nfit_pool, *dma, size);
1467         if (buf)
1468                 vfree(buf);
1469         kfree(nfit_res);
1470         return NULL;
1471 }
1472
1473 static void *test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma)
1474 {
1475         struct genpool_data_align data = {
1476                 .align = SZ_128M,
1477         };
1478         void *buf = vmalloc(size);
1479
1480         if (size >= DIMM_SIZE)
1481                 *dma = gen_pool_alloc_algo(nfit_pool, size,
1482                                 gen_pool_first_fit_align, &data);
1483         else
1484                 *dma = (unsigned long) buf;
1485         return __test_alloc(t, size, dma, buf);
1486 }
1487
1488 static struct nfit_test_resource *nfit_test_lookup(resource_size_t addr)
1489 {
1490         int i;
1491
1492         for (i = 0; i < ARRAY_SIZE(instances); i++) {
1493                 struct nfit_test_resource *n, *nfit_res = NULL;
1494                 struct nfit_test *t = instances[i];
1495
1496                 if (!t)
1497                         continue;
1498                 spin_lock(&nfit_test_lock);
1499                 list_for_each_entry(n, &t->resources, list) {
1500                         if (addr >= n->res.start && (addr < n->res.start
1501                                                 + resource_size(&n->res))) {
1502                                 nfit_res = n;
1503                                 break;
1504                         } else if (addr >= (unsigned long) n->buf
1505                                         && (addr < (unsigned long) n->buf
1506                                                 + resource_size(&n->res))) {
1507                                 nfit_res = n;
1508                                 break;
1509                         }
1510                 }
1511                 spin_unlock(&nfit_test_lock);
1512                 if (nfit_res)
1513                         return nfit_res;
1514         }
1515
1516         return NULL;
1517 }
1518
1519 static int ars_state_init(struct device *dev, struct ars_state *ars_state)
1520 {
1521         /* for testing, only store up to n records that fit within 4k */
1522         ars_state->ars_status = devm_kzalloc(dev,
1523                         sizeof(struct nd_cmd_ars_status) + SZ_4K, GFP_KERNEL);
1524         if (!ars_state->ars_status)
1525                 return -ENOMEM;
1526         spin_lock_init(&ars_state->lock);
1527         return 0;
1528 }
1529
1530 static void put_dimms(void *data)
1531 {
1532         struct nfit_test *t = data;
1533         int i;
1534
1535         for (i = 0; i < t->num_dcr; i++)
1536                 if (t->dimm_dev[i])
1537                         device_unregister(t->dimm_dev[i]);
1538 }
1539
1540 static struct class *nfit_test_dimm;
1541
1542 static int dimm_name_to_id(struct device *dev)
1543 {
1544         int dimm;
1545
1546         if (sscanf(dev_name(dev), "test_dimm%d", &dimm) != 1)
1547                 return -ENXIO;
1548         return dimm;
1549 }
1550
1551 static ssize_t handle_show(struct device *dev, struct device_attribute *attr,
1552                 char *buf)
1553 {
1554         int dimm = dimm_name_to_id(dev);
1555
1556         if (dimm < 0)
1557                 return dimm;
1558
1559         return sprintf(buf, "%#x\n", handle[dimm]);
1560 }
1561 DEVICE_ATTR_RO(handle);
1562
1563 static ssize_t fail_cmd_show(struct device *dev, struct device_attribute *attr,
1564                 char *buf)
1565 {
1566         int dimm = dimm_name_to_id(dev);
1567
1568         if (dimm < 0)
1569                 return dimm;
1570
1571         return sprintf(buf, "%#lx\n", dimm_fail_cmd_flags[dimm]);
1572 }
1573
1574 static ssize_t fail_cmd_store(struct device *dev, struct device_attribute *attr,
1575                 const char *buf, size_t size)
1576 {
1577         int dimm = dimm_name_to_id(dev);
1578         unsigned long val;
1579         ssize_t rc;
1580
1581         if (dimm < 0)
1582                 return dimm;
1583
1584         rc = kstrtol(buf, 0, &val);
1585         if (rc)
1586                 return rc;
1587
1588         dimm_fail_cmd_flags[dimm] = val;
1589         return size;
1590 }
1591 static DEVICE_ATTR_RW(fail_cmd);
1592
1593 static ssize_t fail_cmd_code_show(struct device *dev, struct device_attribute *attr,
1594                 char *buf)
1595 {
1596         int dimm = dimm_name_to_id(dev);
1597
1598         if (dimm < 0)
1599                 return dimm;
1600
1601         return sprintf(buf, "%d\n", dimm_fail_cmd_code[dimm]);
1602 }
1603
1604 static ssize_t fail_cmd_code_store(struct device *dev, struct device_attribute *attr,
1605                 const char *buf, size_t size)
1606 {
1607         int dimm = dimm_name_to_id(dev);
1608         unsigned long val;
1609         ssize_t rc;
1610
1611         if (dimm < 0)
1612                 return dimm;
1613
1614         rc = kstrtol(buf, 0, &val);
1615         if (rc)
1616                 return rc;
1617
1618         dimm_fail_cmd_code[dimm] = val;
1619         return size;
1620 }
1621 static DEVICE_ATTR_RW(fail_cmd_code);
1622
1623 static ssize_t lock_dimm_store(struct device *dev,
1624                 struct device_attribute *attr, const char *buf, size_t size)
1625 {
1626         int dimm = dimm_name_to_id(dev);
1627         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1628
1629         sec->state = ND_INTEL_SEC_STATE_ENABLED | ND_INTEL_SEC_STATE_LOCKED;
1630         return size;
1631 }
1632 static DEVICE_ATTR_WO(lock_dimm);
1633
1634 static struct attribute *nfit_test_dimm_attributes[] = {
1635         &dev_attr_fail_cmd.attr,
1636         &dev_attr_fail_cmd_code.attr,
1637         &dev_attr_handle.attr,
1638         &dev_attr_lock_dimm.attr,
1639         NULL,
1640 };
1641
1642 static struct attribute_group nfit_test_dimm_attribute_group = {
1643         .attrs = nfit_test_dimm_attributes,
1644 };
1645
1646 static const struct attribute_group *nfit_test_dimm_attribute_groups[] = {
1647         &nfit_test_dimm_attribute_group,
1648         NULL,
1649 };
1650
1651 static int nfit_test_dimm_init(struct nfit_test *t)
1652 {
1653         int i;
1654
1655         if (devm_add_action_or_reset(&t->pdev.dev, put_dimms, t))
1656                 return -ENOMEM;
1657         for (i = 0; i < t->num_dcr; i++) {
1658                 t->dimm_dev[i] = device_create_with_groups(nfit_test_dimm,
1659                                 &t->pdev.dev, 0, NULL,
1660                                 nfit_test_dimm_attribute_groups,
1661                                 "test_dimm%d", i + t->dcr_idx);
1662                 if (!t->dimm_dev[i])
1663                         return -ENOMEM;
1664         }
1665         return 0;
1666 }
1667
1668 static void security_init(struct nfit_test *t)
1669 {
1670         int i;
1671
1672         for (i = 0; i < t->num_dcr; i++) {
1673                 struct nfit_test_sec *sec = &dimm_sec_info[i];
1674
1675                 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1676         }
1677 }
1678
1679 static void smart_init(struct nfit_test *t)
1680 {
1681         int i;
1682         const struct nd_intel_smart_threshold smart_t_data = {
1683                 .alarm_control = ND_INTEL_SMART_SPARE_TRIP
1684                         | ND_INTEL_SMART_TEMP_TRIP,
1685                 .media_temperature = 40 * 16,
1686                 .ctrl_temperature = 30 * 16,
1687                 .spares = 5,
1688         };
1689
1690         for (i = 0; i < t->num_dcr; i++) {
1691                 memcpy(&t->smart[i], &smart_def, sizeof(smart_def));
1692                 memcpy(&t->smart_threshold[i], &smart_t_data,
1693                                 sizeof(smart_t_data));
1694         }
1695 }
1696
1697 static int nfit_test0_alloc(struct nfit_test *t)
1698 {
1699         size_t nfit_size = sizeof(struct acpi_nfit_system_address) * NUM_SPA
1700                         + sizeof(struct acpi_nfit_memory_map) * NUM_MEM
1701                         + sizeof(struct acpi_nfit_control_region) * NUM_DCR
1702                         + offsetof(struct acpi_nfit_control_region,
1703                                         window_size) * NUM_DCR
1704                         + sizeof(struct acpi_nfit_data_region) * NUM_BDW
1705                         + (sizeof(struct acpi_nfit_flush_address)
1706                                         + sizeof(u64) * NUM_HINTS) * NUM_DCR
1707                         + sizeof(struct acpi_nfit_capabilities);
1708         int i;
1709
1710         t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
1711         if (!t->nfit_buf)
1712                 return -ENOMEM;
1713         t->nfit_size = nfit_size;
1714
1715         t->spa_set[0] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[0]);
1716         if (!t->spa_set[0])
1717                 return -ENOMEM;
1718
1719         t->spa_set[1] = test_alloc(t, SPA1_SIZE, &t->spa_set_dma[1]);
1720         if (!t->spa_set[1])
1721                 return -ENOMEM;
1722
1723         t->spa_set[2] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[2]);
1724         if (!t->spa_set[2])
1725                 return -ENOMEM;
1726
1727         for (i = 0; i < t->num_dcr; i++) {
1728                 t->dimm[i] = test_alloc(t, DIMM_SIZE, &t->dimm_dma[i]);
1729                 if (!t->dimm[i])
1730                         return -ENOMEM;
1731
1732                 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]);
1733                 if (!t->label[i])
1734                         return -ENOMEM;
1735                 sprintf(t->label[i], "label%d", i);
1736
1737                 t->flush[i] = test_alloc(t, max(PAGE_SIZE,
1738                                         sizeof(u64) * NUM_HINTS),
1739                                 &t->flush_dma[i]);
1740                 if (!t->flush[i])
1741                         return -ENOMEM;
1742         }
1743
1744         for (i = 0; i < t->num_dcr; i++) {
1745                 t->dcr[i] = test_alloc(t, LABEL_SIZE, &t->dcr_dma[i]);
1746                 if (!t->dcr[i])
1747                         return -ENOMEM;
1748         }
1749
1750         t->_fit = test_alloc(t, sizeof(union acpi_object **), &t->_fit_dma);
1751         if (!t->_fit)
1752                 return -ENOMEM;
1753
1754         if (nfit_test_dimm_init(t))
1755                 return -ENOMEM;
1756         smart_init(t);
1757         security_init(t);
1758         return ars_state_init(&t->pdev.dev, &t->ars_state);
1759 }
1760
1761 static int nfit_test1_alloc(struct nfit_test *t)
1762 {
1763         size_t nfit_size = sizeof(struct acpi_nfit_system_address) * 2
1764                 + sizeof(struct acpi_nfit_memory_map) * 2
1765                 + offsetof(struct acpi_nfit_control_region, window_size) * 2;
1766         int i;
1767
1768         t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
1769         if (!t->nfit_buf)
1770                 return -ENOMEM;
1771         t->nfit_size = nfit_size;
1772
1773         t->spa_set[0] = test_alloc(t, SPA2_SIZE, &t->spa_set_dma[0]);
1774         if (!t->spa_set[0])
1775                 return -ENOMEM;
1776
1777         for (i = 0; i < t->num_dcr; i++) {
1778                 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]);
1779                 if (!t->label[i])
1780                         return -ENOMEM;
1781                 sprintf(t->label[i], "label%d", i);
1782         }
1783
1784         t->spa_set[1] = test_alloc(t, SPA_VCD_SIZE, &t->spa_set_dma[1]);
1785         if (!t->spa_set[1])
1786                 return -ENOMEM;
1787
1788         if (nfit_test_dimm_init(t))
1789                 return -ENOMEM;
1790         smart_init(t);
1791         return ars_state_init(&t->pdev.dev, &t->ars_state);
1792 }
1793
1794 static void dcr_common_init(struct acpi_nfit_control_region *dcr)
1795 {
1796         dcr->vendor_id = 0xabcd;
1797         dcr->device_id = 0;
1798         dcr->revision_id = 1;
1799         dcr->valid_fields = 1;
1800         dcr->manufacturing_location = 0xa;
1801         dcr->manufacturing_date = cpu_to_be16(2016);
1802 }
1803
1804 static void nfit_test0_setup(struct nfit_test *t)
1805 {
1806         const int flush_hint_size = sizeof(struct acpi_nfit_flush_address)
1807                 + (sizeof(u64) * NUM_HINTS);
1808         struct acpi_nfit_desc *acpi_desc;
1809         struct acpi_nfit_memory_map *memdev;
1810         void *nfit_buf = t->nfit_buf;
1811         struct acpi_nfit_system_address *spa;
1812         struct acpi_nfit_control_region *dcr;
1813         struct acpi_nfit_data_region *bdw;
1814         struct acpi_nfit_flush_address *flush;
1815         struct acpi_nfit_capabilities *pcap;
1816         unsigned int offset = 0, i;
1817
1818         /*
1819          * spa0 (interleave first half of dimm0 and dimm1, note storage
1820          * does not actually alias the related block-data-window
1821          * regions)
1822          */
1823         spa = nfit_buf;
1824         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1825         spa->header.length = sizeof(*spa);
1826         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
1827         spa->range_index = 0+1;
1828         spa->address = t->spa_set_dma[0];
1829         spa->length = SPA0_SIZE;
1830         offset += spa->header.length;
1831
1832         /*
1833          * spa1 (interleave last half of the 4 DIMMS, note storage
1834          * does not actually alias the related block-data-window
1835          * regions)
1836          */
1837         spa = nfit_buf + offset;
1838         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1839         spa->header.length = sizeof(*spa);
1840         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
1841         spa->range_index = 1+1;
1842         spa->address = t->spa_set_dma[1];
1843         spa->length = SPA1_SIZE;
1844         offset += spa->header.length;
1845
1846         /* spa2 (dcr0) dimm0 */
1847         spa = nfit_buf + offset;
1848         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1849         spa->header.length = sizeof(*spa);
1850         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1851         spa->range_index = 2+1;
1852         spa->address = t->dcr_dma[0];
1853         spa->length = DCR_SIZE;
1854         offset += spa->header.length;
1855
1856         /* spa3 (dcr1) dimm1 */
1857         spa = nfit_buf + offset;
1858         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1859         spa->header.length = sizeof(*spa);
1860         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1861         spa->range_index = 3+1;
1862         spa->address = t->dcr_dma[1];
1863         spa->length = DCR_SIZE;
1864         offset += spa->header.length;
1865
1866         /* spa4 (dcr2) dimm2 */
1867         spa = nfit_buf + offset;
1868         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1869         spa->header.length = sizeof(*spa);
1870         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1871         spa->range_index = 4+1;
1872         spa->address = t->dcr_dma[2];
1873         spa->length = DCR_SIZE;
1874         offset += spa->header.length;
1875
1876         /* spa5 (dcr3) dimm3 */
1877         spa = nfit_buf + offset;
1878         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1879         spa->header.length = sizeof(*spa);
1880         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1881         spa->range_index = 5+1;
1882         spa->address = t->dcr_dma[3];
1883         spa->length = DCR_SIZE;
1884         offset += spa->header.length;
1885
1886         /* spa6 (bdw for dcr0) dimm0 */
1887         spa = nfit_buf + offset;
1888         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1889         spa->header.length = sizeof(*spa);
1890         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1891         spa->range_index = 6+1;
1892         spa->address = t->dimm_dma[0];
1893         spa->length = DIMM_SIZE;
1894         offset += spa->header.length;
1895
1896         /* spa7 (bdw for dcr1) dimm1 */
1897         spa = nfit_buf + offset;
1898         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1899         spa->header.length = sizeof(*spa);
1900         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1901         spa->range_index = 7+1;
1902         spa->address = t->dimm_dma[1];
1903         spa->length = DIMM_SIZE;
1904         offset += spa->header.length;
1905
1906         /* spa8 (bdw for dcr2) dimm2 */
1907         spa = nfit_buf + offset;
1908         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1909         spa->header.length = sizeof(*spa);
1910         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1911         spa->range_index = 8+1;
1912         spa->address = t->dimm_dma[2];
1913         spa->length = DIMM_SIZE;
1914         offset += spa->header.length;
1915
1916         /* spa9 (bdw for dcr3) dimm3 */
1917         spa = nfit_buf + offset;
1918         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1919         spa->header.length = sizeof(*spa);
1920         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1921         spa->range_index = 9+1;
1922         spa->address = t->dimm_dma[3];
1923         spa->length = DIMM_SIZE;
1924         offset += spa->header.length;
1925
1926         /* mem-region0 (spa0, dimm0) */
1927         memdev = nfit_buf + offset;
1928         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1929         memdev->header.length = sizeof(*memdev);
1930         memdev->device_handle = handle[0];
1931         memdev->physical_id = 0;
1932         memdev->region_id = 0;
1933         memdev->range_index = 0+1;
1934         memdev->region_index = 4+1;
1935         memdev->region_size = SPA0_SIZE/2;
1936         memdev->region_offset = 1;
1937         memdev->address = 0;
1938         memdev->interleave_index = 0;
1939         memdev->interleave_ways = 2;
1940         offset += memdev->header.length;
1941
1942         /* mem-region1 (spa0, dimm1) */
1943         memdev = nfit_buf + offset;
1944         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1945         memdev->header.length = sizeof(*memdev);
1946         memdev->device_handle = handle[1];
1947         memdev->physical_id = 1;
1948         memdev->region_id = 0;
1949         memdev->range_index = 0+1;
1950         memdev->region_index = 5+1;
1951         memdev->region_size = SPA0_SIZE/2;
1952         memdev->region_offset = (1 << 8);
1953         memdev->address = 0;
1954         memdev->interleave_index = 0;
1955         memdev->interleave_ways = 2;
1956         memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
1957         offset += memdev->header.length;
1958
1959         /* mem-region2 (spa1, dimm0) */
1960         memdev = nfit_buf + offset;
1961         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1962         memdev->header.length = sizeof(*memdev);
1963         memdev->device_handle = handle[0];
1964         memdev->physical_id = 0;
1965         memdev->region_id = 1;
1966         memdev->range_index = 1+1;
1967         memdev->region_index = 4+1;
1968         memdev->region_size = SPA1_SIZE/4;
1969         memdev->region_offset = (1 << 16);
1970         memdev->address = SPA0_SIZE/2;
1971         memdev->interleave_index = 0;
1972         memdev->interleave_ways = 4;
1973         memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
1974         offset += memdev->header.length;
1975
1976         /* mem-region3 (spa1, dimm1) */
1977         memdev = nfit_buf + offset;
1978         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1979         memdev->header.length = sizeof(*memdev);
1980         memdev->device_handle = handle[1];
1981         memdev->physical_id = 1;
1982         memdev->region_id = 1;
1983         memdev->range_index = 1+1;
1984         memdev->region_index = 5+1;
1985         memdev->region_size = SPA1_SIZE/4;
1986         memdev->region_offset = (1 << 24);
1987         memdev->address = SPA0_SIZE/2;
1988         memdev->interleave_index = 0;
1989         memdev->interleave_ways = 4;
1990         offset += memdev->header.length;
1991
1992         /* mem-region4 (spa1, dimm2) */
1993         memdev = nfit_buf + offset;
1994         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1995         memdev->header.length = sizeof(*memdev);
1996         memdev->device_handle = handle[2];
1997         memdev->physical_id = 2;
1998         memdev->region_id = 0;
1999         memdev->range_index = 1+1;
2000         memdev->region_index = 6+1;
2001         memdev->region_size = SPA1_SIZE/4;
2002         memdev->region_offset = (1ULL << 32);
2003         memdev->address = SPA0_SIZE/2;
2004         memdev->interleave_index = 0;
2005         memdev->interleave_ways = 4;
2006         memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
2007         offset += memdev->header.length;
2008
2009         /* mem-region5 (spa1, dimm3) */
2010         memdev = nfit_buf + offset;
2011         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2012         memdev->header.length = sizeof(*memdev);
2013         memdev->device_handle = handle[3];
2014         memdev->physical_id = 3;
2015         memdev->region_id = 0;
2016         memdev->range_index = 1+1;
2017         memdev->region_index = 7+1;
2018         memdev->region_size = SPA1_SIZE/4;
2019         memdev->region_offset = (1ULL << 40);
2020         memdev->address = SPA0_SIZE/2;
2021         memdev->interleave_index = 0;
2022         memdev->interleave_ways = 4;
2023         offset += memdev->header.length;
2024
2025         /* mem-region6 (spa/dcr0, dimm0) */
2026         memdev = nfit_buf + offset;
2027         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2028         memdev->header.length = sizeof(*memdev);
2029         memdev->device_handle = handle[0];
2030         memdev->physical_id = 0;
2031         memdev->region_id = 0;
2032         memdev->range_index = 2+1;
2033         memdev->region_index = 0+1;
2034         memdev->region_size = 0;
2035         memdev->region_offset = 0;
2036         memdev->address = 0;
2037         memdev->interleave_index = 0;
2038         memdev->interleave_ways = 1;
2039         offset += memdev->header.length;
2040
2041         /* mem-region7 (spa/dcr1, dimm1) */
2042         memdev = nfit_buf + offset;
2043         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2044         memdev->header.length = sizeof(*memdev);
2045         memdev->device_handle = handle[1];
2046         memdev->physical_id = 1;
2047         memdev->region_id = 0;
2048         memdev->range_index = 3+1;
2049         memdev->region_index = 1+1;
2050         memdev->region_size = 0;
2051         memdev->region_offset = 0;
2052         memdev->address = 0;
2053         memdev->interleave_index = 0;
2054         memdev->interleave_ways = 1;
2055         offset += memdev->header.length;
2056
2057         /* mem-region8 (spa/dcr2, dimm2) */
2058         memdev = nfit_buf + offset;
2059         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2060         memdev->header.length = sizeof(*memdev);
2061         memdev->device_handle = handle[2];
2062         memdev->physical_id = 2;
2063         memdev->region_id = 0;
2064         memdev->range_index = 4+1;
2065         memdev->region_index = 2+1;
2066         memdev->region_size = 0;
2067         memdev->region_offset = 0;
2068         memdev->address = 0;
2069         memdev->interleave_index = 0;
2070         memdev->interleave_ways = 1;
2071         offset += memdev->header.length;
2072
2073         /* mem-region9 (spa/dcr3, dimm3) */
2074         memdev = nfit_buf + offset;
2075         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2076         memdev->header.length = sizeof(*memdev);
2077         memdev->device_handle = handle[3];
2078         memdev->physical_id = 3;
2079         memdev->region_id = 0;
2080         memdev->range_index = 5+1;
2081         memdev->region_index = 3+1;
2082         memdev->region_size = 0;
2083         memdev->region_offset = 0;
2084         memdev->address = 0;
2085         memdev->interleave_index = 0;
2086         memdev->interleave_ways = 1;
2087         offset += memdev->header.length;
2088
2089         /* mem-region10 (spa/bdw0, dimm0) */
2090         memdev = nfit_buf + offset;
2091         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2092         memdev->header.length = sizeof(*memdev);
2093         memdev->device_handle = handle[0];
2094         memdev->physical_id = 0;
2095         memdev->region_id = 0;
2096         memdev->range_index = 6+1;
2097         memdev->region_index = 0+1;
2098         memdev->region_size = 0;
2099         memdev->region_offset = 0;
2100         memdev->address = 0;
2101         memdev->interleave_index = 0;
2102         memdev->interleave_ways = 1;
2103         offset += memdev->header.length;
2104
2105         /* mem-region11 (spa/bdw1, dimm1) */
2106         memdev = nfit_buf + offset;
2107         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2108         memdev->header.length = sizeof(*memdev);
2109         memdev->device_handle = handle[1];
2110         memdev->physical_id = 1;
2111         memdev->region_id = 0;
2112         memdev->range_index = 7+1;
2113         memdev->region_index = 1+1;
2114         memdev->region_size = 0;
2115         memdev->region_offset = 0;
2116         memdev->address = 0;
2117         memdev->interleave_index = 0;
2118         memdev->interleave_ways = 1;
2119         offset += memdev->header.length;
2120
2121         /* mem-region12 (spa/bdw2, dimm2) */
2122         memdev = nfit_buf + offset;
2123         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2124         memdev->header.length = sizeof(*memdev);
2125         memdev->device_handle = handle[2];
2126         memdev->physical_id = 2;
2127         memdev->region_id = 0;
2128         memdev->range_index = 8+1;
2129         memdev->region_index = 2+1;
2130         memdev->region_size = 0;
2131         memdev->region_offset = 0;
2132         memdev->address = 0;
2133         memdev->interleave_index = 0;
2134         memdev->interleave_ways = 1;
2135         offset += memdev->header.length;
2136
2137         /* mem-region13 (spa/dcr3, dimm3) */
2138         memdev = nfit_buf + offset;
2139         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2140         memdev->header.length = sizeof(*memdev);
2141         memdev->device_handle = handle[3];
2142         memdev->physical_id = 3;
2143         memdev->region_id = 0;
2144         memdev->range_index = 9+1;
2145         memdev->region_index = 3+1;
2146         memdev->region_size = 0;
2147         memdev->region_offset = 0;
2148         memdev->address = 0;
2149         memdev->interleave_index = 0;
2150         memdev->interleave_ways = 1;
2151         memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
2152         offset += memdev->header.length;
2153
2154         /* dcr-descriptor0: blk */
2155         dcr = nfit_buf + offset;
2156         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2157         dcr->header.length = sizeof(*dcr);
2158         dcr->region_index = 0+1;
2159         dcr_common_init(dcr);
2160         dcr->serial_number = ~handle[0];
2161         dcr->code = NFIT_FIC_BLK;
2162         dcr->windows = 1;
2163         dcr->window_size = DCR_SIZE;
2164         dcr->command_offset = 0;
2165         dcr->command_size = 8;
2166         dcr->status_offset = 8;
2167         dcr->status_size = 4;
2168         offset += dcr->header.length;
2169
2170         /* dcr-descriptor1: blk */
2171         dcr = nfit_buf + offset;
2172         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2173         dcr->header.length = sizeof(*dcr);
2174         dcr->region_index = 1+1;
2175         dcr_common_init(dcr);
2176         dcr->serial_number = ~handle[1];
2177         dcr->code = NFIT_FIC_BLK;
2178         dcr->windows = 1;
2179         dcr->window_size = DCR_SIZE;
2180         dcr->command_offset = 0;
2181         dcr->command_size = 8;
2182         dcr->status_offset = 8;
2183         dcr->status_size = 4;
2184         offset += dcr->header.length;
2185
2186         /* dcr-descriptor2: blk */
2187         dcr = nfit_buf + offset;
2188         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2189         dcr->header.length = sizeof(*dcr);
2190         dcr->region_index = 2+1;
2191         dcr_common_init(dcr);
2192         dcr->serial_number = ~handle[2];
2193         dcr->code = NFIT_FIC_BLK;
2194         dcr->windows = 1;
2195         dcr->window_size = DCR_SIZE;
2196         dcr->command_offset = 0;
2197         dcr->command_size = 8;
2198         dcr->status_offset = 8;
2199         dcr->status_size = 4;
2200         offset += dcr->header.length;
2201
2202         /* dcr-descriptor3: blk */
2203         dcr = nfit_buf + offset;
2204         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2205         dcr->header.length = sizeof(*dcr);
2206         dcr->region_index = 3+1;
2207         dcr_common_init(dcr);
2208         dcr->serial_number = ~handle[3];
2209         dcr->code = NFIT_FIC_BLK;
2210         dcr->windows = 1;
2211         dcr->window_size = DCR_SIZE;
2212         dcr->command_offset = 0;
2213         dcr->command_size = 8;
2214         dcr->status_offset = 8;
2215         dcr->status_size = 4;
2216         offset += dcr->header.length;
2217
2218         /* dcr-descriptor0: pmem */
2219         dcr = nfit_buf + offset;
2220         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2221         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2222                         window_size);
2223         dcr->region_index = 4+1;
2224         dcr_common_init(dcr);
2225         dcr->serial_number = ~handle[0];
2226         dcr->code = NFIT_FIC_BYTEN;
2227         dcr->windows = 0;
2228         offset += dcr->header.length;
2229
2230         /* dcr-descriptor1: pmem */
2231         dcr = nfit_buf + offset;
2232         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2233         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2234                         window_size);
2235         dcr->region_index = 5+1;
2236         dcr_common_init(dcr);
2237         dcr->serial_number = ~handle[1];
2238         dcr->code = NFIT_FIC_BYTEN;
2239         dcr->windows = 0;
2240         offset += dcr->header.length;
2241
2242         /* dcr-descriptor2: pmem */
2243         dcr = nfit_buf + offset;
2244         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2245         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2246                         window_size);
2247         dcr->region_index = 6+1;
2248         dcr_common_init(dcr);
2249         dcr->serial_number = ~handle[2];
2250         dcr->code = NFIT_FIC_BYTEN;
2251         dcr->windows = 0;
2252         offset += dcr->header.length;
2253
2254         /* dcr-descriptor3: pmem */
2255         dcr = nfit_buf + offset;
2256         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2257         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2258                         window_size);
2259         dcr->region_index = 7+1;
2260         dcr_common_init(dcr);
2261         dcr->serial_number = ~handle[3];
2262         dcr->code = NFIT_FIC_BYTEN;
2263         dcr->windows = 0;
2264         offset += dcr->header.length;
2265
2266         /* bdw0 (spa/dcr0, dimm0) */
2267         bdw = nfit_buf + offset;
2268         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2269         bdw->header.length = sizeof(*bdw);
2270         bdw->region_index = 0+1;
2271         bdw->windows = 1;
2272         bdw->offset = 0;
2273         bdw->size = BDW_SIZE;
2274         bdw->capacity = DIMM_SIZE;
2275         bdw->start_address = 0;
2276         offset += bdw->header.length;
2277
2278         /* bdw1 (spa/dcr1, dimm1) */
2279         bdw = nfit_buf + offset;
2280         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2281         bdw->header.length = sizeof(*bdw);
2282         bdw->region_index = 1+1;
2283         bdw->windows = 1;
2284         bdw->offset = 0;
2285         bdw->size = BDW_SIZE;
2286         bdw->capacity = DIMM_SIZE;
2287         bdw->start_address = 0;
2288         offset += bdw->header.length;
2289
2290         /* bdw2 (spa/dcr2, dimm2) */
2291         bdw = nfit_buf + offset;
2292         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2293         bdw->header.length = sizeof(*bdw);
2294         bdw->region_index = 2+1;
2295         bdw->windows = 1;
2296         bdw->offset = 0;
2297         bdw->size = BDW_SIZE;
2298         bdw->capacity = DIMM_SIZE;
2299         bdw->start_address = 0;
2300         offset += bdw->header.length;
2301
2302         /* bdw3 (spa/dcr3, dimm3) */
2303         bdw = nfit_buf + offset;
2304         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2305         bdw->header.length = sizeof(*bdw);
2306         bdw->region_index = 3+1;
2307         bdw->windows = 1;
2308         bdw->offset = 0;
2309         bdw->size = BDW_SIZE;
2310         bdw->capacity = DIMM_SIZE;
2311         bdw->start_address = 0;
2312         offset += bdw->header.length;
2313
2314         /* flush0 (dimm0) */
2315         flush = nfit_buf + offset;
2316         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2317         flush->header.length = flush_hint_size;
2318         flush->device_handle = handle[0];
2319         flush->hint_count = NUM_HINTS;
2320         for (i = 0; i < NUM_HINTS; i++)
2321                 flush->hint_address[i] = t->flush_dma[0] + i * sizeof(u64);
2322         offset += flush->header.length;
2323
2324         /* flush1 (dimm1) */
2325         flush = nfit_buf + offset;
2326         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2327         flush->header.length = flush_hint_size;
2328         flush->device_handle = handle[1];
2329         flush->hint_count = NUM_HINTS;
2330         for (i = 0; i < NUM_HINTS; i++)
2331                 flush->hint_address[i] = t->flush_dma[1] + i * sizeof(u64);
2332         offset += flush->header.length;
2333
2334         /* flush2 (dimm2) */
2335         flush = nfit_buf + offset;
2336         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2337         flush->header.length = flush_hint_size;
2338         flush->device_handle = handle[2];
2339         flush->hint_count = NUM_HINTS;
2340         for (i = 0; i < NUM_HINTS; i++)
2341                 flush->hint_address[i] = t->flush_dma[2] + i * sizeof(u64);
2342         offset += flush->header.length;
2343
2344         /* flush3 (dimm3) */
2345         flush = nfit_buf + offset;
2346         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2347         flush->header.length = flush_hint_size;
2348         flush->device_handle = handle[3];
2349         flush->hint_count = NUM_HINTS;
2350         for (i = 0; i < NUM_HINTS; i++)
2351                 flush->hint_address[i] = t->flush_dma[3] + i * sizeof(u64);
2352         offset += flush->header.length;
2353
2354         /* platform capabilities */
2355         pcap = nfit_buf + offset;
2356         pcap->header.type = ACPI_NFIT_TYPE_CAPABILITIES;
2357         pcap->header.length = sizeof(*pcap);
2358         pcap->highest_capability = 1;
2359         pcap->capabilities = ACPI_NFIT_CAPABILITY_MEM_FLUSH;
2360         offset += pcap->header.length;
2361
2362         if (t->setup_hotplug) {
2363                 /* dcr-descriptor4: blk */
2364                 dcr = nfit_buf + offset;
2365                 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2366                 dcr->header.length = sizeof(*dcr);
2367                 dcr->region_index = 8+1;
2368                 dcr_common_init(dcr);
2369                 dcr->serial_number = ~handle[4];
2370                 dcr->code = NFIT_FIC_BLK;
2371                 dcr->windows = 1;
2372                 dcr->window_size = DCR_SIZE;
2373                 dcr->command_offset = 0;
2374                 dcr->command_size = 8;
2375                 dcr->status_offset = 8;
2376                 dcr->status_size = 4;
2377                 offset += dcr->header.length;
2378
2379                 /* dcr-descriptor4: pmem */
2380                 dcr = nfit_buf + offset;
2381                 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2382                 dcr->header.length = offsetof(struct acpi_nfit_control_region,
2383                                 window_size);
2384                 dcr->region_index = 9+1;
2385                 dcr_common_init(dcr);
2386                 dcr->serial_number = ~handle[4];
2387                 dcr->code = NFIT_FIC_BYTEN;
2388                 dcr->windows = 0;
2389                 offset += dcr->header.length;
2390
2391                 /* bdw4 (spa/dcr4, dimm4) */
2392                 bdw = nfit_buf + offset;
2393                 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2394                 bdw->header.length = sizeof(*bdw);
2395                 bdw->region_index = 8+1;
2396                 bdw->windows = 1;
2397                 bdw->offset = 0;
2398                 bdw->size = BDW_SIZE;
2399                 bdw->capacity = DIMM_SIZE;
2400                 bdw->start_address = 0;
2401                 offset += bdw->header.length;
2402
2403                 /* spa10 (dcr4) dimm4 */
2404                 spa = nfit_buf + offset;
2405                 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2406                 spa->header.length = sizeof(*spa);
2407                 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
2408                 spa->range_index = 10+1;
2409                 spa->address = t->dcr_dma[4];
2410                 spa->length = DCR_SIZE;
2411                 offset += spa->header.length;
2412
2413                 /*
2414                  * spa11 (single-dimm interleave for hotplug, note storage
2415                  * does not actually alias the related block-data-window
2416                  * regions)
2417                  */
2418                 spa = nfit_buf + offset;
2419                 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2420                 spa->header.length = sizeof(*spa);
2421                 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
2422                 spa->range_index = 11+1;
2423                 spa->address = t->spa_set_dma[2];
2424                 spa->length = SPA0_SIZE;
2425                 offset += spa->header.length;
2426
2427                 /* spa12 (bdw for dcr4) dimm4 */
2428                 spa = nfit_buf + offset;
2429                 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2430                 spa->header.length = sizeof(*spa);
2431                 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
2432                 spa->range_index = 12+1;
2433                 spa->address = t->dimm_dma[4];
2434                 spa->length = DIMM_SIZE;
2435                 offset += spa->header.length;
2436
2437                 /* mem-region14 (spa/dcr4, dimm4) */
2438                 memdev = nfit_buf + offset;
2439                 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2440                 memdev->header.length = sizeof(*memdev);
2441                 memdev->device_handle = handle[4];
2442                 memdev->physical_id = 4;
2443                 memdev->region_id = 0;
2444                 memdev->range_index = 10+1;
2445                 memdev->region_index = 8+1;
2446                 memdev->region_size = 0;
2447                 memdev->region_offset = 0;
2448                 memdev->address = 0;
2449                 memdev->interleave_index = 0;
2450                 memdev->interleave_ways = 1;
2451                 offset += memdev->header.length;
2452
2453                 /* mem-region15 (spa11, dimm4) */
2454                 memdev = nfit_buf + offset;
2455                 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2456                 memdev->header.length = sizeof(*memdev);
2457                 memdev->device_handle = handle[4];
2458                 memdev->physical_id = 4;
2459                 memdev->region_id = 0;
2460                 memdev->range_index = 11+1;
2461                 memdev->region_index = 9+1;
2462                 memdev->region_size = SPA0_SIZE;
2463                 memdev->region_offset = (1ULL << 48);
2464                 memdev->address = 0;
2465                 memdev->interleave_index = 0;
2466                 memdev->interleave_ways = 1;
2467                 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
2468                 offset += memdev->header.length;
2469
2470                 /* mem-region16 (spa/bdw4, dimm4) */
2471                 memdev = nfit_buf + offset;
2472                 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2473                 memdev->header.length = sizeof(*memdev);
2474                 memdev->device_handle = handle[4];
2475                 memdev->physical_id = 4;
2476                 memdev->region_id = 0;
2477                 memdev->range_index = 12+1;
2478                 memdev->region_index = 8+1;
2479                 memdev->region_size = 0;
2480                 memdev->region_offset = 0;
2481                 memdev->address = 0;
2482                 memdev->interleave_index = 0;
2483                 memdev->interleave_ways = 1;
2484                 offset += memdev->header.length;
2485
2486                 /* flush3 (dimm4) */
2487                 flush = nfit_buf + offset;
2488                 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2489                 flush->header.length = flush_hint_size;
2490                 flush->device_handle = handle[4];
2491                 flush->hint_count = NUM_HINTS;
2492                 for (i = 0; i < NUM_HINTS; i++)
2493                         flush->hint_address[i] = t->flush_dma[4]
2494                                 + i * sizeof(u64);
2495                 offset += flush->header.length;
2496
2497                 /* sanity check to make sure we've filled the buffer */
2498                 WARN_ON(offset != t->nfit_size);
2499         }
2500
2501         t->nfit_filled = offset;
2502
2503         post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0],
2504                         SPA0_SIZE);
2505
2506         acpi_desc = &t->acpi_desc;
2507         set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en);
2508         set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2509         set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2510         set_bit(ND_INTEL_SMART, &acpi_desc->dimm_cmd_force_en);
2511         set_bit(ND_INTEL_SMART_THRESHOLD, &acpi_desc->dimm_cmd_force_en);
2512         set_bit(ND_INTEL_SMART_SET_THRESHOLD, &acpi_desc->dimm_cmd_force_en);
2513         set_bit(ND_INTEL_SMART_INJECT, &acpi_desc->dimm_cmd_force_en);
2514         set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
2515         set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
2516         set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
2517         set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
2518         set_bit(ND_CMD_CALL, &acpi_desc->bus_cmd_force_en);
2519         set_bit(NFIT_CMD_TRANSLATE_SPA, &acpi_desc->bus_nfit_cmd_force_en);
2520         set_bit(NFIT_CMD_ARS_INJECT_SET, &acpi_desc->bus_nfit_cmd_force_en);
2521         set_bit(NFIT_CMD_ARS_INJECT_CLEAR, &acpi_desc->bus_nfit_cmd_force_en);
2522         set_bit(NFIT_CMD_ARS_INJECT_GET, &acpi_desc->bus_nfit_cmd_force_en);
2523         set_bit(ND_INTEL_FW_GET_INFO, &acpi_desc->dimm_cmd_force_en);
2524         set_bit(ND_INTEL_FW_START_UPDATE, &acpi_desc->dimm_cmd_force_en);
2525         set_bit(ND_INTEL_FW_SEND_DATA, &acpi_desc->dimm_cmd_force_en);
2526         set_bit(ND_INTEL_FW_FINISH_UPDATE, &acpi_desc->dimm_cmd_force_en);
2527         set_bit(ND_INTEL_FW_FINISH_QUERY, &acpi_desc->dimm_cmd_force_en);
2528         set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en);
2529         set_bit(NVDIMM_INTEL_GET_SECURITY_STATE,
2530                         &acpi_desc->dimm_cmd_force_en);
2531         set_bit(NVDIMM_INTEL_SET_PASSPHRASE, &acpi_desc->dimm_cmd_force_en);
2532         set_bit(NVDIMM_INTEL_DISABLE_PASSPHRASE,
2533                         &acpi_desc->dimm_cmd_force_en);
2534         set_bit(NVDIMM_INTEL_UNLOCK_UNIT, &acpi_desc->dimm_cmd_force_en);
2535         set_bit(NVDIMM_INTEL_FREEZE_LOCK, &acpi_desc->dimm_cmd_force_en);
2536         set_bit(NVDIMM_INTEL_SECURE_ERASE, &acpi_desc->dimm_cmd_force_en);
2537         set_bit(NVDIMM_INTEL_OVERWRITE, &acpi_desc->dimm_cmd_force_en);
2538         set_bit(NVDIMM_INTEL_QUERY_OVERWRITE, &acpi_desc->dimm_cmd_force_en);
2539         set_bit(NVDIMM_INTEL_SET_MASTER_PASSPHRASE,
2540                         &acpi_desc->dimm_cmd_force_en);
2541         set_bit(NVDIMM_INTEL_MASTER_SECURE_ERASE,
2542                         &acpi_desc->dimm_cmd_force_en);
2543 }
2544
2545 static void nfit_test1_setup(struct nfit_test *t)
2546 {
2547         size_t offset;
2548         void *nfit_buf = t->nfit_buf;
2549         struct acpi_nfit_memory_map *memdev;
2550         struct acpi_nfit_control_region *dcr;
2551         struct acpi_nfit_system_address *spa;
2552         struct acpi_nfit_desc *acpi_desc;
2553
2554         offset = 0;
2555         /* spa0 (flat range with no bdw aliasing) */
2556         spa = nfit_buf + offset;
2557         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2558         spa->header.length = sizeof(*spa);
2559         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
2560         spa->range_index = 0+1;
2561         spa->address = t->spa_set_dma[0];
2562         spa->length = SPA2_SIZE;
2563         offset += spa->header.length;
2564
2565         /* virtual cd region */
2566         spa = nfit_buf + offset;
2567         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2568         spa->header.length = sizeof(*spa);
2569         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_VCD), 16);
2570         spa->range_index = 0;
2571         spa->address = t->spa_set_dma[1];
2572         spa->length = SPA_VCD_SIZE;
2573         offset += spa->header.length;
2574
2575         /* mem-region0 (spa0, dimm0) */
2576         memdev = nfit_buf + offset;
2577         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2578         memdev->header.length = sizeof(*memdev);
2579         memdev->device_handle = handle[5];
2580         memdev->physical_id = 0;
2581         memdev->region_id = 0;
2582         memdev->range_index = 0+1;
2583         memdev->region_index = 0+1;
2584         memdev->region_size = SPA2_SIZE;
2585         memdev->region_offset = 0;
2586         memdev->address = 0;
2587         memdev->interleave_index = 0;
2588         memdev->interleave_ways = 1;
2589         memdev->flags = ACPI_NFIT_MEM_SAVE_FAILED | ACPI_NFIT_MEM_RESTORE_FAILED
2590                 | ACPI_NFIT_MEM_FLUSH_FAILED | ACPI_NFIT_MEM_HEALTH_OBSERVED
2591                 | ACPI_NFIT_MEM_NOT_ARMED;
2592         offset += memdev->header.length;
2593
2594         /* dcr-descriptor0 */
2595         dcr = nfit_buf + offset;
2596         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2597         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2598                         window_size);
2599         dcr->region_index = 0+1;
2600         dcr_common_init(dcr);
2601         dcr->serial_number = ~handle[5];
2602         dcr->code = NFIT_FIC_BYTE;
2603         dcr->windows = 0;
2604         offset += dcr->header.length;
2605
2606         memdev = nfit_buf + offset;
2607         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2608         memdev->header.length = sizeof(*memdev);
2609         memdev->device_handle = handle[6];
2610         memdev->physical_id = 0;
2611         memdev->region_id = 0;
2612         memdev->range_index = 0;
2613         memdev->region_index = 0+2;
2614         memdev->region_size = SPA2_SIZE;
2615         memdev->region_offset = 0;
2616         memdev->address = 0;
2617         memdev->interleave_index = 0;
2618         memdev->interleave_ways = 1;
2619         memdev->flags = ACPI_NFIT_MEM_MAP_FAILED;
2620         offset += memdev->header.length;
2621
2622         /* dcr-descriptor1 */
2623         dcr = nfit_buf + offset;
2624         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2625         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2626                         window_size);
2627         dcr->region_index = 0+2;
2628         dcr_common_init(dcr);
2629         dcr->serial_number = ~handle[6];
2630         dcr->code = NFIT_FIC_BYTE;
2631         dcr->windows = 0;
2632         offset += dcr->header.length;
2633
2634         /* sanity check to make sure we've filled the buffer */
2635         WARN_ON(offset != t->nfit_size);
2636
2637         t->nfit_filled = offset;
2638
2639         post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0],
2640                         SPA2_SIZE);
2641
2642         acpi_desc = &t->acpi_desc;
2643         set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
2644         set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
2645         set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
2646         set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
2647         set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en);
2648         set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en);
2649         set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2650         set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2651 }
2652
2653 static int nfit_test_blk_do_io(struct nd_blk_region *ndbr, resource_size_t dpa,
2654                 void *iobuf, u64 len, int rw)
2655 {
2656         struct nfit_blk *nfit_blk = ndbr->blk_provider_data;
2657         struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW];
2658         struct nd_region *nd_region = &ndbr->nd_region;
2659         unsigned int lane;
2660
2661         lane = nd_region_acquire_lane(nd_region);
2662         if (rw)
2663                 memcpy(mmio->addr.base + dpa, iobuf, len);
2664         else {
2665                 memcpy(iobuf, mmio->addr.base + dpa, len);
2666
2667                 /* give us some some coverage of the arch_invalidate_pmem() API */
2668                 arch_invalidate_pmem(mmio->addr.base + dpa, len);
2669         }
2670         nd_region_release_lane(nd_region, lane);
2671
2672         return 0;
2673 }
2674
2675 static unsigned long nfit_ctl_handle;
2676
2677 union acpi_object *result;
2678
2679 static union acpi_object *nfit_test_evaluate_dsm(acpi_handle handle,
2680                 const guid_t *guid, u64 rev, u64 func, union acpi_object *argv4)
2681 {
2682         if (handle != &nfit_ctl_handle)
2683                 return ERR_PTR(-ENXIO);
2684
2685         return result;
2686 }
2687
2688 static int setup_result(void *buf, size_t size)
2689 {
2690         result = kmalloc(sizeof(union acpi_object) + size, GFP_KERNEL);
2691         if (!result)
2692                 return -ENOMEM;
2693         result->package.type = ACPI_TYPE_BUFFER,
2694         result->buffer.pointer = (void *) (result + 1);
2695         result->buffer.length = size;
2696         memcpy(result->buffer.pointer, buf, size);
2697         memset(buf, 0, size);
2698         return 0;
2699 }
2700
2701 static int nfit_ctl_test(struct device *dev)
2702 {
2703         int rc, cmd_rc;
2704         struct nvdimm *nvdimm;
2705         struct acpi_device *adev;
2706         struct nfit_mem *nfit_mem;
2707         struct nd_ars_record *record;
2708         struct acpi_nfit_desc *acpi_desc;
2709         const u64 test_val = 0x0123456789abcdefULL;
2710         unsigned long mask, cmd_size, offset;
2711         union {
2712                 struct nd_cmd_get_config_size cfg_size;
2713                 struct nd_cmd_clear_error clear_err;
2714                 struct nd_cmd_ars_status ars_stat;
2715                 struct nd_cmd_ars_cap ars_cap;
2716                 char buf[sizeof(struct nd_cmd_ars_status)
2717                         + sizeof(struct nd_ars_record)];
2718         } cmds;
2719
2720         adev = devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL);
2721         if (!adev)
2722                 return -ENOMEM;
2723         *adev = (struct acpi_device) {
2724                 .handle = &nfit_ctl_handle,
2725                 .dev = {
2726                         .init_name = "test-adev",
2727                 },
2728         };
2729
2730         acpi_desc = devm_kzalloc(dev, sizeof(*acpi_desc), GFP_KERNEL);
2731         if (!acpi_desc)
2732                 return -ENOMEM;
2733         *acpi_desc = (struct acpi_nfit_desc) {
2734                 .nd_desc = {
2735                         .cmd_mask = 1UL << ND_CMD_ARS_CAP
2736                                 | 1UL << ND_CMD_ARS_START
2737                                 | 1UL << ND_CMD_ARS_STATUS
2738                                 | 1UL << ND_CMD_CLEAR_ERROR
2739                                 | 1UL << ND_CMD_CALL,
2740                         .module = THIS_MODULE,
2741                         .provider_name = "ACPI.NFIT",
2742                         .ndctl = acpi_nfit_ctl,
2743                         .bus_dsm_mask = 1UL << NFIT_CMD_TRANSLATE_SPA
2744                                 | 1UL << NFIT_CMD_ARS_INJECT_SET
2745                                 | 1UL << NFIT_CMD_ARS_INJECT_CLEAR
2746                                 | 1UL << NFIT_CMD_ARS_INJECT_GET,
2747                 },
2748                 .dev = &adev->dev,
2749         };
2750
2751         nfit_mem = devm_kzalloc(dev, sizeof(*nfit_mem), GFP_KERNEL);
2752         if (!nfit_mem)
2753                 return -ENOMEM;
2754
2755         mask = 1UL << ND_CMD_SMART | 1UL << ND_CMD_SMART_THRESHOLD
2756                 | 1UL << ND_CMD_DIMM_FLAGS | 1UL << ND_CMD_GET_CONFIG_SIZE
2757                 | 1UL << ND_CMD_GET_CONFIG_DATA | 1UL << ND_CMD_SET_CONFIG_DATA
2758                 | 1UL << ND_CMD_VENDOR;
2759         *nfit_mem = (struct nfit_mem) {
2760                 .adev = adev,
2761                 .family = NVDIMM_FAMILY_INTEL,
2762                 .dsm_mask = mask,
2763         };
2764
2765         nvdimm = devm_kzalloc(dev, sizeof(*nvdimm), GFP_KERNEL);
2766         if (!nvdimm)
2767                 return -ENOMEM;
2768         *nvdimm = (struct nvdimm) {
2769                 .provider_data = nfit_mem,
2770                 .cmd_mask = mask,
2771                 .dev = {
2772                         .init_name = "test-dimm",
2773                 },
2774         };
2775
2776
2777         /* basic checkout of a typical 'get config size' command */
2778         cmd_size = sizeof(cmds.cfg_size);
2779         cmds.cfg_size = (struct nd_cmd_get_config_size) {
2780                 .status = 0,
2781                 .config_size = SZ_128K,
2782                 .max_xfer = SZ_4K,
2783         };
2784         rc = setup_result(cmds.buf, cmd_size);
2785         if (rc)
2786                 return rc;
2787         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE,
2788                         cmds.buf, cmd_size, &cmd_rc);
2789
2790         if (rc < 0 || cmd_rc || cmds.cfg_size.status != 0
2791                         || cmds.cfg_size.config_size != SZ_128K
2792                         || cmds.cfg_size.max_xfer != SZ_4K) {
2793                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2794                                 __func__, __LINE__, rc, cmd_rc);
2795                 return -EIO;
2796         }
2797
2798
2799         /* test ars_status with zero output */
2800         cmd_size = offsetof(struct nd_cmd_ars_status, address);
2801         cmds.ars_stat = (struct nd_cmd_ars_status) {
2802                 .out_length = 0,
2803         };
2804         rc = setup_result(cmds.buf, cmd_size);
2805         if (rc)
2806                 return rc;
2807         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
2808                         cmds.buf, cmd_size, &cmd_rc);
2809
2810         if (rc < 0 || cmd_rc) {
2811                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2812                                 __func__, __LINE__, rc, cmd_rc);
2813                 return -EIO;
2814         }
2815
2816
2817         /* test ars_cap with benign extended status */
2818         cmd_size = sizeof(cmds.ars_cap);
2819         cmds.ars_cap = (struct nd_cmd_ars_cap) {
2820                 .status = ND_ARS_PERSISTENT << 16,
2821         };
2822         offset = offsetof(struct nd_cmd_ars_cap, status);
2823         rc = setup_result(cmds.buf + offset, cmd_size - offset);
2824         if (rc)
2825                 return rc;
2826         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_CAP,
2827                         cmds.buf, cmd_size, &cmd_rc);
2828
2829         if (rc < 0 || cmd_rc) {
2830                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2831                                 __func__, __LINE__, rc, cmd_rc);
2832                 return -EIO;
2833         }
2834
2835
2836         /* test ars_status with 'status' trimmed from 'out_length' */
2837         cmd_size = sizeof(cmds.ars_stat) + sizeof(struct nd_ars_record);
2838         cmds.ars_stat = (struct nd_cmd_ars_status) {
2839                 .out_length = cmd_size - 4,
2840         };
2841         record = &cmds.ars_stat.records[0];
2842         *record = (struct nd_ars_record) {
2843                 .length = test_val,
2844         };
2845         rc = setup_result(cmds.buf, cmd_size);
2846         if (rc)
2847                 return rc;
2848         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
2849                         cmds.buf, cmd_size, &cmd_rc);
2850
2851         if (rc < 0 || cmd_rc || record->length != test_val) {
2852                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2853                                 __func__, __LINE__, rc, cmd_rc);
2854                 return -EIO;
2855         }
2856
2857
2858         /* test ars_status with 'Output (Size)' including 'status' */
2859         cmd_size = sizeof(cmds.ars_stat) + sizeof(struct nd_ars_record);
2860         cmds.ars_stat = (struct nd_cmd_ars_status) {
2861                 .out_length = cmd_size,
2862         };
2863         record = &cmds.ars_stat.records[0];
2864         *record = (struct nd_ars_record) {
2865                 .length = test_val,
2866         };
2867         rc = setup_result(cmds.buf, cmd_size);
2868         if (rc)
2869                 return rc;
2870         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
2871                         cmds.buf, cmd_size, &cmd_rc);
2872
2873         if (rc < 0 || cmd_rc || record->length != test_val) {
2874                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2875                                 __func__, __LINE__, rc, cmd_rc);
2876                 return -EIO;
2877         }
2878
2879
2880         /* test extended status for get_config_size results in failure */
2881         cmd_size = sizeof(cmds.cfg_size);
2882         cmds.cfg_size = (struct nd_cmd_get_config_size) {
2883                 .status = 1 << 16,
2884         };
2885         rc = setup_result(cmds.buf, cmd_size);
2886         if (rc)
2887                 return rc;
2888         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE,
2889                         cmds.buf, cmd_size, &cmd_rc);
2890
2891         if (rc < 0 || cmd_rc >= 0) {
2892                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2893                                 __func__, __LINE__, rc, cmd_rc);
2894                 return -EIO;
2895         }
2896
2897         /* test clear error */
2898         cmd_size = sizeof(cmds.clear_err);
2899         cmds.clear_err = (struct nd_cmd_clear_error) {
2900                 .length = 512,
2901                 .cleared = 512,
2902         };
2903         rc = setup_result(cmds.buf, cmd_size);
2904         if (rc)
2905                 return rc;
2906         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_CLEAR_ERROR,
2907                         cmds.buf, cmd_size, &cmd_rc);
2908         if (rc < 0 || cmd_rc) {
2909                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2910                                 __func__, __LINE__, rc, cmd_rc);
2911                 return -EIO;
2912         }
2913
2914         return 0;
2915 }
2916
2917 static int nfit_test_probe(struct platform_device *pdev)
2918 {
2919         struct nvdimm_bus_descriptor *nd_desc;
2920         struct acpi_nfit_desc *acpi_desc;
2921         struct device *dev = &pdev->dev;
2922         struct nfit_test *nfit_test;
2923         struct nfit_mem *nfit_mem;
2924         union acpi_object *obj;
2925         int rc;
2926
2927         if (strcmp(dev_name(&pdev->dev), "nfit_test.0") == 0) {
2928                 rc = nfit_ctl_test(&pdev->dev);
2929                 if (rc)
2930                         return rc;
2931         }
2932
2933         nfit_test = to_nfit_test(&pdev->dev);
2934
2935         /* common alloc */
2936         if (nfit_test->num_dcr) {
2937                 int num = nfit_test->num_dcr;
2938
2939                 nfit_test->dimm = devm_kcalloc(dev, num, sizeof(void *),
2940                                 GFP_KERNEL);
2941                 nfit_test->dimm_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
2942                                 GFP_KERNEL);
2943                 nfit_test->flush = devm_kcalloc(dev, num, sizeof(void *),
2944                                 GFP_KERNEL);
2945                 nfit_test->flush_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
2946                                 GFP_KERNEL);
2947                 nfit_test->label = devm_kcalloc(dev, num, sizeof(void *),
2948                                 GFP_KERNEL);
2949                 nfit_test->label_dma = devm_kcalloc(dev, num,
2950                                 sizeof(dma_addr_t), GFP_KERNEL);
2951                 nfit_test->dcr = devm_kcalloc(dev, num,
2952                                 sizeof(struct nfit_test_dcr *), GFP_KERNEL);
2953                 nfit_test->dcr_dma = devm_kcalloc(dev, num,
2954                                 sizeof(dma_addr_t), GFP_KERNEL);
2955                 nfit_test->smart = devm_kcalloc(dev, num,
2956                                 sizeof(struct nd_intel_smart), GFP_KERNEL);
2957                 nfit_test->smart_threshold = devm_kcalloc(dev, num,
2958                                 sizeof(struct nd_intel_smart_threshold),
2959                                 GFP_KERNEL);
2960                 nfit_test->fw = devm_kcalloc(dev, num,
2961                                 sizeof(struct nfit_test_fw), GFP_KERNEL);
2962                 if (nfit_test->dimm && nfit_test->dimm_dma && nfit_test->label
2963                                 && nfit_test->label_dma && nfit_test->dcr
2964                                 && nfit_test->dcr_dma && nfit_test->flush
2965                                 && nfit_test->flush_dma
2966                                 && nfit_test->fw)
2967                         /* pass */;
2968                 else
2969                         return -ENOMEM;
2970         }
2971
2972         if (nfit_test->num_pm) {
2973                 int num = nfit_test->num_pm;
2974
2975                 nfit_test->spa_set = devm_kcalloc(dev, num, sizeof(void *),
2976                                 GFP_KERNEL);
2977                 nfit_test->spa_set_dma = devm_kcalloc(dev, num,
2978                                 sizeof(dma_addr_t), GFP_KERNEL);
2979                 if (nfit_test->spa_set && nfit_test->spa_set_dma)
2980                         /* pass */;
2981                 else
2982                         return -ENOMEM;
2983         }
2984
2985         /* per-nfit specific alloc */
2986         if (nfit_test->alloc(nfit_test))
2987                 return -ENOMEM;
2988
2989         nfit_test->setup(nfit_test);
2990         acpi_desc = &nfit_test->acpi_desc;
2991         acpi_nfit_desc_init(acpi_desc, &pdev->dev);
2992         acpi_desc->blk_do_io = nfit_test_blk_do_io;
2993         nd_desc = &acpi_desc->nd_desc;
2994         nd_desc->provider_name = NULL;
2995         nd_desc->module = THIS_MODULE;
2996         nd_desc->ndctl = nfit_test_ctl;
2997
2998         rc = acpi_nfit_init(acpi_desc, nfit_test->nfit_buf,
2999                         nfit_test->nfit_filled);
3000         if (rc)
3001                 return rc;
3002
3003         rc = devm_add_action_or_reset(&pdev->dev, acpi_nfit_shutdown, acpi_desc);
3004         if (rc)
3005                 return rc;
3006
3007         if (nfit_test->setup != nfit_test0_setup)
3008                 return 0;
3009
3010         nfit_test->setup_hotplug = 1;
3011         nfit_test->setup(nfit_test);
3012
3013         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3014         if (!obj)
3015                 return -ENOMEM;
3016         obj->type = ACPI_TYPE_BUFFER;
3017         obj->buffer.length = nfit_test->nfit_size;
3018         obj->buffer.pointer = nfit_test->nfit_buf;
3019         *(nfit_test->_fit) = obj;
3020         __acpi_nfit_notify(&pdev->dev, nfit_test, 0x80);
3021
3022         /* associate dimm devices with nfit_mem data for notification testing */
3023         mutex_lock(&acpi_desc->init_mutex);
3024         list_for_each_entry(nfit_mem, &acpi_desc->dimms, list) {
3025                 u32 nfit_handle = __to_nfit_memdev(nfit_mem)->device_handle;
3026                 int i;
3027
3028                 for (i = 0; i < ARRAY_SIZE(handle); i++)
3029                         if (nfit_handle == handle[i])
3030                                 dev_set_drvdata(nfit_test->dimm_dev[i],
3031                                                 nfit_mem);
3032         }
3033         mutex_unlock(&acpi_desc->init_mutex);
3034
3035         return 0;
3036 }
3037
3038 static int nfit_test_remove(struct platform_device *pdev)
3039 {
3040         return 0;
3041 }
3042
3043 static void nfit_test_release(struct device *dev)
3044 {
3045         struct nfit_test *nfit_test = to_nfit_test(dev);
3046
3047         kfree(nfit_test);
3048 }
3049
3050 static const struct platform_device_id nfit_test_id[] = {
3051         { KBUILD_MODNAME },
3052         { },
3053 };
3054
3055 static struct platform_driver nfit_test_driver = {
3056         .probe = nfit_test_probe,
3057         .remove = nfit_test_remove,
3058         .driver = {
3059                 .name = KBUILD_MODNAME,
3060         },
3061         .id_table = nfit_test_id,
3062 };
3063
3064 static char mcsafe_buf[PAGE_SIZE] __attribute__((__aligned__(PAGE_SIZE)));
3065
3066 enum INJECT {
3067         INJECT_NONE,
3068         INJECT_SRC,
3069         INJECT_DST,
3070 };
3071
3072 static void mcsafe_test_init(char *dst, char *src, size_t size)
3073 {
3074         size_t i;
3075
3076         memset(dst, 0xff, size);
3077         for (i = 0; i < size; i++)
3078                 src[i] = (char) i;
3079 }
3080
3081 static bool mcsafe_test_validate(unsigned char *dst, unsigned char *src,
3082                 size_t size, unsigned long rem)
3083 {
3084         size_t i;
3085
3086         for (i = 0; i < size - rem; i++)
3087                 if (dst[i] != (unsigned char) i) {
3088                         pr_info_once("%s:%d: offset: %zd got: %#x expect: %#x\n",
3089                                         __func__, __LINE__, i, dst[i],
3090                                         (unsigned char) i);
3091                         return false;
3092                 }
3093         for (i = size - rem; i < size; i++)
3094                 if (dst[i] != 0xffU) {
3095                         pr_info_once("%s:%d: offset: %zd got: %#x expect: 0xff\n",
3096                                         __func__, __LINE__, i, dst[i]);
3097                         return false;
3098                 }
3099         return true;
3100 }
3101
3102 void mcsafe_test(void)
3103 {
3104         char *inject_desc[] = { "none", "source", "destination" };
3105         enum INJECT inj;
3106
3107         if (IS_ENABLED(CONFIG_MCSAFE_TEST)) {
3108                 pr_info("%s: run...\n", __func__);
3109         } else {
3110                 pr_info("%s: disabled, skip.\n", __func__);
3111                 return;
3112         }
3113
3114         for (inj = INJECT_NONE; inj <= INJECT_DST; inj++) {
3115                 int i;
3116
3117                 pr_info("%s: inject: %s\n", __func__, inject_desc[inj]);
3118                 for (i = 0; i < 512; i++) {
3119                         unsigned long expect, rem;
3120                         void *src, *dst;
3121                         bool valid;
3122
3123                         switch (inj) {
3124                         case INJECT_NONE:
3125                                 mcsafe_inject_src(NULL);
3126                                 mcsafe_inject_dst(NULL);
3127                                 dst = &mcsafe_buf[2048];
3128                                 src = &mcsafe_buf[1024 - i];
3129                                 expect = 0;
3130                                 break;
3131                         case INJECT_SRC:
3132                                 mcsafe_inject_src(&mcsafe_buf[1024]);
3133                                 mcsafe_inject_dst(NULL);
3134                                 dst = &mcsafe_buf[2048];
3135                                 src = &mcsafe_buf[1024 - i];
3136                                 expect = 512 - i;
3137                                 break;
3138                         case INJECT_DST:
3139                                 mcsafe_inject_src(NULL);
3140                                 mcsafe_inject_dst(&mcsafe_buf[2048]);
3141                                 dst = &mcsafe_buf[2048 - i];
3142                                 src = &mcsafe_buf[1024];
3143                                 expect = 512 - i;
3144                                 break;
3145                         }
3146
3147                         mcsafe_test_init(dst, src, 512);
3148                         rem = __memcpy_mcsafe(dst, src, 512);
3149                         valid = mcsafe_test_validate(dst, src, 512, expect);
3150                         if (rem == expect && valid)
3151                                 continue;
3152                         pr_info("%s: copy(%#lx, %#lx, %d) off: %d rem: %ld %s expect: %ld\n",
3153                                         __func__,
3154                                         ((unsigned long) dst) & ~PAGE_MASK,
3155                                         ((unsigned long ) src) & ~PAGE_MASK,
3156                                         512, i, rem, valid ? "valid" : "bad",
3157                                         expect);
3158                 }
3159         }
3160
3161         mcsafe_inject_src(NULL);
3162         mcsafe_inject_dst(NULL);
3163 }
3164
3165 static __init int nfit_test_init(void)
3166 {
3167         int rc, i;
3168
3169         pmem_test();
3170         libnvdimm_test();
3171         acpi_nfit_test();
3172         device_dax_test();
3173         mcsafe_test();
3174
3175         nfit_test_setup(nfit_test_lookup, nfit_test_evaluate_dsm);
3176
3177         nfit_wq = create_singlethread_workqueue("nfit");
3178         if (!nfit_wq)
3179                 return -ENOMEM;
3180
3181         nfit_test_dimm = class_create(THIS_MODULE, "nfit_test_dimm");
3182         if (IS_ERR(nfit_test_dimm)) {
3183                 rc = PTR_ERR(nfit_test_dimm);
3184                 goto err_register;
3185         }
3186
3187         nfit_pool = gen_pool_create(ilog2(SZ_4M), NUMA_NO_NODE);
3188         if (!nfit_pool) {
3189                 rc = -ENOMEM;
3190                 goto err_register;
3191         }
3192
3193         if (gen_pool_add(nfit_pool, SZ_4G, SZ_4G, NUMA_NO_NODE)) {
3194                 rc = -ENOMEM;
3195                 goto err_register;
3196         }
3197
3198         for (i = 0; i < NUM_NFITS; i++) {
3199                 struct nfit_test *nfit_test;
3200                 struct platform_device *pdev;
3201
3202                 nfit_test = kzalloc(sizeof(*nfit_test), GFP_KERNEL);
3203                 if (!nfit_test) {
3204                         rc = -ENOMEM;
3205                         goto err_register;
3206                 }
3207                 INIT_LIST_HEAD(&nfit_test->resources);
3208                 badrange_init(&nfit_test->badrange);
3209                 switch (i) {
3210                 case 0:
3211                         nfit_test->num_pm = NUM_PM;
3212                         nfit_test->dcr_idx = 0;
3213                         nfit_test->num_dcr = NUM_DCR;
3214                         nfit_test->alloc = nfit_test0_alloc;
3215                         nfit_test->setup = nfit_test0_setup;
3216                         break;
3217                 case 1:
3218                         nfit_test->num_pm = 2;
3219                         nfit_test->dcr_idx = NUM_DCR;
3220                         nfit_test->num_dcr = 2;
3221                         nfit_test->alloc = nfit_test1_alloc;
3222                         nfit_test->setup = nfit_test1_setup;
3223                         break;
3224                 default:
3225                         rc = -EINVAL;
3226                         goto err_register;
3227                 }
3228                 pdev = &nfit_test->pdev;
3229                 pdev->name = KBUILD_MODNAME;
3230                 pdev->id = i;
3231                 pdev->dev.release = nfit_test_release;
3232                 rc = platform_device_register(pdev);
3233                 if (rc) {
3234                         put_device(&pdev->dev);
3235                         goto err_register;
3236                 }
3237                 get_device(&pdev->dev);
3238
3239                 rc = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3240                 if (rc)
3241                         goto err_register;
3242
3243                 instances[i] = nfit_test;
3244                 INIT_WORK(&nfit_test->work, uc_error_notify);
3245         }
3246
3247         rc = platform_driver_register(&nfit_test_driver);
3248         if (rc)
3249                 goto err_register;
3250         return 0;
3251
3252  err_register:
3253         if (nfit_pool)
3254                 gen_pool_destroy(nfit_pool);
3255
3256         destroy_workqueue(nfit_wq);
3257         for (i = 0; i < NUM_NFITS; i++)
3258                 if (instances[i])
3259                         platform_device_unregister(&instances[i]->pdev);
3260         nfit_test_teardown();
3261         for (i = 0; i < NUM_NFITS; i++)
3262                 if (instances[i])
3263                         put_device(&instances[i]->pdev.dev);
3264
3265         return rc;
3266 }
3267
3268 static __exit void nfit_test_exit(void)
3269 {
3270         int i;
3271
3272         flush_workqueue(nfit_wq);
3273         destroy_workqueue(nfit_wq);
3274         for (i = 0; i < NUM_NFITS; i++)
3275                 platform_device_unregister(&instances[i]->pdev);
3276         platform_driver_unregister(&nfit_test_driver);
3277         nfit_test_teardown();
3278
3279         gen_pool_destroy(nfit_pool);
3280
3281         for (i = 0; i < NUM_NFITS; i++)
3282                 put_device(&instances[i]->pdev.dev);
3283         class_destroy(nfit_test_dimm);
3284 }
3285
3286 module_init(nfit_test_init);
3287 module_exit(nfit_test_exit);
3288 MODULE_LICENSE("GPL v2");
3289 MODULE_AUTHOR("Intel Corporation");