1 // SPDX-License-Identifier: GPL-2.0-only
3 * turbostat -- show CPU frequency and C-state residency
4 * on modern Intel and AMD processors.
6 * Copyright (c) 2013 Intel Corporation.
7 * Len Brown <len.brown@intel.com>
12 #include INTEL_FAMILY_HEADER
17 #include <sys/types.h>
20 #include <sys/select.h>
21 #include <sys/resource.h>
33 #include <sys/capability.h>
37 char *proc_stat = "/proc/stat";
40 struct timeval interval_tv = {5, 0};
41 struct timespec interval_ts = {5, 0};
42 unsigned int num_iterations;
46 unsigned int sums_need_wide_columns;
47 unsigned int rapl_joules;
48 unsigned int summary_only;
49 unsigned int list_header_only;
50 unsigned int dump_only;
51 unsigned int do_snb_cstates;
52 unsigned int do_knl_cstates;
53 unsigned int do_slm_cstates;
54 unsigned int use_c1_residency_msr;
55 unsigned int has_aperf;
57 unsigned int do_irtl_snb;
58 unsigned int do_irtl_hsw;
59 unsigned int units = 1000000; /* MHz etc */
60 unsigned int genuine_intel;
61 unsigned int authentic_amd;
62 unsigned int hygon_genuine;
63 unsigned int max_level, max_extended_level;
64 unsigned int has_invariant_tsc;
65 unsigned int do_nhm_platform_info;
66 unsigned int no_MSR_MISC_PWR_MGMT;
67 unsigned int aperf_mperf_multiplier = 1;
70 unsigned int has_base_hz;
71 double tsc_tweak = 1.0;
72 unsigned int show_pkg_only;
73 unsigned int show_core_only;
74 char *output_buffer, *outp;
78 unsigned long long gfx_cur_rc6_ms;
79 unsigned long long cpuidle_cur_cpu_lpi_us;
80 unsigned long long cpuidle_cur_sys_lpi_us;
81 unsigned int gfx_cur_mhz;
82 unsigned int tcc_activation_temp;
83 unsigned int tcc_activation_temp_override;
84 double rapl_power_units, rapl_time_units;
85 double rapl_dram_energy_units, rapl_energy_units;
86 double rapl_joule_counter_range;
87 unsigned int do_core_perf_limit_reasons;
88 unsigned int has_automatic_cstate_conversion;
89 unsigned int do_gfx_perf_limit_reasons;
90 unsigned int do_ring_perf_limit_reasons;
91 unsigned int crystal_hz;
92 unsigned long long tsc_hz;
94 double discover_bclk(unsigned int family, unsigned int model);
95 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
96 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */
97 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */
98 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */
99 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */
100 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */
101 unsigned int has_misc_feature_control;
102 unsigned int first_counter_read = 1;
105 #define RAPL_PKG (1 << 0)
106 /* 0x610 MSR_PKG_POWER_LIMIT */
107 /* 0x611 MSR_PKG_ENERGY_STATUS */
108 #define RAPL_PKG_PERF_STATUS (1 << 1)
109 /* 0x613 MSR_PKG_PERF_STATUS */
110 #define RAPL_PKG_POWER_INFO (1 << 2)
111 /* 0x614 MSR_PKG_POWER_INFO */
113 #define RAPL_DRAM (1 << 3)
114 /* 0x618 MSR_DRAM_POWER_LIMIT */
115 /* 0x619 MSR_DRAM_ENERGY_STATUS */
116 #define RAPL_DRAM_PERF_STATUS (1 << 4)
117 /* 0x61b MSR_DRAM_PERF_STATUS */
118 #define RAPL_DRAM_POWER_INFO (1 << 5)
119 /* 0x61c MSR_DRAM_POWER_INFO */
121 #define RAPL_CORES_POWER_LIMIT (1 << 6)
122 /* 0x638 MSR_PP0_POWER_LIMIT */
123 #define RAPL_CORE_POLICY (1 << 7)
124 /* 0x63a MSR_PP0_POLICY */
126 #define RAPL_GFX (1 << 8)
127 /* 0x640 MSR_PP1_POWER_LIMIT */
128 /* 0x641 MSR_PP1_ENERGY_STATUS */
129 /* 0x642 MSR_PP1_POLICY */
131 #define RAPL_CORES_ENERGY_STATUS (1 << 9)
132 /* 0x639 MSR_PP0_ENERGY_STATUS */
133 #define RAPL_PER_CORE_ENERGY (1 << 10)
134 /* Indicates cores energy collection is per-core,
135 * not per-package. */
136 #define RAPL_AMD_F17H (1 << 11)
137 /* 0xc0010299 MSR_RAPL_PWR_UNIT */
138 /* 0xc001029a MSR_CORE_ENERGY_STAT */
139 /* 0xc001029b MSR_PKG_ENERGY_STAT */
140 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT)
141 #define TJMAX_DEFAULT 100
143 /* MSRs that are not yet in the kernel-provided header. */
144 #define MSR_RAPL_PWR_UNIT 0xc0010299
145 #define MSR_CORE_ENERGY_STAT 0xc001029a
146 #define MSR_PKG_ENERGY_STAT 0xc001029b
148 #define MAX(a, b) ((a) > (b) ? (a) : (b))
151 * buffer size used by sscanf() for added column names
152 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters
154 #define NAME_BYTES 20
155 #define PATH_BYTES 128
160 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */
161 cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset;
162 size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size;
163 #define MAX_ADDED_COUNTERS 8
164 #define MAX_ADDED_THREAD_COUNTERS 24
165 #define BITMASK_SIZE 32
168 struct timeval tv_begin;
169 struct timeval tv_end;
170 struct timeval tv_delta;
171 unsigned long long tsc;
172 unsigned long long aperf;
173 unsigned long long mperf;
174 unsigned long long c1;
175 unsigned long long irq_count;
176 unsigned int smi_count;
178 unsigned int apic_id;
179 unsigned int x2apic_id;
181 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2
182 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4
183 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS];
184 } *thread_even, *thread_odd;
187 unsigned long long c3;
188 unsigned long long c6;
189 unsigned long long c7;
190 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */
191 unsigned int core_temp_c;
192 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */
193 unsigned int core_id;
194 unsigned long long counter[MAX_ADDED_COUNTERS];
195 } *core_even, *core_odd;
198 unsigned long long pc2;
199 unsigned long long pc3;
200 unsigned long long pc6;
201 unsigned long long pc7;
202 unsigned long long pc8;
203 unsigned long long pc9;
204 unsigned long long pc10;
205 unsigned long long cpu_lpi;
206 unsigned long long sys_lpi;
207 unsigned long long pkg_wtd_core_c0;
208 unsigned long long pkg_any_core_c0;
209 unsigned long long pkg_any_gfxe_c0;
210 unsigned long long pkg_both_core_gfxe_c0;
211 long long gfx_rc6_ms;
212 unsigned int gfx_mhz;
213 unsigned int package_id;
214 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */
215 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */
216 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */
217 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */
218 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */
219 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */
220 unsigned int pkg_temp_c;
221 unsigned long long counter[MAX_ADDED_COUNTERS];
222 } *package_even, *package_odd;
224 #define ODD_COUNTERS thread_odd, core_odd, package_odd
225 #define EVEN_COUNTERS thread_even, core_even, package_even
227 #define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \
230 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \
231 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \
232 ((core_no) * topo.threads_per_core) + \
235 #define GET_CORE(core_base, core_no, node_no, pkg_no) \
237 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \
238 ((node_no) * topo.cores_per_node) + \
242 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no)
244 enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE};
245 enum counter_type {COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC};
246 enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT};
249 unsigned int msr_num;
250 char name[NAME_BYTES];
251 char path[PATH_BYTES];
253 enum counter_type type;
254 enum counter_format format;
255 struct msr_counter *next;
257 #define FLAGS_HIDE (1 << 0)
258 #define FLAGS_SHOW (1 << 1)
259 #define SYSFS_PERCPU (1 << 1)
262 struct sys_counters {
263 unsigned int added_thread_counters;
264 unsigned int added_core_counters;
265 unsigned int added_package_counters;
266 struct msr_counter *tp;
267 struct msr_counter *cp;
268 struct msr_counter *pp;
271 struct system_summary {
272 struct thread_data threads;
273 struct core_data cores;
274 struct pkg_data packages;
277 struct cpu_topology {
278 int physical_package_id;
281 int physical_node_id;
282 int logical_node_id; /* 0-based count within the package */
283 int physical_core_id;
285 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */
297 int threads_per_core;
300 struct timeval tv_even, tv_odd, tv_delta;
302 int *irq_column_2_cpu; /* /proc/interrupts column numbers */
303 int *irqs_per_cpu; /* indexed by cpu_num */
305 void setup_all_buffers(void);
308 char *sys_lpi_file_sysfs = "/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us";
309 char *sys_lpi_file_debugfs = "/sys/kernel/debug/pmc_core/slp_s0_residency_usec";
311 int cpu_is_not_present(int cpu)
313 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set);
316 * run func(thread, core, package) in topology order
317 * skip non-present cpus
320 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *),
321 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base)
323 int retval, pkg_no, core_no, thread_no, node_no;
325 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
326 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) {
327 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) {
328 for (thread_no = 0; thread_no <
329 topo.threads_per_core; ++thread_no) {
330 struct thread_data *t;
334 t = GET_THREAD(thread_base, thread_no,
338 if (cpu_is_not_present(t->cpu_id))
341 c = GET_CORE(core_base, core_no,
343 p = GET_PKG(pkg_base, pkg_no);
345 retval = func(t, c, p);
355 int cpu_migrate(int cpu)
357 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
358 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set);
359 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1)
364 int get_msr_fd(int cpu)
374 sprintf(pathname, "/dev/cpu/%d/msr", cpu);
375 fd = open(pathname, O_RDONLY);
377 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname);
384 int get_msr(int cpu, off_t offset, unsigned long long *msr)
388 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset);
390 if (retval != sizeof *msr)
391 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset);
397 * This list matches the column headers, except
398 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time
399 * 2. Core and CPU are moved to the end, we can't have strings that contain them
400 * matching on them for --show and --hide.
402 struct msr_counter bic[] = {
404 { 0x0, "Time_Of_Day_Seconds" },
412 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL},
456 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
457 #define BIC_USEC (1ULL << 0)
458 #define BIC_TOD (1ULL << 1)
459 #define BIC_Package (1ULL << 2)
460 #define BIC_Node (1ULL << 3)
461 #define BIC_Avg_MHz (1ULL << 4)
462 #define BIC_Busy (1ULL << 5)
463 #define BIC_Bzy_MHz (1ULL << 6)
464 #define BIC_TSC_MHz (1ULL << 7)
465 #define BIC_IRQ (1ULL << 8)
466 #define BIC_SMI (1ULL << 9)
467 #define BIC_sysfs (1ULL << 10)
468 #define BIC_CPU_c1 (1ULL << 11)
469 #define BIC_CPU_c3 (1ULL << 12)
470 #define BIC_CPU_c6 (1ULL << 13)
471 #define BIC_CPU_c7 (1ULL << 14)
472 #define BIC_ThreadC (1ULL << 15)
473 #define BIC_CoreTmp (1ULL << 16)
474 #define BIC_CoreCnt (1ULL << 17)
475 #define BIC_PkgTmp (1ULL << 18)
476 #define BIC_GFX_rc6 (1ULL << 19)
477 #define BIC_GFXMHz (1ULL << 20)
478 #define BIC_Pkgpc2 (1ULL << 21)
479 #define BIC_Pkgpc3 (1ULL << 22)
480 #define BIC_Pkgpc6 (1ULL << 23)
481 #define BIC_Pkgpc7 (1ULL << 24)
482 #define BIC_Pkgpc8 (1ULL << 25)
483 #define BIC_Pkgpc9 (1ULL << 26)
484 #define BIC_Pkgpc10 (1ULL << 27)
485 #define BIC_CPU_LPI (1ULL << 28)
486 #define BIC_SYS_LPI (1ULL << 29)
487 #define BIC_PkgWatt (1ULL << 30)
488 #define BIC_CorWatt (1ULL << 31)
489 #define BIC_GFXWatt (1ULL << 32)
490 #define BIC_PkgCnt (1ULL << 33)
491 #define BIC_RAMWatt (1ULL << 34)
492 #define BIC_PKG__ (1ULL << 35)
493 #define BIC_RAM__ (1ULL << 36)
494 #define BIC_Pkg_J (1ULL << 37)
495 #define BIC_Cor_J (1ULL << 38)
496 #define BIC_GFX_J (1ULL << 39)
497 #define BIC_RAM_J (1ULL << 40)
498 #define BIC_Mod_c6 (1ULL << 41)
499 #define BIC_Totl_c0 (1ULL << 42)
500 #define BIC_Any_c0 (1ULL << 43)
501 #define BIC_GFX_c0 (1ULL << 44)
502 #define BIC_CPUGFX (1ULL << 45)
503 #define BIC_Core (1ULL << 46)
504 #define BIC_CPU (1ULL << 47)
505 #define BIC_APIC (1ULL << 48)
506 #define BIC_X2APIC (1ULL << 49)
507 #define BIC_Die (1ULL << 50)
509 #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC)
511 unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT);
512 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC;
514 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME)
515 #define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME)
516 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME)
517 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT)
518 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT)
521 #define MAX_DEFERRED 16
522 char *deferred_skip_names[MAX_DEFERRED];
523 int deferred_skip_index;
526 * HIDE_LIST - hide this list of counters, show the rest [default]
527 * SHOW_LIST - show this list of counters, hide the rest
529 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST;
534 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n"
536 "Turbostat forks the specified COMMAND and prints statistics\n"
537 "when COMMAND completes.\n"
538 "If no COMMAND is specified, turbostat wakes every 5-seconds\n"
539 "to print statistics, until interrupted.\n"
540 " -a, --add add a counter\n"
541 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n"
542 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n"
543 " {core | package | j,k,l..m,n-p }\n"
544 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n"
545 " -D, --Dump displays the raw counter values\n"
546 " -e, --enable [all | column]\n"
547 " shows all or the specified disabled column\n"
548 " -H, --hide [column|column,column,...]\n"
549 " hide the specified column(s)\n"
550 " -i, --interval sec.subsec\n"
551 " Override default 5-second measurement interval\n"
552 " -J, --Joules displays energy in Joules instead of Watts\n"
553 " -l, --list list column headers only\n"
554 " -n, --num_iterations num\n"
555 " number of the measurement iterations\n"
557 " create or truncate \"file\" for all output\n"
558 " -q, --quiet skip decoding system configuration header\n"
559 " -s, --show [column|column,column,...]\n"
560 " show only the specified column(s)\n"
562 " limits output to 1-line system summary per interval\n"
563 " -T, --TCC temperature\n"
564 " sets the Thermal Control Circuit temperature in\n"
566 " -h, --help print this help message\n"
567 " -v, --version print version information\n"
569 "For more help, run \"man turbostat\"\n");
574 * for all the strings in comma separate name_list,
575 * set the approprate bit in return value.
577 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode)
580 unsigned long long retval = 0;
585 comma = strchr(name_list, ',');
590 if (!strcmp(name_list, "all"))
593 for (i = 0; i < MAX_BIC; ++i) {
594 if (!strcmp(name_list, bic[i].name)) {
595 retval |= (1ULL << i);
600 if (mode == SHOW_LIST) {
601 fprintf(stderr, "Invalid counter name: %s\n", name_list);
604 deferred_skip_names[deferred_skip_index++] = name_list;
606 fprintf(stderr, "deferred \"%s\"\n", name_list);
607 if (deferred_skip_index >= MAX_DEFERRED) {
608 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n",
609 MAX_DEFERRED, name_list);
624 void print_header(char *delim)
626 struct msr_counter *mp;
629 if (DO_BIC(BIC_USEC))
630 outp += sprintf(outp, "%susec", (printed++ ? delim : ""));
632 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : ""));
633 if (DO_BIC(BIC_Package))
634 outp += sprintf(outp, "%sPackage", (printed++ ? delim : ""));
636 outp += sprintf(outp, "%sDie", (printed++ ? delim : ""));
637 if (DO_BIC(BIC_Node))
638 outp += sprintf(outp, "%sNode", (printed++ ? delim : ""));
639 if (DO_BIC(BIC_Core))
640 outp += sprintf(outp, "%sCore", (printed++ ? delim : ""));
642 outp += sprintf(outp, "%sCPU", (printed++ ? delim : ""));
643 if (DO_BIC(BIC_APIC))
644 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : ""));
645 if (DO_BIC(BIC_X2APIC))
646 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : ""));
647 if (DO_BIC(BIC_Avg_MHz))
648 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : ""));
649 if (DO_BIC(BIC_Busy))
650 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : ""));
651 if (DO_BIC(BIC_Bzy_MHz))
652 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : ""));
653 if (DO_BIC(BIC_TSC_MHz))
654 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : ""));
656 if (DO_BIC(BIC_IRQ)) {
657 if (sums_need_wide_columns)
658 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : ""));
660 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : ""));
664 outp += sprintf(outp, "%sSMI", (printed++ ? delim : ""));
666 for (mp = sys.tp; mp; mp = mp->next) {
668 if (mp->format == FORMAT_RAW) {
670 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name);
672 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name);
674 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
675 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name);
677 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name);
681 if (DO_BIC(BIC_CPU_c1))
682 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : ""));
683 if (DO_BIC(BIC_CPU_c3))
684 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : ""));
685 if (DO_BIC(BIC_CPU_c6))
686 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : ""));
687 if (DO_BIC(BIC_CPU_c7))
688 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : ""));
690 if (DO_BIC(BIC_Mod_c6))
691 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : ""));
693 if (DO_BIC(BIC_CoreTmp))
694 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : ""));
696 if (do_rapl && !rapl_joules) {
697 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY))
698 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : ""));
699 } else if (do_rapl && rapl_joules) {
700 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY))
701 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : ""));
704 for (mp = sys.cp; mp; mp = mp->next) {
705 if (mp->format == FORMAT_RAW) {
707 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
709 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
711 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
712 outp += sprintf(outp, "%s%8s", delim, mp->name);
714 outp += sprintf(outp, "%s%s", delim, mp->name);
718 if (DO_BIC(BIC_PkgTmp))
719 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : ""));
721 if (DO_BIC(BIC_GFX_rc6))
722 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : ""));
724 if (DO_BIC(BIC_GFXMHz))
725 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : ""));
727 if (DO_BIC(BIC_Totl_c0))
728 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : ""));
729 if (DO_BIC(BIC_Any_c0))
730 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : ""));
731 if (DO_BIC(BIC_GFX_c0))
732 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : ""));
733 if (DO_BIC(BIC_CPUGFX))
734 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : ""));
736 if (DO_BIC(BIC_Pkgpc2))
737 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : ""));
738 if (DO_BIC(BIC_Pkgpc3))
739 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : ""));
740 if (DO_BIC(BIC_Pkgpc6))
741 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : ""));
742 if (DO_BIC(BIC_Pkgpc7))
743 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : ""));
744 if (DO_BIC(BIC_Pkgpc8))
745 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : ""));
746 if (DO_BIC(BIC_Pkgpc9))
747 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : ""));
748 if (DO_BIC(BIC_Pkgpc10))
749 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : ""));
750 if (DO_BIC(BIC_CPU_LPI))
751 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : ""));
752 if (DO_BIC(BIC_SYS_LPI))
753 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : ""));
755 if (do_rapl && !rapl_joules) {
756 if (DO_BIC(BIC_PkgWatt))
757 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : ""));
758 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY))
759 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : ""));
760 if (DO_BIC(BIC_GFXWatt))
761 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : ""));
762 if (DO_BIC(BIC_RAMWatt))
763 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : ""));
764 if (DO_BIC(BIC_PKG__))
765 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
766 if (DO_BIC(BIC_RAM__))
767 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
768 } else if (do_rapl && rapl_joules) {
769 if (DO_BIC(BIC_Pkg_J))
770 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : ""));
771 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY))
772 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : ""));
773 if (DO_BIC(BIC_GFX_J))
774 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : ""));
775 if (DO_BIC(BIC_RAM_J))
776 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : ""));
777 if (DO_BIC(BIC_PKG__))
778 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
779 if (DO_BIC(BIC_RAM__))
780 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
782 for (mp = sys.pp; mp; mp = mp->next) {
783 if (mp->format == FORMAT_RAW) {
785 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
787 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
789 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
790 outp += sprintf(outp, "%s%8s", delim, mp->name);
792 outp += sprintf(outp, "%s%s", delim, mp->name);
796 outp += sprintf(outp, "\n");
799 int dump_counters(struct thread_data *t, struct core_data *c,
803 struct msr_counter *mp;
805 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p);
808 outp += sprintf(outp, "CPU: %d flags 0x%x\n",
809 t->cpu_id, t->flags);
810 outp += sprintf(outp, "TSC: %016llX\n", t->tsc);
811 outp += sprintf(outp, "aperf: %016llX\n", t->aperf);
812 outp += sprintf(outp, "mperf: %016llX\n", t->mperf);
813 outp += sprintf(outp, "c1: %016llX\n", t->c1);
816 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count);
818 outp += sprintf(outp, "SMI: %d\n", t->smi_count);
820 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
821 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n",
822 i, mp->msr_num, t->counter[i]);
827 outp += sprintf(outp, "core: %d\n", c->core_id);
828 outp += sprintf(outp, "c3: %016llX\n", c->c3);
829 outp += sprintf(outp, "c6: %016llX\n", c->c6);
830 outp += sprintf(outp, "c7: %016llX\n", c->c7);
831 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c);
832 outp += sprintf(outp, "Joules: %0X\n", c->core_energy);
834 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
835 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n",
836 i, mp->msr_num, c->counter[i]);
838 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us);
842 outp += sprintf(outp, "package: %d\n", p->package_id);
844 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0);
845 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0);
846 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0);
847 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0);
849 outp += sprintf(outp, "pc2: %016llX\n", p->pc2);
850 if (DO_BIC(BIC_Pkgpc3))
851 outp += sprintf(outp, "pc3: %016llX\n", p->pc3);
852 if (DO_BIC(BIC_Pkgpc6))
853 outp += sprintf(outp, "pc6: %016llX\n", p->pc6);
854 if (DO_BIC(BIC_Pkgpc7))
855 outp += sprintf(outp, "pc7: %016llX\n", p->pc7);
856 outp += sprintf(outp, "pc8: %016llX\n", p->pc8);
857 outp += sprintf(outp, "pc9: %016llX\n", p->pc9);
858 outp += sprintf(outp, "pc10: %016llX\n", p->pc10);
859 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi);
860 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi);
861 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg);
862 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores);
863 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx);
864 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram);
865 outp += sprintf(outp, "Throttle PKG: %0X\n",
866 p->rapl_pkg_perf_status);
867 outp += sprintf(outp, "Throttle RAM: %0X\n",
868 p->rapl_dram_perf_status);
869 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c);
871 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
872 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n",
873 i, mp->msr_num, p->counter[i]);
877 outp += sprintf(outp, "\n");
883 * column formatting convention & formats
885 int format_counters(struct thread_data *t, struct core_data *c,
888 double interval_float, tsc;
891 struct msr_counter *mp;
895 /* if showing only 1st thread in core and this isn't one, bail out */
896 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
899 /* if showing only 1st thread in pkg and this isn't one, bail out */
900 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
903 /*if not summary line and --cpu is used */
904 if ((t != &average.threads) &&
905 (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset)))
908 if (DO_BIC(BIC_USEC)) {
909 /* on each row, print how many usec each timestamp took to gather */
912 timersub(&t->tv_end, &t->tv_begin, &tv);
913 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec);
916 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */
918 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec);
920 interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec/1000000.0;
922 tsc = t->tsc * tsc_tweak;
924 /* topo columns, print blanks on 1st (average) line */
925 if (t == &average.threads) {
926 if (DO_BIC(BIC_Package))
927 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
929 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
930 if (DO_BIC(BIC_Node))
931 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
932 if (DO_BIC(BIC_Core))
933 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
935 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
936 if (DO_BIC(BIC_APIC))
937 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
938 if (DO_BIC(BIC_X2APIC))
939 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
941 if (DO_BIC(BIC_Package)) {
943 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id);
945 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
947 if (DO_BIC(BIC_Die)) {
949 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id);
951 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
953 if (DO_BIC(BIC_Node)) {
955 outp += sprintf(outp, "%s%d",
956 (printed++ ? delim : ""),
957 cpus[t->cpu_id].physical_node_id);
959 outp += sprintf(outp, "%s-",
960 (printed++ ? delim : ""));
962 if (DO_BIC(BIC_Core)) {
964 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id);
966 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
969 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id);
970 if (DO_BIC(BIC_APIC))
971 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id);
972 if (DO_BIC(BIC_X2APIC))
973 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id);
976 if (DO_BIC(BIC_Avg_MHz))
977 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""),
978 1.0 / units * t->aperf / interval_float);
980 if (DO_BIC(BIC_Busy))
981 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf/tsc);
983 if (DO_BIC(BIC_Bzy_MHz)) {
985 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf);
987 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""),
988 tsc / units * t->aperf / t->mperf / interval_float);
991 if (DO_BIC(BIC_TSC_MHz))
992 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc/units/interval_float);
995 if (DO_BIC(BIC_IRQ)) {
996 if (sums_need_wide_columns)
997 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count);
999 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count);
1003 if (DO_BIC(BIC_SMI))
1004 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count);
1006 /* Added counters */
1007 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1008 if (mp->format == FORMAT_RAW) {
1009 if (mp->width == 32)
1010 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) t->counter[i]);
1012 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]);
1013 } else if (mp->format == FORMAT_DELTA) {
1014 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1015 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]);
1017 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]);
1018 } else if (mp->format == FORMAT_PERCENT) {
1019 if (mp->type == COUNTER_USEC)
1020 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), t->counter[i]/interval_float/10000);
1022 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i]/tsc);
1027 if (DO_BIC(BIC_CPU_c1))
1028 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1/tsc);
1031 /* print per-core data only for 1st thread in core */
1032 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1035 if (DO_BIC(BIC_CPU_c3))
1036 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3/tsc);
1037 if (DO_BIC(BIC_CPU_c6))
1038 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6/tsc);
1039 if (DO_BIC(BIC_CPU_c7))
1040 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7/tsc);
1043 if (DO_BIC(BIC_Mod_c6))
1044 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc);
1046 if (DO_BIC(BIC_CoreTmp))
1047 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c);
1049 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1050 if (mp->format == FORMAT_RAW) {
1051 if (mp->width == 32)
1052 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) c->counter[i]);
1054 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]);
1055 } else if (mp->format == FORMAT_DELTA) {
1056 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1057 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]);
1059 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]);
1060 } else if (mp->format == FORMAT_PERCENT) {
1061 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i]/tsc);
1066 * If measurement interval exceeds minimum RAPL Joule Counter range,
1067 * indicate that results are suspect by printing "**" in fraction place.
1069 if (interval_float < rapl_joule_counter_range)
1074 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY))
1075 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float);
1076 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY))
1077 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units);
1079 /* print per-package data only for 1st core in package */
1080 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1084 if (DO_BIC(BIC_PkgTmp))
1085 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c);
1088 if (DO_BIC(BIC_GFX_rc6)) {
1089 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */
1090 outp += sprintf(outp, "%s**.**", (printed++ ? delim : ""));
1092 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""),
1093 p->gfx_rc6_ms / 10.0 / interval_float);
1098 if (DO_BIC(BIC_GFXMHz))
1099 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz);
1101 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
1102 if (DO_BIC(BIC_Totl_c0))
1103 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0/tsc);
1104 if (DO_BIC(BIC_Any_c0))
1105 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0/tsc);
1106 if (DO_BIC(BIC_GFX_c0))
1107 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0/tsc);
1108 if (DO_BIC(BIC_CPUGFX))
1109 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0/tsc);
1111 if (DO_BIC(BIC_Pkgpc2))
1112 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2/tsc);
1113 if (DO_BIC(BIC_Pkgpc3))
1114 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3/tsc);
1115 if (DO_BIC(BIC_Pkgpc6))
1116 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6/tsc);
1117 if (DO_BIC(BIC_Pkgpc7))
1118 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7/tsc);
1119 if (DO_BIC(BIC_Pkgpc8))
1120 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8/tsc);
1121 if (DO_BIC(BIC_Pkgpc9))
1122 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9/tsc);
1123 if (DO_BIC(BIC_Pkgpc10))
1124 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10/tsc);
1126 if (DO_BIC(BIC_CPU_LPI))
1127 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float);
1128 if (DO_BIC(BIC_SYS_LPI))
1129 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float);
1131 if (DO_BIC(BIC_PkgWatt))
1132 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float);
1133 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY))
1134 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float);
1135 if (DO_BIC(BIC_GFXWatt))
1136 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float);
1137 if (DO_BIC(BIC_RAMWatt))
1138 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units / interval_float);
1139 if (DO_BIC(BIC_Pkg_J))
1140 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units);
1141 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY))
1142 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units);
1143 if (DO_BIC(BIC_GFX_J))
1144 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units);
1145 if (DO_BIC(BIC_RAM_J))
1146 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units);
1147 if (DO_BIC(BIC_PKG__))
1148 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
1149 if (DO_BIC(BIC_RAM__))
1150 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
1152 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1153 if (mp->format == FORMAT_RAW) {
1154 if (mp->width == 32)
1155 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) p->counter[i]);
1157 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]);
1158 } else if (mp->format == FORMAT_DELTA) {
1159 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1160 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]);
1162 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]);
1163 } else if (mp->format == FORMAT_PERCENT) {
1164 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i]/tsc);
1169 if (*(outp - 1) != '\n')
1170 outp += sprintf(outp, "\n");
1175 void flush_output_stdout(void)
1184 fputs(output_buffer, filep);
1187 outp = output_buffer;
1189 void flush_output_stderr(void)
1191 fputs(output_buffer, outf);
1193 outp = output_buffer;
1195 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1199 if (!printed || !summary_only)
1202 format_counters(&average.threads, &average.cores, &average.packages);
1209 for_all_cpus(format_counters, t, c, p);
1212 #define DELTA_WRAP32(new, old) \
1216 old = 0x100000000 + new - old; \
1220 delta_package(struct pkg_data *new, struct pkg_data *old)
1223 struct msr_counter *mp;
1226 if (DO_BIC(BIC_Totl_c0))
1227 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
1228 if (DO_BIC(BIC_Any_c0))
1229 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
1230 if (DO_BIC(BIC_GFX_c0))
1231 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
1232 if (DO_BIC(BIC_CPUGFX))
1233 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
1235 old->pc2 = new->pc2 - old->pc2;
1236 if (DO_BIC(BIC_Pkgpc3))
1237 old->pc3 = new->pc3 - old->pc3;
1238 if (DO_BIC(BIC_Pkgpc6))
1239 old->pc6 = new->pc6 - old->pc6;
1240 if (DO_BIC(BIC_Pkgpc7))
1241 old->pc7 = new->pc7 - old->pc7;
1242 old->pc8 = new->pc8 - old->pc8;
1243 old->pc9 = new->pc9 - old->pc9;
1244 old->pc10 = new->pc10 - old->pc10;
1245 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi;
1246 old->sys_lpi = new->sys_lpi - old->sys_lpi;
1247 old->pkg_temp_c = new->pkg_temp_c;
1249 /* flag an error when rc6 counter resets/wraps */
1250 if (old->gfx_rc6_ms > new->gfx_rc6_ms)
1251 old->gfx_rc6_ms = -1;
1253 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms;
1255 old->gfx_mhz = new->gfx_mhz;
1257 DELTA_WRAP32(new->energy_pkg, old->energy_pkg);
1258 DELTA_WRAP32(new->energy_cores, old->energy_cores);
1259 DELTA_WRAP32(new->energy_gfx, old->energy_gfx);
1260 DELTA_WRAP32(new->energy_dram, old->energy_dram);
1261 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status);
1262 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status);
1264 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1265 if (mp->format == FORMAT_RAW)
1266 old->counter[i] = new->counter[i];
1268 old->counter[i] = new->counter[i] - old->counter[i];
1275 delta_core(struct core_data *new, struct core_data *old)
1278 struct msr_counter *mp;
1280 old->c3 = new->c3 - old->c3;
1281 old->c6 = new->c6 - old->c6;
1282 old->c7 = new->c7 - old->c7;
1283 old->core_temp_c = new->core_temp_c;
1284 old->mc6_us = new->mc6_us - old->mc6_us;
1286 DELTA_WRAP32(new->core_energy, old->core_energy);
1288 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1289 if (mp->format == FORMAT_RAW)
1290 old->counter[i] = new->counter[i];
1292 old->counter[i] = new->counter[i] - old->counter[i];
1296 int soft_c1_residency_display(int bic)
1298 if (!DO_BIC(BIC_CPU_c1) || use_c1_residency_msr)
1301 return DO_BIC_READ(bic);
1308 delta_thread(struct thread_data *new, struct thread_data *old,
1309 struct core_data *core_delta)
1312 struct msr_counter *mp;
1314 /* we run cpuid just the 1st time, copy the results */
1315 if (DO_BIC(BIC_APIC))
1316 new->apic_id = old->apic_id;
1317 if (DO_BIC(BIC_X2APIC))
1318 new->x2apic_id = old->x2apic_id;
1321 * the timestamps from start of measurement interval are in "old"
1322 * the timestamp from end of measurement interval are in "new"
1323 * over-write old w/ new so we can print end of interval values
1326 timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta);
1327 old->tv_begin = new->tv_begin;
1328 old->tv_end = new->tv_end;
1330 old->tsc = new->tsc - old->tsc;
1332 /* check for TSC < 1 Mcycles over interval */
1333 if (old->tsc < (1000 * 1000))
1334 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n"
1335 "You can disable all c-states by booting with \"idle=poll\"\n"
1336 "or just the deep ones with \"processor.max_cstate=1\"");
1338 old->c1 = new->c1 - old->c1;
1340 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) ||
1341 soft_c1_residency_display(BIC_Avg_MHz)) {
1342 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) {
1343 old->aperf = new->aperf - old->aperf;
1344 old->mperf = new->mperf - old->mperf;
1351 if (use_c1_residency_msr) {
1353 * Some models have a dedicated C1 residency MSR,
1354 * which should be more accurate than the derivation below.
1358 * As counter collection is not atomic,
1359 * it is possible for mperf's non-halted cycles + idle states
1360 * to exceed TSC's all cycles: show c1 = 0% in that case.
1362 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak))
1365 /* normal case, derive c1 */
1366 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3
1367 - core_delta->c6 - core_delta->c7;
1371 if (old->mperf == 0) {
1373 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id);
1374 old->mperf = 1; /* divide by 0 protection */
1377 if (DO_BIC(BIC_IRQ))
1378 old->irq_count = new->irq_count - old->irq_count;
1380 if (DO_BIC(BIC_SMI))
1381 old->smi_count = new->smi_count - old->smi_count;
1383 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1384 if (mp->format == FORMAT_RAW)
1385 old->counter[i] = new->counter[i];
1387 old->counter[i] = new->counter[i] - old->counter[i];
1392 int delta_cpu(struct thread_data *t, struct core_data *c,
1393 struct pkg_data *p, struct thread_data *t2,
1394 struct core_data *c2, struct pkg_data *p2)
1398 /* calculate core delta only for 1st thread in core */
1399 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE)
1402 /* always calculate thread delta */
1403 retval = delta_thread(t, t2, c2); /* c2 is core delta */
1407 /* calculate package delta only for 1st core in package */
1408 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)
1409 retval = delta_package(p, p2);
1414 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1417 struct msr_counter *mp;
1419 t->tv_begin.tv_sec = 0;
1420 t->tv_begin.tv_usec = 0;
1421 t->tv_end.tv_sec = 0;
1422 t->tv_end.tv_usec = 0;
1423 t->tv_delta.tv_sec = 0;
1424 t->tv_delta.tv_usec = 0;
1434 /* tells format_counters to dump all fields from this set */
1435 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE;
1444 p->pkg_wtd_core_c0 = 0;
1445 p->pkg_any_core_c0 = 0;
1446 p->pkg_any_gfxe_c0 = 0;
1447 p->pkg_both_core_gfxe_c0 = 0;
1450 if (DO_BIC(BIC_Pkgpc3))
1452 if (DO_BIC(BIC_Pkgpc6))
1454 if (DO_BIC(BIC_Pkgpc7))
1464 p->energy_cores = 0;
1466 p->rapl_pkg_perf_status = 0;
1467 p->rapl_dram_perf_status = 0;
1472 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next)
1475 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next)
1478 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next)
1481 int sum_counters(struct thread_data *t, struct core_data *c,
1485 struct msr_counter *mp;
1487 /* copy un-changing apic_id's */
1488 if (DO_BIC(BIC_APIC))
1489 average.threads.apic_id = t->apic_id;
1490 if (DO_BIC(BIC_X2APIC))
1491 average.threads.x2apic_id = t->x2apic_id;
1493 /* remember first tv_begin */
1494 if (average.threads.tv_begin.tv_sec == 0)
1495 average.threads.tv_begin = t->tv_begin;
1497 /* remember last tv_end */
1498 average.threads.tv_end = t->tv_end;
1500 average.threads.tsc += t->tsc;
1501 average.threads.aperf += t->aperf;
1502 average.threads.mperf += t->mperf;
1503 average.threads.c1 += t->c1;
1505 average.threads.irq_count += t->irq_count;
1506 average.threads.smi_count += t->smi_count;
1508 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1509 if (mp->format == FORMAT_RAW)
1511 average.threads.counter[i] += t->counter[i];
1514 /* sum per-core values only for 1st thread in core */
1515 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1518 average.cores.c3 += c->c3;
1519 average.cores.c6 += c->c6;
1520 average.cores.c7 += c->c7;
1521 average.cores.mc6_us += c->mc6_us;
1523 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
1525 average.cores.core_energy += c->core_energy;
1527 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1528 if (mp->format == FORMAT_RAW)
1530 average.cores.counter[i] += c->counter[i];
1533 /* sum per-pkg values only for 1st core in pkg */
1534 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1537 if (DO_BIC(BIC_Totl_c0))
1538 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
1539 if (DO_BIC(BIC_Any_c0))
1540 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
1541 if (DO_BIC(BIC_GFX_c0))
1542 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
1543 if (DO_BIC(BIC_CPUGFX))
1544 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
1546 average.packages.pc2 += p->pc2;
1547 if (DO_BIC(BIC_Pkgpc3))
1548 average.packages.pc3 += p->pc3;
1549 if (DO_BIC(BIC_Pkgpc6))
1550 average.packages.pc6 += p->pc6;
1551 if (DO_BIC(BIC_Pkgpc7))
1552 average.packages.pc7 += p->pc7;
1553 average.packages.pc8 += p->pc8;
1554 average.packages.pc9 += p->pc9;
1555 average.packages.pc10 += p->pc10;
1557 average.packages.cpu_lpi = p->cpu_lpi;
1558 average.packages.sys_lpi = p->sys_lpi;
1560 average.packages.energy_pkg += p->energy_pkg;
1561 average.packages.energy_dram += p->energy_dram;
1562 average.packages.energy_cores += p->energy_cores;
1563 average.packages.energy_gfx += p->energy_gfx;
1565 average.packages.gfx_rc6_ms = p->gfx_rc6_ms;
1566 average.packages.gfx_mhz = p->gfx_mhz;
1568 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c);
1570 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status;
1571 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status;
1573 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1574 if (mp->format == FORMAT_RAW)
1576 average.packages.counter[i] += p->counter[i];
1581 * sum the counters for all cpus in the system
1582 * compute the weighted average
1584 void compute_average(struct thread_data *t, struct core_data *c,
1588 struct msr_counter *mp;
1590 clear_counters(&average.threads, &average.cores, &average.packages);
1592 for_all_cpus(sum_counters, t, c, p);
1594 /* Use the global time delta for the average. */
1595 average.threads.tv_delta = tv_delta;
1597 average.threads.tsc /= topo.num_cpus;
1598 average.threads.aperf /= topo.num_cpus;
1599 average.threads.mperf /= topo.num_cpus;
1600 average.threads.c1 /= topo.num_cpus;
1602 if (average.threads.irq_count > 9999999)
1603 sums_need_wide_columns = 1;
1605 average.cores.c3 /= topo.num_cores;
1606 average.cores.c6 /= topo.num_cores;
1607 average.cores.c7 /= topo.num_cores;
1608 average.cores.mc6_us /= topo.num_cores;
1610 if (DO_BIC(BIC_Totl_c0))
1611 average.packages.pkg_wtd_core_c0 /= topo.num_packages;
1612 if (DO_BIC(BIC_Any_c0))
1613 average.packages.pkg_any_core_c0 /= topo.num_packages;
1614 if (DO_BIC(BIC_GFX_c0))
1615 average.packages.pkg_any_gfxe_c0 /= topo.num_packages;
1616 if (DO_BIC(BIC_CPUGFX))
1617 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages;
1619 average.packages.pc2 /= topo.num_packages;
1620 if (DO_BIC(BIC_Pkgpc3))
1621 average.packages.pc3 /= topo.num_packages;
1622 if (DO_BIC(BIC_Pkgpc6))
1623 average.packages.pc6 /= topo.num_packages;
1624 if (DO_BIC(BIC_Pkgpc7))
1625 average.packages.pc7 /= topo.num_packages;
1627 average.packages.pc8 /= topo.num_packages;
1628 average.packages.pc9 /= topo.num_packages;
1629 average.packages.pc10 /= topo.num_packages;
1631 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1632 if (mp->format == FORMAT_RAW)
1634 if (mp->type == COUNTER_ITEMS) {
1635 if (average.threads.counter[i] > 9999999)
1636 sums_need_wide_columns = 1;
1639 average.threads.counter[i] /= topo.num_cpus;
1641 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1642 if (mp->format == FORMAT_RAW)
1644 if (mp->type == COUNTER_ITEMS) {
1645 if (average.cores.counter[i] > 9999999)
1646 sums_need_wide_columns = 1;
1648 average.cores.counter[i] /= topo.num_cores;
1650 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1651 if (mp->format == FORMAT_RAW)
1653 if (mp->type == COUNTER_ITEMS) {
1654 if (average.packages.counter[i] > 9999999)
1655 sums_need_wide_columns = 1;
1657 average.packages.counter[i] /= topo.num_packages;
1661 static unsigned long long rdtsc(void)
1663 unsigned int low, high;
1665 asm volatile("rdtsc" : "=a" (low), "=d" (high));
1667 return low | ((unsigned long long)high) << 32;
1671 * Open a file, and exit on failure
1673 FILE *fopen_or_die(const char *path, const char *mode)
1675 FILE *filep = fopen(path, mode);
1678 err(1, "%s: open failed", path);
1682 * snapshot_sysfs_counter()
1684 * return snapshot of given counter
1686 unsigned long long snapshot_sysfs_counter(char *path)
1690 unsigned long long counter;
1692 fp = fopen_or_die(path, "r");
1694 retval = fscanf(fp, "%lld", &counter);
1696 err(1, "snapshot_sysfs_counter(%s)", path);
1703 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp)
1705 if (mp->msr_num != 0) {
1706 if (get_msr(cpu, mp->msr_num, counterp))
1709 char path[128 + PATH_BYTES];
1711 if (mp->flags & SYSFS_PERCPU) {
1712 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s",
1715 *counterp = snapshot_sysfs_counter(path);
1717 *counterp = snapshot_sysfs_counter(mp->path);
1724 void get_apic_id(struct thread_data *t)
1726 unsigned int eax, ebx, ecx, edx;
1728 if (DO_BIC(BIC_APIC)) {
1729 eax = ebx = ecx = edx = 0;
1730 __cpuid(1, eax, ebx, ecx, edx);
1732 t->apic_id = (ebx >> 24) & 0xff;
1735 if (!DO_BIC(BIC_X2APIC))
1738 if (authentic_amd || hygon_genuine) {
1739 unsigned int topology_extensions;
1741 if (max_extended_level < 0x8000001e)
1744 eax = ebx = ecx = edx = 0;
1745 __cpuid(0x80000001, eax, ebx, ecx, edx);
1746 topology_extensions = ecx & (1 << 22);
1748 if (topology_extensions == 0)
1751 eax = ebx = ecx = edx = 0;
1752 __cpuid(0x8000001e, eax, ebx, ecx, edx);
1761 if (max_level < 0xb)
1765 __cpuid(0xb, eax, ebx, ecx, edx);
1768 if (debug && (t->apic_id != (t->x2apic_id & 0xff)))
1769 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n",
1770 t->cpu_id, t->apic_id, t->x2apic_id);
1776 * acquire and record local counters for that cpu
1778 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1780 int cpu = t->cpu_id;
1781 unsigned long long msr;
1782 int aperf_mperf_retry_count = 0;
1783 struct msr_counter *mp;
1786 if (cpu_migrate(cpu)) {
1787 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
1791 gettimeofday(&t->tv_begin, (struct timezone *)NULL);
1793 if (first_counter_read)
1796 t->tsc = rdtsc(); /* we are running on local CPU of interest */
1798 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) ||
1799 soft_c1_residency_display(BIC_Avg_MHz)) {
1800 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time;
1803 * The TSC, APERF and MPERF must be read together for
1804 * APERF/MPERF and MPERF/TSC to give accurate results.
1806 * Unfortunately, APERF and MPERF are read by
1807 * individual system call, so delays may occur
1808 * between them. If the time to read them
1809 * varies by a large amount, we re-read them.
1813 * This initial dummy APERF read has been seen to
1814 * reduce jitter in the subsequent reads.
1817 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
1820 t->tsc = rdtsc(); /* re-read close to APERF */
1822 tsc_before = t->tsc;
1824 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
1827 tsc_between = rdtsc();
1829 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
1832 tsc_after = rdtsc();
1834 aperf_time = tsc_between - tsc_before;
1835 mperf_time = tsc_after - tsc_between;
1838 * If the system call latency to read APERF and MPERF
1839 * differ by more than 2x, then try again.
1841 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) {
1842 aperf_mperf_retry_count++;
1843 if (aperf_mperf_retry_count < 5)
1846 warnx("cpu%d jitter %lld %lld",
1847 cpu, aperf_time, mperf_time);
1849 aperf_mperf_retry_count = 0;
1851 t->aperf = t->aperf * aperf_mperf_multiplier;
1852 t->mperf = t->mperf * aperf_mperf_multiplier;
1855 if (DO_BIC(BIC_IRQ))
1856 t->irq_count = irqs_per_cpu[cpu];
1857 if (DO_BIC(BIC_SMI)) {
1858 if (get_msr(cpu, MSR_SMI_COUNT, &msr))
1860 t->smi_count = msr & 0xFFFFFFFF;
1862 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) {
1863 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
1867 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1868 if (get_mp(cpu, mp, &t->counter[i]))
1872 /* collect core counters only for 1st thread in core */
1873 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1876 if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) {
1877 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
1881 if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !do_knl_cstates) {
1882 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
1884 } else if (do_knl_cstates || soft_c1_residency_display(BIC_CPU_c6)) {
1885 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6))
1889 if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7))
1890 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
1893 if (DO_BIC(BIC_Mod_c6))
1894 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us))
1897 if (DO_BIC(BIC_CoreTmp)) {
1898 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
1900 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
1903 if (do_rapl & RAPL_AMD_F17H) {
1904 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr))
1906 c->core_energy = msr & 0xFFFFFFFF;
1909 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1910 if (get_mp(cpu, mp, &c->counter[i]))
1914 /* collect package counters only for 1st core in package */
1915 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1918 if (DO_BIC(BIC_Totl_c0)) {
1919 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
1922 if (DO_BIC(BIC_Any_c0)) {
1923 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
1926 if (DO_BIC(BIC_GFX_c0)) {
1927 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
1930 if (DO_BIC(BIC_CPUGFX)) {
1931 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
1934 if (DO_BIC(BIC_Pkgpc3))
1935 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
1937 if (DO_BIC(BIC_Pkgpc6)) {
1938 if (do_slm_cstates) {
1939 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6))
1942 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
1947 if (DO_BIC(BIC_Pkgpc2))
1948 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
1950 if (DO_BIC(BIC_Pkgpc7))
1951 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7))
1953 if (DO_BIC(BIC_Pkgpc8))
1954 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8))
1956 if (DO_BIC(BIC_Pkgpc9))
1957 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9))
1959 if (DO_BIC(BIC_Pkgpc10))
1960 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10))
1963 if (DO_BIC(BIC_CPU_LPI))
1964 p->cpu_lpi = cpuidle_cur_cpu_lpi_us;
1965 if (DO_BIC(BIC_SYS_LPI))
1966 p->sys_lpi = cpuidle_cur_sys_lpi_us;
1968 if (do_rapl & RAPL_PKG) {
1969 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr))
1971 p->energy_pkg = msr & 0xFFFFFFFF;
1973 if (do_rapl & RAPL_CORES_ENERGY_STATUS) {
1974 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr))
1976 p->energy_cores = msr & 0xFFFFFFFF;
1978 if (do_rapl & RAPL_DRAM) {
1979 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr))
1981 p->energy_dram = msr & 0xFFFFFFFF;
1983 if (do_rapl & RAPL_GFX) {
1984 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr))
1986 p->energy_gfx = msr & 0xFFFFFFFF;
1988 if (do_rapl & RAPL_PKG_PERF_STATUS) {
1989 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr))
1991 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF;
1993 if (do_rapl & RAPL_DRAM_PERF_STATUS) {
1994 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr))
1996 p->rapl_dram_perf_status = msr & 0xFFFFFFFF;
1998 if (do_rapl & RAPL_AMD_F17H) {
1999 if (get_msr(cpu, MSR_PKG_ENERGY_STAT, &msr))
2001 p->energy_pkg = msr & 0xFFFFFFFF;
2003 if (DO_BIC(BIC_PkgTmp)) {
2004 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
2006 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
2009 if (DO_BIC(BIC_GFX_rc6))
2010 p->gfx_rc6_ms = gfx_cur_rc6_ms;
2012 if (DO_BIC(BIC_GFXMHz))
2013 p->gfx_mhz = gfx_cur_mhz;
2015 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
2016 if (get_mp(cpu, mp, &p->counter[i]))
2020 gettimeofday(&t->tv_end, (struct timezone *)NULL);
2026 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit:
2027 * If you change the values, note they are used both in comparisons
2028 * (>= PCL__7) and to index pkg_cstate_limit_strings[].
2031 #define PCLUKN 0 /* Unknown */
2032 #define PCLRSV 1 /* Reserved */
2033 #define PCL__0 2 /* PC0 */
2034 #define PCL__1 3 /* PC1 */
2035 #define PCL__2 4 /* PC2 */
2036 #define PCL__3 5 /* PC3 */
2037 #define PCL__4 6 /* PC4 */
2038 #define PCL__6 7 /* PC6 */
2039 #define PCL_6N 8 /* PC6 No Retention */
2040 #define PCL_6R 9 /* PC6 Retention */
2041 #define PCL__7 10 /* PC7 */
2042 #define PCL_7S 11 /* PC7 Shrink */
2043 #define PCL__8 12 /* PC8 */
2044 #define PCL__9 13 /* PC9 */
2045 #define PCL_10 14 /* PC10 */
2046 #define PCLUNL 15 /* Unlimited */
2048 int pkg_cstate_limit = PCLUKN;
2049 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
2050 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited"};
2052 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
2053 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
2054 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
2055 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7};
2056 int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
2057 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
2058 int glm_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
2059 int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
2063 calculate_tsc_tweak()
2065 tsc_tweak = base_hz / tsc_hz;
2069 dump_nhm_platform_info(void)
2071 unsigned long long msr;
2074 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
2076 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
2078 ratio = (msr >> 40) & 0xFF;
2079 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n",
2080 ratio, bclk, ratio * bclk);
2082 ratio = (msr >> 8) & 0xFF;
2083 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n",
2084 ratio, bclk, ratio * bclk);
2086 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
2087 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
2088 base_cpu, msr, msr & 0x2 ? "EN" : "DIS");
2094 dump_hsw_turbo_ratio_limits(void)
2096 unsigned long long msr;
2099 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
2101 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr);
2103 ratio = (msr >> 8) & 0xFF;
2105 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n",
2106 ratio, bclk, ratio * bclk);
2108 ratio = (msr >> 0) & 0xFF;
2110 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n",
2111 ratio, bclk, ratio * bclk);
2116 dump_ivt_turbo_ratio_limits(void)
2118 unsigned long long msr;
2121 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
2123 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr);
2125 ratio = (msr >> 56) & 0xFF;
2127 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n",
2128 ratio, bclk, ratio * bclk);
2130 ratio = (msr >> 48) & 0xFF;
2132 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n",
2133 ratio, bclk, ratio * bclk);
2135 ratio = (msr >> 40) & 0xFF;
2137 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n",
2138 ratio, bclk, ratio * bclk);
2140 ratio = (msr >> 32) & 0xFF;
2142 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n",
2143 ratio, bclk, ratio * bclk);
2145 ratio = (msr >> 24) & 0xFF;
2147 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n",
2148 ratio, bclk, ratio * bclk);
2150 ratio = (msr >> 16) & 0xFF;
2152 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n",
2153 ratio, bclk, ratio * bclk);
2155 ratio = (msr >> 8) & 0xFF;
2157 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n",
2158 ratio, bclk, ratio * bclk);
2160 ratio = (msr >> 0) & 0xFF;
2162 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n",
2163 ratio, bclk, ratio * bclk);
2166 int has_turbo_ratio_group_limits(int family, int model)
2173 case INTEL_FAM6_ATOM_GOLDMONT:
2174 case INTEL_FAM6_SKYLAKE_X:
2175 case INTEL_FAM6_ATOM_GOLDMONT_D:
2182 dump_turbo_ratio_limits(int family, int model)
2184 unsigned long long msr, core_counts;
2185 unsigned int ratio, group_size;
2187 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
2188 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
2190 if (has_turbo_ratio_group_limits(family, model)) {
2191 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts);
2192 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts);
2194 core_counts = 0x0807060504030201;
2197 ratio = (msr >> 56) & 0xFF;
2198 group_size = (core_counts >> 56) & 0xFF;
2200 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2201 ratio, bclk, ratio * bclk, group_size);
2203 ratio = (msr >> 48) & 0xFF;
2204 group_size = (core_counts >> 48) & 0xFF;
2206 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2207 ratio, bclk, ratio * bclk, group_size);
2209 ratio = (msr >> 40) & 0xFF;
2210 group_size = (core_counts >> 40) & 0xFF;
2212 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2213 ratio, bclk, ratio * bclk, group_size);
2215 ratio = (msr >> 32) & 0xFF;
2216 group_size = (core_counts >> 32) & 0xFF;
2218 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2219 ratio, bclk, ratio * bclk, group_size);
2221 ratio = (msr >> 24) & 0xFF;
2222 group_size = (core_counts >> 24) & 0xFF;
2224 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2225 ratio, bclk, ratio * bclk, group_size);
2227 ratio = (msr >> 16) & 0xFF;
2228 group_size = (core_counts >> 16) & 0xFF;
2230 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2231 ratio, bclk, ratio * bclk, group_size);
2233 ratio = (msr >> 8) & 0xFF;
2234 group_size = (core_counts >> 8) & 0xFF;
2236 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2237 ratio, bclk, ratio * bclk, group_size);
2239 ratio = (msr >> 0) & 0xFF;
2240 group_size = (core_counts >> 0) & 0xFF;
2242 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2243 ratio, bclk, ratio * bclk, group_size);
2248 dump_atom_turbo_ratio_limits(void)
2250 unsigned long long msr;
2253 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr);
2254 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
2256 ratio = (msr >> 0) & 0x3F;
2258 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n",
2259 ratio, bclk, ratio * bclk);
2261 ratio = (msr >> 8) & 0x3F;
2263 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n",
2264 ratio, bclk, ratio * bclk);
2266 ratio = (msr >> 16) & 0x3F;
2268 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n",
2269 ratio, bclk, ratio * bclk);
2271 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr);
2272 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
2274 ratio = (msr >> 24) & 0x3F;
2276 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n",
2277 ratio, bclk, ratio * bclk);
2279 ratio = (msr >> 16) & 0x3F;
2281 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n",
2282 ratio, bclk, ratio * bclk);
2284 ratio = (msr >> 8) & 0x3F;
2286 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n",
2287 ratio, bclk, ratio * bclk);
2289 ratio = (msr >> 0) & 0x3F;
2291 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n",
2292 ratio, bclk, ratio * bclk);
2296 dump_knl_turbo_ratio_limits(void)
2298 const unsigned int buckets_no = 7;
2300 unsigned long long msr;
2301 int delta_cores, delta_ratio;
2303 unsigned int cores[buckets_no];
2304 unsigned int ratio[buckets_no];
2306 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
2308 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n",
2312 * Turbo encoding in KNL is as follows:
2314 * [7:1] -- Base value of number of active cores of bucket 1.
2315 * [15:8] -- Base value of freq ratio of bucket 1.
2316 * [20:16] -- +ve delta of number of active cores of bucket 2.
2317 * i.e. active cores of bucket 2 =
2318 * active cores of bucket 1 + delta
2319 * [23:21] -- Negative delta of freq ratio of bucket 2.
2320 * i.e. freq ratio of bucket 2 =
2321 * freq ratio of bucket 1 - delta
2322 * [28:24]-- +ve delta of number of active cores of bucket 3.
2323 * [31:29]-- -ve delta of freq ratio of bucket 3.
2324 * [36:32]-- +ve delta of number of active cores of bucket 4.
2325 * [39:37]-- -ve delta of freq ratio of bucket 4.
2326 * [44:40]-- +ve delta of number of active cores of bucket 5.
2327 * [47:45]-- -ve delta of freq ratio of bucket 5.
2328 * [52:48]-- +ve delta of number of active cores of bucket 6.
2329 * [55:53]-- -ve delta of freq ratio of bucket 6.
2330 * [60:56]-- +ve delta of number of active cores of bucket 7.
2331 * [63:61]-- -ve delta of freq ratio of bucket 7.
2335 cores[b_nr] = (msr & 0xFF) >> 1;
2336 ratio[b_nr] = (msr >> 8) & 0xFF;
2338 for (i = 16; i < 64; i += 8) {
2339 delta_cores = (msr >> i) & 0x1F;
2340 delta_ratio = (msr >> (i + 5)) & 0x7;
2342 cores[b_nr + 1] = cores[b_nr] + delta_cores;
2343 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio;
2347 for (i = buckets_no - 1; i >= 0; i--)
2348 if (i > 0 ? ratio[i] != ratio[i - 1] : 1)
2350 "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2351 ratio[i], bclk, ratio[i] * bclk, cores[i]);
2355 dump_nhm_cst_cfg(void)
2357 unsigned long long msr;
2359 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
2361 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr);
2363 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)",
2364 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "",
2365 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "",
2366 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "",
2367 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "",
2368 (msr & (1 << 15)) ? "" : "UN",
2369 (unsigned int)msr & 0xF,
2370 pkg_cstate_limit_strings[pkg_cstate_limit]);
2372 #define AUTOMATIC_CSTATE_CONVERSION (1UL << 16)
2373 if (has_automatic_cstate_conversion) {
2374 fprintf(outf, ", automatic c-state conversion=%s",
2375 (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off");
2378 fprintf(outf, ")\n");
2384 dump_config_tdp(void)
2386 unsigned long long msr;
2388 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
2389 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr);
2390 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF);
2392 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
2393 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr);
2395 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
2396 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
2397 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
2398 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF);
2400 fprintf(outf, ")\n");
2402 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
2403 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr);
2405 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
2406 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
2407 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
2408 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF);
2410 fprintf(outf, ")\n");
2412 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
2413 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr);
2415 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3);
2416 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
2417 fprintf(outf, ")\n");
2419 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
2420 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr);
2421 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF);
2422 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
2423 fprintf(outf, ")\n");
2426 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
2428 void print_irtl(void)
2430 unsigned long long msr;
2432 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr);
2433 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr);
2434 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2435 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2437 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr);
2438 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr);
2439 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2440 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2442 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr);
2443 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr);
2444 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2445 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2450 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr);
2451 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr);
2452 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2453 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2455 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr);
2456 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr);
2457 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2458 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2460 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr);
2461 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr);
2462 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2463 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2466 void free_fd_percpu(void)
2470 for (i = 0; i < topo.max_cpu_num + 1; ++i) {
2471 if (fd_percpu[i] != 0)
2472 close(fd_percpu[i]);
2478 void free_all_buffers(void)
2482 CPU_FREE(cpu_present_set);
2483 cpu_present_set = NULL;
2484 cpu_present_setsize = 0;
2486 CPU_FREE(cpu_affinity_set);
2487 cpu_affinity_set = NULL;
2488 cpu_affinity_setsize = 0;
2496 package_even = NULL;
2506 free(output_buffer);
2507 output_buffer = NULL;
2512 free(irq_column_2_cpu);
2515 for (i = 0; i <= topo.max_cpu_num; ++i) {
2516 if (cpus[i].put_ids)
2517 CPU_FREE(cpus[i].put_ids);
2524 * Parse a file containing a single int.
2525 * Return 0 if file can not be opened
2526 * Exit if file can be opened, but can not be parsed
2528 int parse_int_file(const char *fmt, ...)
2531 char path[PATH_MAX];
2535 va_start(args, fmt);
2536 vsnprintf(path, sizeof(path), fmt, args);
2538 filep = fopen(path, "r");
2541 if (fscanf(filep, "%d", &value) != 1)
2542 err(1, "%s: failed to parse number from file", path);
2548 * cpu_is_first_core_in_package(cpu)
2549 * return 1 if given CPU is 1st core in package
2551 int cpu_is_first_core_in_package(int cpu)
2553 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu);
2556 int get_physical_package_id(int cpu)
2558 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu);
2561 int get_die_id(int cpu)
2563 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu);
2566 int get_core_id(int cpu)
2568 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu);
2571 void set_node_data(void)
2573 int pkg, node, lnode, cpu, cpux;
2576 /* initialize logical_node_id */
2577 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu)
2578 cpus[cpu].logical_node_id = -1;
2581 for (pkg = 0; pkg < topo.num_packages; pkg++) {
2583 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) {
2584 if (cpus[cpu].physical_package_id != pkg)
2586 /* find a cpu with an unset logical_node_id */
2587 if (cpus[cpu].logical_node_id != -1)
2589 cpus[cpu].logical_node_id = lnode;
2590 node = cpus[cpu].physical_node_id;
2593 * find all matching cpus on this pkg and set
2594 * the logical_node_id
2596 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) {
2597 if ((cpus[cpux].physical_package_id == pkg) &&
2598 (cpus[cpux].physical_node_id == node)) {
2599 cpus[cpux].logical_node_id = lnode;
2604 if (lnode > topo.nodes_per_pkg)
2605 topo.nodes_per_pkg = lnode;
2607 if (cpu_count >= topo.max_cpu_num)
2612 int get_physical_node_id(struct cpu_topology *thiscpu)
2617 int cpu = thiscpu->logical_cpu_id;
2619 for (i = 0; i <= topo.max_cpu_num; i++) {
2620 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist",
2622 filep = fopen(path, "r");
2631 int get_thread_siblings(struct cpu_topology *thiscpu)
2633 char path[80], character;
2636 int so, shift, sib_core;
2637 int cpu = thiscpu->logical_cpu_id;
2638 int offset = topo.max_cpu_num + 1;
2642 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1));
2643 if (thiscpu->thread_id < 0)
2644 thiscpu->thread_id = thread_id++;
2645 if (!thiscpu->put_ids)
2648 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
2649 CPU_ZERO_S(size, thiscpu->put_ids);
2652 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu);
2653 filep = fopen_or_die(path, "r");
2655 offset -= BITMASK_SIZE;
2656 if (fscanf(filep, "%lx%c", &map, &character) != 2)
2657 err(1, "%s: failed to parse file", path);
2658 for (shift = 0; shift < BITMASK_SIZE; shift++) {
2659 if ((map >> shift) & 0x1) {
2660 so = shift + offset;
2661 sib_core = get_core_id(so);
2662 if (sib_core == thiscpu->physical_core_id) {
2663 CPU_SET_S(so, size, thiscpu->put_ids);
2665 (cpus[so].thread_id < 0))
2666 cpus[so].thread_id =
2671 } while (!strncmp(&character, ",", 1));
2674 return CPU_COUNT_S(size, thiscpu->put_ids);
2678 * run func(thread, core, package) in topology order
2679 * skip non-present cpus
2682 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *,
2683 struct pkg_data *, struct thread_data *, struct core_data *,
2684 struct pkg_data *), struct thread_data *thread_base,
2685 struct core_data *core_base, struct pkg_data *pkg_base,
2686 struct thread_data *thread_base2, struct core_data *core_base2,
2687 struct pkg_data *pkg_base2)
2689 int retval, pkg_no, node_no, core_no, thread_no;
2691 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
2692 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) {
2693 for (core_no = 0; core_no < topo.cores_per_node;
2695 for (thread_no = 0; thread_no <
2696 topo.threads_per_core; ++thread_no) {
2697 struct thread_data *t, *t2;
2698 struct core_data *c, *c2;
2699 struct pkg_data *p, *p2;
2701 t = GET_THREAD(thread_base, thread_no,
2705 if (cpu_is_not_present(t->cpu_id))
2708 t2 = GET_THREAD(thread_base2, thread_no,
2712 c = GET_CORE(core_base, core_no,
2714 c2 = GET_CORE(core_base2, core_no,
2718 p = GET_PKG(pkg_base, pkg_no);
2719 p2 = GET_PKG(pkg_base2, pkg_no);
2721 retval = func(t, c, p, t2, c2, p2);
2732 * run func(cpu) on every cpu in /proc/stat
2733 * return max_cpu number
2735 int for_all_proc_cpus(int (func)(int))
2741 fp = fopen_or_die(proc_stat, "r");
2743 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
2745 err(1, "%s: failed to parse format", proc_stat);
2748 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num);
2752 retval = func(cpu_num);
2762 void re_initialize(void)
2765 setup_all_buffers();
2766 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus);
2769 void set_max_cpu_num(void)
2772 unsigned long dummy;
2774 topo.max_cpu_num = 0;
2775 filep = fopen_or_die(
2776 "/sys/devices/system/cpu/cpu0/topology/thread_siblings",
2778 while (fscanf(filep, "%lx,", &dummy) == 1)
2779 topo.max_cpu_num += BITMASK_SIZE;
2781 topo.max_cpu_num--; /* 0 based */
2786 * remember the last one seen, it will be the max
2788 int count_cpus(int cpu)
2793 int mark_cpu_present(int cpu)
2795 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set);
2799 int init_thread_id(int cpu)
2801 cpus[cpu].thread_id = -1;
2806 * snapshot_proc_interrupts()
2808 * read and record summary of /proc/interrupts
2810 * return 1 if config change requires a restart, else return 0
2812 int snapshot_proc_interrupts(void)
2818 fp = fopen_or_die("/proc/interrupts", "r");
2822 /* read 1st line of /proc/interrupts to get cpu* name for each column */
2823 for (column = 0; column < topo.num_cpus; ++column) {
2826 retval = fscanf(fp, " CPU%d", &cpu_number);
2830 if (cpu_number > topo.max_cpu_num) {
2831 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num);
2835 irq_column_2_cpu[column] = cpu_number;
2836 irqs_per_cpu[cpu_number] = 0;
2839 /* read /proc/interrupt count lines and sum up irqs per cpu */
2844 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */
2848 /* read the count per cpu */
2849 for (column = 0; column < topo.num_cpus; ++column) {
2851 int cpu_number, irq_count;
2853 retval = fscanf(fp, " %d", &irq_count);
2857 cpu_number = irq_column_2_cpu[column];
2858 irqs_per_cpu[cpu_number] += irq_count;
2862 while (getc(fp) != '\n')
2863 ; /* flush interrupt description */
2869 * snapshot_gfx_rc6_ms()
2871 * record snapshot of
2872 * /sys/class/drm/card0/power/rc6_residency_ms
2874 * return 1 if config change requires a restart, else return 0
2876 int snapshot_gfx_rc6_ms(void)
2881 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r");
2883 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms);
2892 * snapshot_gfx_mhz()
2894 * record snapshot of
2895 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz
2897 * return 1 if config change requires a restart, else return 0
2899 int snapshot_gfx_mhz(void)
2905 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r");
2911 retval = fscanf(fp, "%d", &gfx_cur_mhz);
2919 * snapshot_cpu_lpi()
2921 * record snapshot of
2922 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
2924 int snapshot_cpu_lpi_us(void)
2929 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r");
2931 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us);
2933 fprintf(stderr, "Disabling Low Power Idle CPU output\n");
2934 BIC_NOT_PRESENT(BIC_CPU_LPI);
2944 * snapshot_sys_lpi()
2946 * record snapshot of sys_lpi_file
2948 int snapshot_sys_lpi_us(void)
2953 fp = fopen_or_die(sys_lpi_file, "r");
2955 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us);
2957 fprintf(stderr, "Disabling Low Power Idle System output\n");
2958 BIC_NOT_PRESENT(BIC_SYS_LPI);
2967 * snapshot /proc and /sys files
2969 * return 1 if configuration restart needed, else return 0
2971 int snapshot_proc_sysfs_files(void)
2973 if (DO_BIC(BIC_IRQ))
2974 if (snapshot_proc_interrupts())
2977 if (DO_BIC(BIC_GFX_rc6))
2978 snapshot_gfx_rc6_ms();
2980 if (DO_BIC(BIC_GFXMHz))
2983 if (DO_BIC(BIC_CPU_LPI))
2984 snapshot_cpu_lpi_us();
2986 if (DO_BIC(BIC_SYS_LPI))
2987 snapshot_sys_lpi_us();
2994 static void signal_handler (int signal)
3000 fprintf(stderr, " SIGINT\n");
3004 fprintf(stderr, "SIGUSR1\n");
3009 void setup_signal_handler(void)
3011 struct sigaction sa;
3013 memset(&sa, 0, sizeof(sa));
3015 sa.sa_handler = &signal_handler;
3017 if (sigaction(SIGINT, &sa, NULL) < 0)
3018 err(1, "sigaction SIGINT");
3019 if (sigaction(SIGUSR1, &sa, NULL) < 0)
3020 err(1, "sigaction SIGUSR1");
3025 struct timeval tout;
3026 struct timespec rest;
3031 FD_SET(0, &readfds);
3034 nanosleep(&interval_ts, NULL);
3039 retval = select(1, &readfds, NULL, NULL, &tout);
3042 switch (getc(stdin)) {
3048 * 'stdin' is a pipe closed on the other end. There
3049 * won't be any further input.
3052 /* Sleep the rest of the time */
3053 rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000);
3054 rest.tv_nsec = (tout.tv_usec % 1000000) * 1000;
3055 nanosleep(&rest, NULL);
3061 void turbostat_loop()
3067 setup_signal_handler();
3072 snapshot_proc_sysfs_files();
3073 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
3074 first_counter_read = 0;
3077 } else if (retval == -1) {
3078 if (restarted > 1) {
3086 gettimeofday(&tv_even, (struct timezone *)NULL);
3089 if (for_all_proc_cpus(cpu_is_not_present)) {
3094 if (snapshot_proc_sysfs_files())
3096 retval = for_all_cpus(get_counters, ODD_COUNTERS);
3099 } else if (retval == -1) {
3103 gettimeofday(&tv_odd, (struct timezone *)NULL);
3104 timersub(&tv_odd, &tv_even, &tv_delta);
3105 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) {
3109 compute_average(EVEN_COUNTERS);
3110 format_all_counters(EVEN_COUNTERS);
3111 flush_output_stdout();
3114 if (num_iterations && ++done_iters >= num_iterations)
3117 if (snapshot_proc_sysfs_files())
3119 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
3122 } else if (retval == -1) {
3126 gettimeofday(&tv_even, (struct timezone *)NULL);
3127 timersub(&tv_even, &tv_odd, &tv_delta);
3128 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) {
3132 compute_average(ODD_COUNTERS);
3133 format_all_counters(ODD_COUNTERS);
3134 flush_output_stdout();
3137 if (num_iterations && ++done_iters >= num_iterations)
3142 void check_dev_msr()
3147 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
3148 if (stat(pathname, &sb))
3149 if (system("/sbin/modprobe msr > /dev/null 2>&1"))
3150 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
3154 * check for CAP_SYS_RAWIO
3155 * return 0 on success
3158 int check_for_cap_sys_rawio(void)
3161 cap_flag_value_t cap_flag_value;
3163 caps = cap_get_proc();
3165 err(-6, "cap_get_proc\n");
3167 if (cap_get_flag(caps, CAP_SYS_RAWIO, CAP_EFFECTIVE, &cap_flag_value))
3168 err(-6, "cap_get\n");
3170 if (cap_flag_value != CAP_SET) {
3171 warnx("capget(CAP_SYS_RAWIO) failed,"
3172 " try \"# setcap cap_sys_rawio=ep %s\"", progname);
3176 if (cap_free(caps) == -1)
3177 err(-6, "cap_free\n");
3181 void check_permissions(void)
3186 /* check for CAP_SYS_RAWIO */
3187 do_exit += check_for_cap_sys_rawio();
3189 /* test file permissions */
3190 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
3191 if (euidaccess(pathname, R_OK)) {
3193 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr");
3196 /* if all else fails, thell them to be root */
3199 warnx("... or simply run as root");
3206 * NHM adds support for additional MSRs:
3208 * MSR_SMI_COUNT 0x00000034
3210 * MSR_PLATFORM_INFO 0x000000ce
3211 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
3213 * MSR_MISC_PWR_MGMT 0x000001aa
3215 * MSR_PKG_C3_RESIDENCY 0x000003f8
3216 * MSR_PKG_C6_RESIDENCY 0x000003f9
3217 * MSR_CORE_C3_RESIDENCY 0x000003fc
3218 * MSR_CORE_C6_RESIDENCY 0x000003fd
3221 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL
3222 * sets has_misc_feature_control
3224 int probe_nhm_msrs(unsigned int family, unsigned int model)
3226 unsigned long long msr;
3227 unsigned int base_ratio;
3228 int *pkg_cstate_limits;
3236 bclk = discover_bclk(family, model);
3239 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
3240 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
3241 pkg_cstate_limits = nhm_pkg_cstate_limits;
3243 case INTEL_FAM6_SANDYBRIDGE: /* SNB */
3244 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */
3245 case INTEL_FAM6_IVYBRIDGE: /* IVB */
3246 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
3247 pkg_cstate_limits = snb_pkg_cstate_limits;
3248 has_misc_feature_control = 1;
3250 case INTEL_FAM6_HASWELL: /* HSW */
3251 case INTEL_FAM6_HASWELL_G: /* HSW */
3252 case INTEL_FAM6_HASWELL_X: /* HSX */
3253 case INTEL_FAM6_HASWELL_L: /* HSW */
3254 case INTEL_FAM6_BROADWELL: /* BDW */
3255 case INTEL_FAM6_BROADWELL_G: /* BDW */
3256 case INTEL_FAM6_BROADWELL_X: /* BDX */
3257 case INTEL_FAM6_SKYLAKE_L: /* SKL */
3258 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
3259 pkg_cstate_limits = hsw_pkg_cstate_limits;
3260 has_misc_feature_control = 1;
3262 case INTEL_FAM6_SKYLAKE_X: /* SKX */
3263 pkg_cstate_limits = skx_pkg_cstate_limits;
3264 has_misc_feature_control = 1;
3266 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
3267 no_MSR_MISC_PWR_MGMT = 1;
3268 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
3269 pkg_cstate_limits = slv_pkg_cstate_limits;
3271 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */
3272 pkg_cstate_limits = amt_pkg_cstate_limits;
3273 no_MSR_MISC_PWR_MGMT = 1;
3275 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */
3276 pkg_cstate_limits = phi_pkg_cstate_limits;
3278 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3279 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
3280 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
3281 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
3282 pkg_cstate_limits = glm_pkg_cstate_limits;
3287 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
3288 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
3290 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
3291 base_ratio = (msr >> 8) & 0xFF;
3293 base_hz = base_ratio * bclk * 1000000;
3298 * SLV client has support for unique MSRs:
3300 * MSR_CC6_DEMOTION_POLICY_CONFIG
3301 * MSR_MC6_DEMOTION_POLICY_CONFIG
3304 int has_slv_msrs(unsigned int family, unsigned int model)
3310 case INTEL_FAM6_ATOM_SILVERMONT:
3311 case INTEL_FAM6_ATOM_SILVERMONT_MID:
3312 case INTEL_FAM6_ATOM_AIRMONT_MID:
3317 int is_dnv(unsigned int family, unsigned int model)
3324 case INTEL_FAM6_ATOM_GOLDMONT_D:
3329 int is_bdx(unsigned int family, unsigned int model)
3336 case INTEL_FAM6_BROADWELL_X:
3341 int is_skx(unsigned int family, unsigned int model)
3348 case INTEL_FAM6_SKYLAKE_X:
3353 int is_ehl(unsigned int family, unsigned int model)
3359 case INTEL_FAM6_ATOM_TREMONT:
3365 int has_turbo_ratio_limit(unsigned int family, unsigned int model)
3367 if (has_slv_msrs(family, model))
3371 /* Nehalem compatible, but do not include turbo-ratio limit support */
3372 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
3373 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */
3379 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model)
3381 if (has_slv_msrs(family, model))
3386 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
3395 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
3396 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
3402 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model)
3411 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
3418 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model)
3427 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
3433 int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model)
3442 case INTEL_FAM6_ATOM_GOLDMONT:
3443 case INTEL_FAM6_SKYLAKE_X:
3449 int has_config_tdp(unsigned int family, unsigned int model)
3458 case INTEL_FAM6_IVYBRIDGE: /* IVB */
3459 case INTEL_FAM6_HASWELL: /* HSW */
3460 case INTEL_FAM6_HASWELL_X: /* HSX */
3461 case INTEL_FAM6_HASWELL_L: /* HSW */
3462 case INTEL_FAM6_HASWELL_G: /* HSW */
3463 case INTEL_FAM6_BROADWELL: /* BDW */
3464 case INTEL_FAM6_BROADWELL_G: /* BDW */
3465 case INTEL_FAM6_BROADWELL_X: /* BDX */
3466 case INTEL_FAM6_SKYLAKE_L: /* SKL */
3467 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
3468 case INTEL_FAM6_SKYLAKE_X: /* SKX */
3470 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
3478 dump_cstate_pstate_config_info(unsigned int family, unsigned int model)
3480 if (!do_nhm_platform_info)
3483 dump_nhm_platform_info();
3485 if (has_hsw_turbo_ratio_limit(family, model))
3486 dump_hsw_turbo_ratio_limits();
3488 if (has_ivt_turbo_ratio_limit(family, model))
3489 dump_ivt_turbo_ratio_limits();
3491 if (has_turbo_ratio_limit(family, model))
3492 dump_turbo_ratio_limits(family, model);
3494 if (has_atom_turbo_ratio_limit(family, model))
3495 dump_atom_turbo_ratio_limits();
3497 if (has_knl_turbo_ratio_limit(family, model))
3498 dump_knl_turbo_ratio_limits();
3500 if (has_config_tdp(family, model))
3507 dump_sysfs_cstate_config(void)
3516 if (!DO_BIC(BIC_sysfs))
3519 for (state = 0; state < 10; ++state) {
3521 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name",
3523 input = fopen(path, "r");
3526 if (!fgets(name_buf, sizeof(name_buf), input))
3527 err(1, "%s: failed to read file", path);
3529 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
3530 sp = strchr(name_buf, '-');
3532 sp = strchrnul(name_buf, '\n');
3536 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc",
3538 input = fopen(path, "r");
3541 if (!fgets(desc, sizeof(desc), input))
3542 err(1, "%s: failed to read file", path);
3544 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc);
3549 dump_sysfs_pstate_config(void)
3552 char driver_buf[64];
3553 char governor_buf[64];
3557 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver",
3559 input = fopen(path, "r");
3560 if (input == NULL) {
3561 fprintf(outf, "NSFOD %s\n", path);
3564 if (!fgets(driver_buf, sizeof(driver_buf), input))
3565 err(1, "%s: failed to read file", path);
3568 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor",
3570 input = fopen(path, "r");
3571 if (input == NULL) {
3572 fprintf(outf, "NSFOD %s\n", path);
3575 if (!fgets(governor_buf, sizeof(governor_buf), input))
3576 err(1, "%s: failed to read file", path);
3579 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf);
3580 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf);
3582 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost");
3583 input = fopen(path, "r");
3584 if (input != NULL) {
3585 if (fscanf(input, "%d", &turbo) != 1)
3586 err(1, "%s: failed to parse number from file", path);
3587 fprintf(outf, "cpufreq boost: %d\n", turbo);
3591 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo");
3592 input = fopen(path, "r");
3593 if (input != NULL) {
3594 if (fscanf(input, "%d", &turbo) != 1)
3595 err(1, "%s: failed to parse number from file", path);
3596 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo);
3604 * Decode the ENERGY_PERF_BIAS MSR
3606 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3608 unsigned long long msr;
3617 /* EPB is per-package */
3618 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
3621 if (cpu_migrate(cpu)) {
3622 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3626 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr))
3629 switch (msr & 0xF) {
3630 case ENERGY_PERF_BIAS_PERFORMANCE:
3631 epb_string = "performance";
3633 case ENERGY_PERF_BIAS_NORMAL:
3634 epb_string = "balanced";
3636 case ENERGY_PERF_BIAS_POWERSAVE:
3637 epb_string = "powersave";
3640 epb_string = "custom";
3643 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string);
3649 * Decode the MSR_HWP_CAPABILITIES
3651 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3653 unsigned long long msr;
3661 /* MSR_HWP_CAPABILITIES is per-package */
3662 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
3665 if (cpu_migrate(cpu)) {
3666 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3670 if (get_msr(cpu, MSR_PM_ENABLE, &msr))
3673 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n",
3674 cpu, msr, (msr & (1 << 0)) ? "" : "No-");
3676 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */
3677 if ((msr & (1 << 0)) == 0)
3680 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
3683 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx "
3684 "(high %d guar %d eff %d low %d)\n",
3686 (unsigned int)HWP_HIGHEST_PERF(msr),
3687 (unsigned int)HWP_GUARANTEED_PERF(msr),
3688 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr),
3689 (unsigned int)HWP_LOWEST_PERF(msr));
3691 if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
3694 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx "
3695 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n",
3697 (unsigned int)(((msr) >> 0) & 0xff),
3698 (unsigned int)(((msr) >> 8) & 0xff),
3699 (unsigned int)(((msr) >> 16) & 0xff),
3700 (unsigned int)(((msr) >> 24) & 0xff),
3701 (unsigned int)(((msr) >> 32) & 0xff3),
3702 (unsigned int)(((msr) >> 42) & 0x1));
3705 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
3708 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx "
3709 "(min %d max %d des %d epp 0x%x window 0x%x)\n",
3711 (unsigned int)(((msr) >> 0) & 0xff),
3712 (unsigned int)(((msr) >> 8) & 0xff),
3713 (unsigned int)(((msr) >> 16) & 0xff),
3714 (unsigned int)(((msr) >> 24) & 0xff),
3715 (unsigned int)(((msr) >> 32) & 0xff3));
3717 if (has_hwp_notify) {
3718 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
3721 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx "
3722 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n",
3724 ((msr) & 0x1) ? "EN" : "Dis",
3725 ((msr) & 0x2) ? "EN" : "Dis");
3727 if (get_msr(cpu, MSR_HWP_STATUS, &msr))
3730 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx "
3731 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n",
3733 ((msr) & 0x1) ? "" : "No-",
3734 ((msr) & 0x2) ? "" : "No-");
3740 * print_perf_limit()
3742 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3744 unsigned long long msr;
3750 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
3753 if (cpu_migrate(cpu)) {
3754 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3758 if (do_core_perf_limit_reasons) {
3759 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
3760 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
3761 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)",
3762 (msr & 1 << 15) ? "bit15, " : "",
3763 (msr & 1 << 14) ? "bit14, " : "",
3764 (msr & 1 << 13) ? "Transitions, " : "",
3765 (msr & 1 << 12) ? "MultiCoreTurbo, " : "",
3766 (msr & 1 << 11) ? "PkgPwrL2, " : "",
3767 (msr & 1 << 10) ? "PkgPwrL1, " : "",
3768 (msr & 1 << 9) ? "CorePwr, " : "",
3769 (msr & 1 << 8) ? "Amps, " : "",
3770 (msr & 1 << 6) ? "VR-Therm, " : "",
3771 (msr & 1 << 5) ? "Auto-HWP, " : "",
3772 (msr & 1 << 4) ? "Graphics, " : "",
3773 (msr & 1 << 2) ? "bit2, " : "",
3774 (msr & 1 << 1) ? "ThermStatus, " : "",
3775 (msr & 1 << 0) ? "PROCHOT, " : "");
3776 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
3777 (msr & 1 << 31) ? "bit31, " : "",
3778 (msr & 1 << 30) ? "bit30, " : "",
3779 (msr & 1 << 29) ? "Transitions, " : "",
3780 (msr & 1 << 28) ? "MultiCoreTurbo, " : "",
3781 (msr & 1 << 27) ? "PkgPwrL2, " : "",
3782 (msr & 1 << 26) ? "PkgPwrL1, " : "",
3783 (msr & 1 << 25) ? "CorePwr, " : "",
3784 (msr & 1 << 24) ? "Amps, " : "",
3785 (msr & 1 << 22) ? "VR-Therm, " : "",
3786 (msr & 1 << 21) ? "Auto-HWP, " : "",
3787 (msr & 1 << 20) ? "Graphics, " : "",
3788 (msr & 1 << 18) ? "bit18, " : "",
3789 (msr & 1 << 17) ? "ThermStatus, " : "",
3790 (msr & 1 << 16) ? "PROCHOT, " : "");
3793 if (do_gfx_perf_limit_reasons) {
3794 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
3795 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
3796 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)",
3797 (msr & 1 << 0) ? "PROCHOT, " : "",
3798 (msr & 1 << 1) ? "ThermStatus, " : "",
3799 (msr & 1 << 4) ? "Graphics, " : "",
3800 (msr & 1 << 6) ? "VR-Therm, " : "",
3801 (msr & 1 << 8) ? "Amps, " : "",
3802 (msr & 1 << 9) ? "GFXPwr, " : "",
3803 (msr & 1 << 10) ? "PkgPwrL1, " : "",
3804 (msr & 1 << 11) ? "PkgPwrL2, " : "");
3805 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n",
3806 (msr & 1 << 16) ? "PROCHOT, " : "",
3807 (msr & 1 << 17) ? "ThermStatus, " : "",
3808 (msr & 1 << 20) ? "Graphics, " : "",
3809 (msr & 1 << 22) ? "VR-Therm, " : "",
3810 (msr & 1 << 24) ? "Amps, " : "",
3811 (msr & 1 << 25) ? "GFXPwr, " : "",
3812 (msr & 1 << 26) ? "PkgPwrL1, " : "",
3813 (msr & 1 << 27) ? "PkgPwrL2, " : "");
3815 if (do_ring_perf_limit_reasons) {
3816 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
3817 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
3818 fprintf(outf, " (Active: %s%s%s%s%s%s)",
3819 (msr & 1 << 0) ? "PROCHOT, " : "",
3820 (msr & 1 << 1) ? "ThermStatus, " : "",
3821 (msr & 1 << 6) ? "VR-Therm, " : "",
3822 (msr & 1 << 8) ? "Amps, " : "",
3823 (msr & 1 << 10) ? "PkgPwrL1, " : "",
3824 (msr & 1 << 11) ? "PkgPwrL2, " : "");
3825 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n",
3826 (msr & 1 << 16) ? "PROCHOT, " : "",
3827 (msr & 1 << 17) ? "ThermStatus, " : "",
3828 (msr & 1 << 22) ? "VR-Therm, " : "",
3829 (msr & 1 << 24) ? "Amps, " : "",
3830 (msr & 1 << 26) ? "PkgPwrL1, " : "",
3831 (msr & 1 << 27) ? "PkgPwrL2, " : "");
3836 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */
3837 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */
3839 double get_tdp_intel(unsigned int model)
3841 unsigned long long msr;
3843 if (do_rapl & RAPL_PKG_POWER_INFO)
3844 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr))
3845 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
3848 case INTEL_FAM6_ATOM_SILVERMONT:
3849 case INTEL_FAM6_ATOM_SILVERMONT_D:
3856 double get_tdp_amd(unsigned int family)
3862 /* This is the max stock TDP of HEDT/Server Fam17h chips */
3868 * rapl_dram_energy_units_probe()
3869 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR.
3872 rapl_dram_energy_units_probe(int model, double rapl_energy_units)
3874 /* only called for genuine_intel, family 6 */
3877 case INTEL_FAM6_HASWELL_X: /* HSX */
3878 case INTEL_FAM6_BROADWELL_X: /* BDX */
3879 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
3880 return (rapl_dram_energy_units = 15.3 / 1000000);
3882 return (rapl_energy_units);
3886 void rapl_probe_intel(unsigned int family, unsigned int model)
3888 unsigned long long msr;
3889 unsigned int time_unit;
3896 case INTEL_FAM6_SANDYBRIDGE:
3897 case INTEL_FAM6_IVYBRIDGE:
3898 case INTEL_FAM6_HASWELL: /* HSW */
3899 case INTEL_FAM6_HASWELL_L: /* HSW */
3900 case INTEL_FAM6_HASWELL_G: /* HSW */
3901 case INTEL_FAM6_BROADWELL: /* BDW */
3902 case INTEL_FAM6_BROADWELL_G: /* BDW */
3903 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
3905 BIC_PRESENT(BIC_Pkg_J);
3906 BIC_PRESENT(BIC_Cor_J);
3907 BIC_PRESENT(BIC_GFX_J);
3909 BIC_PRESENT(BIC_PkgWatt);
3910 BIC_PRESENT(BIC_CorWatt);
3911 BIC_PRESENT(BIC_GFXWatt);
3914 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3915 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
3916 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO;
3918 BIC_PRESENT(BIC_Pkg_J);
3920 BIC_PRESENT(BIC_PkgWatt);
3922 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
3923 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_GFX | RAPL_PKG_POWER_INFO;
3925 BIC_PRESENT(BIC_Pkg_J);
3926 BIC_PRESENT(BIC_Cor_J);
3927 BIC_PRESENT(BIC_RAM_J);
3928 BIC_PRESENT(BIC_GFX_J);
3930 BIC_PRESENT(BIC_PkgWatt);
3931 BIC_PRESENT(BIC_CorWatt);
3932 BIC_PRESENT(BIC_RAMWatt);
3933 BIC_PRESENT(BIC_GFXWatt);
3936 case INTEL_FAM6_SKYLAKE_L: /* SKL */
3937 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
3938 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_GFX | RAPL_PKG_POWER_INFO;
3939 BIC_PRESENT(BIC_PKG__);
3940 BIC_PRESENT(BIC_RAM__);
3942 BIC_PRESENT(BIC_Pkg_J);
3943 BIC_PRESENT(BIC_Cor_J);
3944 BIC_PRESENT(BIC_RAM_J);
3945 BIC_PRESENT(BIC_GFX_J);
3947 BIC_PRESENT(BIC_PkgWatt);
3948 BIC_PRESENT(BIC_CorWatt);
3949 BIC_PRESENT(BIC_RAMWatt);
3950 BIC_PRESENT(BIC_GFXWatt);
3953 case INTEL_FAM6_HASWELL_X: /* HSX */
3954 case INTEL_FAM6_BROADWELL_X: /* BDX */
3955 case INTEL_FAM6_SKYLAKE_X: /* SKX */
3956 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
3957 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
3958 BIC_PRESENT(BIC_PKG__);
3959 BIC_PRESENT(BIC_RAM__);
3961 BIC_PRESENT(BIC_Pkg_J);
3962 BIC_PRESENT(BIC_RAM_J);
3964 BIC_PRESENT(BIC_PkgWatt);
3965 BIC_PRESENT(BIC_RAMWatt);
3968 case INTEL_FAM6_SANDYBRIDGE_X:
3969 case INTEL_FAM6_IVYBRIDGE_X:
3970 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
3971 BIC_PRESENT(BIC_PKG__);
3972 BIC_PRESENT(BIC_RAM__);
3974 BIC_PRESENT(BIC_Pkg_J);
3975 BIC_PRESENT(BIC_Cor_J);
3976 BIC_PRESENT(BIC_RAM_J);
3978 BIC_PRESENT(BIC_PkgWatt);
3979 BIC_PRESENT(BIC_CorWatt);
3980 BIC_PRESENT(BIC_RAMWatt);
3983 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
3984 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
3985 do_rapl = RAPL_PKG | RAPL_CORES;
3987 BIC_PRESENT(BIC_Pkg_J);
3988 BIC_PRESENT(BIC_Cor_J);
3990 BIC_PRESENT(BIC_PkgWatt);
3991 BIC_PRESENT(BIC_CorWatt);
3994 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
3995 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS;
3996 BIC_PRESENT(BIC_PKG__);
3997 BIC_PRESENT(BIC_RAM__);
3999 BIC_PRESENT(BIC_Pkg_J);
4000 BIC_PRESENT(BIC_Cor_J);
4001 BIC_PRESENT(BIC_RAM_J);
4003 BIC_PRESENT(BIC_PkgWatt);
4004 BIC_PRESENT(BIC_CorWatt);
4005 BIC_PRESENT(BIC_RAMWatt);
4012 /* units on package 0, verify later other packages match */
4013 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr))
4016 rapl_power_units = 1.0 / (1 << (msr & 0xF));
4017 if (model == INTEL_FAM6_ATOM_SILVERMONT)
4018 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
4020 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
4022 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units);
4024 time_unit = msr >> 16 & 0xF;
4028 rapl_time_units = 1.0 / (1 << (time_unit));
4030 tdp = get_tdp_intel(model);
4032 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
4034 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
4037 void rapl_probe_amd(unsigned int family, unsigned int model)
4039 unsigned long long msr;
4040 unsigned int eax, ebx, ecx, edx;
4041 unsigned int has_rapl = 0;
4044 if (max_extended_level >= 0x80000007) {
4045 __cpuid(0x80000007, eax, ebx, ecx, edx);
4046 /* RAPL (Fam 17h) */
4047 has_rapl = edx & (1 << 14);
4054 case 0x17: /* Zen, Zen+ */
4055 case 0x18: /* Hygon Dhyana */
4056 do_rapl = RAPL_AMD_F17H | RAPL_PER_CORE_ENERGY;
4058 BIC_PRESENT(BIC_Pkg_J);
4059 BIC_PRESENT(BIC_Cor_J);
4061 BIC_PRESENT(BIC_PkgWatt);
4062 BIC_PRESENT(BIC_CorWatt);
4069 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr))
4072 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf));
4073 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f));
4074 rapl_power_units = ldexp(1.0, -(msr & 0xf));
4076 tdp = get_tdp_amd(family);
4078 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
4080 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
4086 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units
4088 void rapl_probe(unsigned int family, unsigned int model)
4091 rapl_probe_intel(family, model);
4092 if (authentic_amd || hygon_genuine)
4093 rapl_probe_amd(family, model);
4096 void perf_limit_reasons_probe(unsigned int family, unsigned int model)
4105 case INTEL_FAM6_HASWELL: /* HSW */
4106 case INTEL_FAM6_HASWELL_L: /* HSW */
4107 case INTEL_FAM6_HASWELL_G: /* HSW */
4108 do_gfx_perf_limit_reasons = 1;
4109 case INTEL_FAM6_HASWELL_X: /* HSX */
4110 do_core_perf_limit_reasons = 1;
4111 do_ring_perf_limit_reasons = 1;
4117 void automatic_cstate_conversion_probe(unsigned int family, unsigned int model)
4119 if (is_skx(family, model) || is_bdx(family, model))
4120 has_automatic_cstate_conversion = 1;
4123 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4125 unsigned long long msr;
4126 unsigned int dts, dts2;
4129 if (!(do_dts || do_ptm))
4134 /* DTS is per-core, no need to print for each thread */
4135 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
4138 if (cpu_migrate(cpu)) {
4139 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
4143 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) {
4144 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
4147 dts = (msr >> 16) & 0x7F;
4148 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n",
4149 cpu, msr, tcc_activation_temp - dts);
4151 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
4154 dts = (msr >> 16) & 0x7F;
4155 dts2 = (msr >> 8) & 0x7F;
4156 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
4157 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
4161 if (do_dts && debug) {
4162 unsigned int resolution;
4164 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
4167 dts = (msr >> 16) & 0x7F;
4168 resolution = (msr >> 27) & 0xF;
4169 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n",
4170 cpu, msr, tcc_activation_temp - dts, resolution);
4172 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
4175 dts = (msr >> 16) & 0x7F;
4176 dts2 = (msr >> 8) & 0x7F;
4177 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
4178 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
4184 void print_power_limit_msr(int cpu, unsigned long long msr, char *label)
4186 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n",
4188 ((msr >> 15) & 1) ? "EN" : "DIS",
4189 ((msr >> 0) & 0x7FFF) * rapl_power_units,
4190 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units,
4191 (((msr >> 16) & 1) ? "EN" : "DIS"));
4196 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4198 unsigned long long msr;
4199 const char *msr_name;
4205 /* RAPL counters are per package, so print only for 1st thread/package */
4206 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4210 if (cpu_migrate(cpu)) {
4211 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
4215 if (do_rapl & RAPL_AMD_F17H) {
4216 msr_name = "MSR_RAPL_PWR_UNIT";
4217 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr))
4220 msr_name = "MSR_RAPL_POWER_UNIT";
4221 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
4225 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr,
4226 rapl_power_units, rapl_energy_units, rapl_time_units);
4228 if (do_rapl & RAPL_PKG_POWER_INFO) {
4230 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
4234 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
4236 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4237 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4238 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4239 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
4242 if (do_rapl & RAPL_PKG) {
4244 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
4247 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n",
4248 cpu, msr, (msr >> 63) & 1 ? "" : "UN");
4250 print_power_limit_msr(cpu, msr, "PKG Limit #1");
4251 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n",
4253 ((msr >> 47) & 1) ? "EN" : "DIS",
4254 ((msr >> 32) & 0x7FFF) * rapl_power_units,
4255 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units,
4256 ((msr >> 48) & 1) ? "EN" : "DIS");
4259 if (do_rapl & RAPL_DRAM_POWER_INFO) {
4260 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
4263 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
4265 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4266 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4267 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4268 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
4270 if (do_rapl & RAPL_DRAM) {
4271 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
4273 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
4274 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
4276 print_power_limit_msr(cpu, msr, "DRAM Limit");
4278 if (do_rapl & RAPL_CORE_POLICY) {
4279 if (get_msr(cpu, MSR_PP0_POLICY, &msr))
4282 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF);
4284 if (do_rapl & RAPL_CORES_POWER_LIMIT) {
4285 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
4287 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",
4288 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
4289 print_power_limit_msr(cpu, msr, "Cores Limit");
4291 if (do_rapl & RAPL_GFX) {
4292 if (get_msr(cpu, MSR_PP1_POLICY, &msr))
4295 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF);
4297 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
4299 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n",
4300 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
4301 print_power_limit_msr(cpu, msr, "GFX Limit");
4307 * SNB adds support for additional MSRs:
4309 * MSR_PKG_C7_RESIDENCY 0x000003fa
4310 * MSR_CORE_C7_RESIDENCY 0x000003fe
4311 * MSR_PKG_C2_RESIDENCY 0x0000060d
4314 int has_snb_msrs(unsigned int family, unsigned int model)
4320 case INTEL_FAM6_SANDYBRIDGE:
4321 case INTEL_FAM6_SANDYBRIDGE_X:
4322 case INTEL_FAM6_IVYBRIDGE: /* IVB */
4323 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
4324 case INTEL_FAM6_HASWELL: /* HSW */
4325 case INTEL_FAM6_HASWELL_X: /* HSW */
4326 case INTEL_FAM6_HASWELL_L: /* HSW */
4327 case INTEL_FAM6_HASWELL_G: /* HSW */
4328 case INTEL_FAM6_BROADWELL: /* BDW */
4329 case INTEL_FAM6_BROADWELL_G: /* BDW */
4330 case INTEL_FAM6_BROADWELL_X: /* BDX */
4331 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4332 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
4333 case INTEL_FAM6_SKYLAKE_X: /* SKX */
4334 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
4335 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
4336 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
4337 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
4344 * HSW ULT added support for C8/C9/C10 MSRs:
4346 * MSR_PKG_C8_RESIDENCY 0x00000630
4347 * MSR_PKG_C9_RESIDENCY 0x00000631
4348 * MSR_PKG_C10_RESIDENCY 0x00000632
4350 * MSR_PKGC8_IRTL 0x00000633
4351 * MSR_PKGC9_IRTL 0x00000634
4352 * MSR_PKGC10_IRTL 0x00000635
4355 int has_c8910_msrs(unsigned int family, unsigned int model)
4361 case INTEL_FAM6_HASWELL_L: /* HSW */
4362 case INTEL_FAM6_BROADWELL: /* BDW */
4363 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4364 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
4365 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
4366 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
4367 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
4374 * SKL adds support for additional MSRS:
4376 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
4377 * MSR_PKG_ANY_CORE_C0_RES 0x00000659
4378 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
4379 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
4381 int has_skl_msrs(unsigned int family, unsigned int model)
4387 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4388 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
4394 int is_slm(unsigned int family, unsigned int model)
4399 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
4400 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
4406 int is_knl(unsigned int family, unsigned int model)
4411 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
4417 int is_cnl(unsigned int family, unsigned int model)
4423 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
4430 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model)
4432 if (is_knl(family, model))
4437 #define SLM_BCLK_FREQS 5
4438 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0};
4440 double slm_bclk(void)
4442 unsigned long long msr = 3;
4446 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr))
4447 fprintf(outf, "SLM BCLK: unknown\n");
4450 if (i >= SLM_BCLK_FREQS) {
4451 fprintf(outf, "SLM BCLK[%d] invalid\n", i);
4454 freq = slm_freq_table[i];
4457 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq);
4462 double discover_bclk(unsigned int family, unsigned int model)
4464 if (has_snb_msrs(family, model) || is_knl(family, model))
4466 else if (is_slm(family, model))
4473 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where
4474 * the Thermal Control Circuit (TCC) activates.
4475 * This is usually equal to tjMax.
4477 * Older processors do not have this MSR, so there we guess,
4478 * but also allow cmdline over-ride with -T.
4480 * Several MSR temperature values are in units of degrees-C
4481 * below this value, including the Digital Thermal Sensor (DTS),
4482 * Package Thermal Management Sensor (PTM), and thermal event thresholds.
4484 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4486 unsigned long long msr;
4487 unsigned int target_c_local;
4490 /* tcc_activation_temp is used only for dts or ptm */
4491 if (!(do_dts || do_ptm))
4494 /* this is a per-package concept */
4495 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4499 if (cpu_migrate(cpu)) {
4500 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
4504 if (tcc_activation_temp_override != 0) {
4505 tcc_activation_temp = tcc_activation_temp_override;
4506 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n",
4507 cpu, tcc_activation_temp);
4511 /* Temperature Target MSR is Nehalem and newer only */
4512 if (!do_nhm_platform_info)
4515 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
4518 target_c_local = (msr >> 16) & 0xFF;
4521 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n",
4522 cpu, msr, target_c_local);
4524 if (!target_c_local)
4527 tcc_activation_temp = target_c_local;
4532 tcc_activation_temp = TJMAX_DEFAULT;
4533 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n",
4534 cpu, tcc_activation_temp);
4539 void decode_feature_control_msr(void)
4541 unsigned long long msr;
4543 if (!get_msr(base_cpu, MSR_IA32_FEAT_CTL, &msr))
4544 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n",
4546 msr & FEAT_CTL_LOCKED ? "" : "UN-",
4547 msr & (1 << 18) ? "SGX" : "");
4550 void decode_misc_enable_msr(void)
4552 unsigned long long msr;
4557 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
4558 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n",
4560 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-",
4561 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-",
4562 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-",
4563 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "",
4564 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : "");
4567 void decode_misc_feature_control(void)
4569 unsigned long long msr;
4571 if (!has_misc_feature_control)
4574 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr))
4575 fprintf(outf, "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n",
4577 msr & (0 << 0) ? "No-" : "",
4578 msr & (1 << 0) ? "No-" : "",
4579 msr & (2 << 0) ? "No-" : "",
4580 msr & (3 << 0) ? "No-" : "");
4583 * Decode MSR_MISC_PWR_MGMT
4585 * Decode the bits according to the Nehalem documentation
4586 * bit[0] seems to continue to have same meaning going forward
4589 void decode_misc_pwr_mgmt_msr(void)
4591 unsigned long long msr;
4593 if (!do_nhm_platform_info)
4596 if (no_MSR_MISC_PWR_MGMT)
4599 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
4600 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
4602 msr & (1 << 0) ? "DIS" : "EN",
4603 msr & (1 << 1) ? "EN" : "DIS",
4604 msr & (1 << 8) ? "EN" : "DIS");
4607 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG
4609 * This MSRs are present on Silvermont processors,
4610 * Intel Atom processor E3000 series (Baytrail), and friends.
4612 void decode_c6_demotion_policy_msr(void)
4614 unsigned long long msr;
4616 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr))
4617 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n",
4618 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
4620 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr))
4621 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n",
4622 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
4626 * When models are the same, for the purpose of turbostat, reuse
4628 unsigned int intel_model_duplicates(unsigned int model)
4632 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
4633 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
4634 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
4635 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */
4636 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */
4637 return INTEL_FAM6_NEHALEM;
4639 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
4640 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
4641 return INTEL_FAM6_NEHALEM_EX;
4643 case INTEL_FAM6_XEON_PHI_KNM:
4644 return INTEL_FAM6_XEON_PHI_KNL;
4646 case INTEL_FAM6_BROADWELL_X:
4647 case INTEL_FAM6_BROADWELL_D: /* BDX-DE */
4648 return INTEL_FAM6_BROADWELL_X;
4650 case INTEL_FAM6_SKYLAKE_L:
4651 case INTEL_FAM6_SKYLAKE:
4652 case INTEL_FAM6_KABYLAKE_L:
4653 case INTEL_FAM6_KABYLAKE:
4654 case INTEL_FAM6_COMETLAKE_L:
4655 case INTEL_FAM6_COMETLAKE:
4656 return INTEL_FAM6_SKYLAKE_L;
4658 case INTEL_FAM6_ICELAKE_L:
4659 case INTEL_FAM6_ICELAKE_NNPI:
4660 case INTEL_FAM6_TIGERLAKE_L:
4661 case INTEL_FAM6_TIGERLAKE:
4662 return INTEL_FAM6_CANNONLAKE_L;
4664 case INTEL_FAM6_ATOM_TREMONT_D:
4665 return INTEL_FAM6_ATOM_GOLDMONT_D;
4667 case INTEL_FAM6_ATOM_TREMONT_L:
4668 return INTEL_FAM6_ATOM_TREMONT;
4670 case INTEL_FAM6_ICELAKE_X:
4671 return INTEL_FAM6_SKYLAKE_X;
4675 void process_cpuid()
4677 unsigned int eax, ebx, ecx, edx;
4678 unsigned int fms, family, model, stepping, ecx_flags, edx_flags;
4679 unsigned int has_turbo;
4681 eax = ebx = ecx = edx = 0;
4683 __cpuid(0, max_level, ebx, ecx, edx);
4685 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
4687 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
4689 else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e)
4693 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ",
4694 (char *)&ebx, (char *)&edx, (char *)&ecx);
4696 __cpuid(1, fms, ebx, ecx, edx);
4697 family = (fms >> 8) & 0xf;
4698 model = (fms >> 4) & 0xf;
4699 stepping = fms & 0xf;
4701 family += (fms >> 20) & 0xff;
4703 model += ((fms >> 16) & 0xf) << 4;
4708 * check max extended function levels of CPUID.
4709 * This is needed to check for invariant TSC.
4710 * This check is valid for both Intel and AMD.
4712 ebx = ecx = edx = 0;
4713 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx);
4716 fprintf(outf, "0x%x CPUID levels; 0x%x xlevels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n",
4717 max_level, max_extended_level, family, model, stepping, family, model, stepping);
4718 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n",
4719 ecx_flags & (1 << 0) ? "SSE3" : "-",
4720 ecx_flags & (1 << 3) ? "MONITOR" : "-",
4721 ecx_flags & (1 << 6) ? "SMX" : "-",
4722 ecx_flags & (1 << 7) ? "EIST" : "-",
4723 ecx_flags & (1 << 8) ? "TM2" : "-",
4724 edx_flags & (1 << 4) ? "TSC" : "-",
4725 edx_flags & (1 << 5) ? "MSR" : "-",
4726 edx_flags & (1 << 22) ? "ACPI-TM" : "-",
4727 edx_flags & (1 << 28) ? "HT" : "-",
4728 edx_flags & (1 << 29) ? "TM" : "-");
4731 model = intel_model_duplicates(model);
4733 if (!(edx_flags & (1 << 5)))
4734 errx(1, "CPUID: no MSR");
4736 if (max_extended_level >= 0x80000007) {
4739 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8
4740 * this check is valid for both Intel and AMD
4742 __cpuid(0x80000007, eax, ebx, ecx, edx);
4743 has_invariant_tsc = edx & (1 << 8);
4747 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0
4748 * this check is valid for both Intel and AMD
4751 __cpuid(0x6, eax, ebx, ecx, edx);
4752 has_aperf = ecx & (1 << 0);
4754 BIC_PRESENT(BIC_Avg_MHz);
4755 BIC_PRESENT(BIC_Busy);
4756 BIC_PRESENT(BIC_Bzy_MHz);
4758 do_dts = eax & (1 << 0);
4760 BIC_PRESENT(BIC_CoreTmp);
4761 has_turbo = eax & (1 << 1);
4762 do_ptm = eax & (1 << 6);
4764 BIC_PRESENT(BIC_PkgTmp);
4765 has_hwp = eax & (1 << 7);
4766 has_hwp_notify = eax & (1 << 8);
4767 has_hwp_activity_window = eax & (1 << 9);
4768 has_hwp_epp = eax & (1 << 10);
4769 has_hwp_pkg = eax & (1 << 11);
4770 has_epb = ecx & (1 << 3);
4773 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, "
4774 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n",
4775 has_aperf ? "" : "No-",
4776 has_turbo ? "" : "No-",
4777 do_dts ? "" : "No-",
4778 do_ptm ? "" : "No-",
4779 has_hwp ? "" : "No-",
4780 has_hwp_notify ? "" : "No-",
4781 has_hwp_activity_window ? "" : "No-",
4782 has_hwp_epp ? "" : "No-",
4783 has_hwp_pkg ? "" : "No-",
4784 has_epb ? "" : "No-");
4787 decode_misc_enable_msr();
4790 if (max_level >= 0x7 && !quiet) {
4795 __cpuid_count(0x7, 0, eax, ebx, ecx, edx);
4797 has_sgx = ebx & (1 << 2);
4798 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-");
4801 decode_feature_control_msr();
4804 if (max_level >= 0x15) {
4805 unsigned int eax_crystal;
4806 unsigned int ebx_tsc;
4809 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz
4811 eax_crystal = ebx_tsc = crystal_hz = edx = 0;
4812 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx);
4816 if (!quiet && (ebx != 0))
4817 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n",
4818 eax_crystal, ebx_tsc, crystal_hz);
4820 if (crystal_hz == 0)
4822 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4823 crystal_hz = 24000000; /* 24.0 MHz */
4825 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
4826 crystal_hz = 25000000; /* 25.0 MHz */
4828 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
4829 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
4830 crystal_hz = 19200000; /* 19.2 MHz */
4837 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal;
4839 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n",
4840 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal);
4844 if (max_level >= 0x16) {
4845 unsigned int base_mhz, max_mhz, bus_mhz, edx;
4848 * CPUID 16H Base MHz, Max MHz, Bus MHz
4850 base_mhz = max_mhz = bus_mhz = edx = 0;
4852 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx);
4854 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n",
4855 base_mhz, max_mhz, bus_mhz);
4859 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model);
4861 BIC_PRESENT(BIC_IRQ);
4862 BIC_PRESENT(BIC_TSC_MHz);
4864 if (probe_nhm_msrs(family, model)) {
4865 do_nhm_platform_info = 1;
4866 BIC_PRESENT(BIC_CPU_c1);
4867 BIC_PRESENT(BIC_CPU_c3);
4868 BIC_PRESENT(BIC_CPU_c6);
4869 BIC_PRESENT(BIC_SMI);
4871 do_snb_cstates = has_snb_msrs(family, model);
4874 BIC_PRESENT(BIC_CPU_c7);
4876 do_irtl_snb = has_snb_msrs(family, model);
4877 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2))
4878 BIC_PRESENT(BIC_Pkgpc2);
4879 if (pkg_cstate_limit >= PCL__3)
4880 BIC_PRESENT(BIC_Pkgpc3);
4881 if (pkg_cstate_limit >= PCL__6)
4882 BIC_PRESENT(BIC_Pkgpc6);
4883 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7))
4884 BIC_PRESENT(BIC_Pkgpc7);
4885 if (has_slv_msrs(family, model)) {
4886 BIC_NOT_PRESENT(BIC_Pkgpc2);
4887 BIC_NOT_PRESENT(BIC_Pkgpc3);
4888 BIC_PRESENT(BIC_Pkgpc6);
4889 BIC_NOT_PRESENT(BIC_Pkgpc7);
4890 BIC_PRESENT(BIC_Mod_c6);
4891 use_c1_residency_msr = 1;
4893 if (is_dnv(family, model)) {
4894 BIC_PRESENT(BIC_CPU_c1);
4895 BIC_NOT_PRESENT(BIC_CPU_c3);
4896 BIC_NOT_PRESENT(BIC_Pkgpc3);
4897 BIC_NOT_PRESENT(BIC_CPU_c7);
4898 BIC_NOT_PRESENT(BIC_Pkgpc7);
4899 use_c1_residency_msr = 1;
4901 if (is_skx(family, model)) {
4902 BIC_NOT_PRESENT(BIC_CPU_c3);
4903 BIC_NOT_PRESENT(BIC_Pkgpc3);
4904 BIC_NOT_PRESENT(BIC_CPU_c7);
4905 BIC_NOT_PRESENT(BIC_Pkgpc7);
4907 if (is_bdx(family, model)) {
4908 BIC_NOT_PRESENT(BIC_CPU_c7);
4909 BIC_NOT_PRESENT(BIC_Pkgpc7);
4911 if (has_c8910_msrs(family, model)) {
4912 BIC_PRESENT(BIC_Pkgpc8);
4913 BIC_PRESENT(BIC_Pkgpc9);
4914 BIC_PRESENT(BIC_Pkgpc10);
4916 do_irtl_hsw = has_c8910_msrs(family, model);
4917 if (has_skl_msrs(family, model)) {
4918 BIC_PRESENT(BIC_Totl_c0);
4919 BIC_PRESENT(BIC_Any_c0);
4920 BIC_PRESENT(BIC_GFX_c0);
4921 BIC_PRESENT(BIC_CPUGFX);
4923 do_slm_cstates = is_slm(family, model);
4924 do_knl_cstates = is_knl(family, model);
4926 if (do_slm_cstates || do_knl_cstates || is_cnl(family, model) ||
4927 is_ehl(family, model))
4928 BIC_NOT_PRESENT(BIC_CPU_c3);
4931 decode_misc_pwr_mgmt_msr();
4933 if (!quiet && has_slv_msrs(family, model))
4934 decode_c6_demotion_policy_msr();
4936 rapl_probe(family, model);
4937 perf_limit_reasons_probe(family, model);
4938 automatic_cstate_conversion_probe(family, model);
4941 dump_cstate_pstate_config_info(family, model);
4944 dump_sysfs_cstate_config();
4946 dump_sysfs_pstate_config();
4948 if (has_skl_msrs(family, model))
4949 calculate_tsc_tweak();
4951 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK))
4952 BIC_PRESENT(BIC_GFX_rc6);
4954 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK))
4955 BIC_PRESENT(BIC_GFXMHz);
4957 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK))
4958 BIC_PRESENT(BIC_CPU_LPI);
4960 BIC_NOT_PRESENT(BIC_CPU_LPI);
4962 if (!access(sys_lpi_file_sysfs, R_OK)) {
4963 sys_lpi_file = sys_lpi_file_sysfs;
4964 BIC_PRESENT(BIC_SYS_LPI);
4965 } else if (!access(sys_lpi_file_debugfs, R_OK)) {
4966 sys_lpi_file = sys_lpi_file_debugfs;
4967 BIC_PRESENT(BIC_SYS_LPI);
4969 sys_lpi_file_sysfs = NULL;
4970 BIC_NOT_PRESENT(BIC_SYS_LPI);
4974 decode_misc_feature_control();
4980 * in /dev/cpu/ return success for names that are numbers
4981 * ie. filter out ".", "..", "microcode".
4983 int dir_filter(const struct dirent *dirp)
4985 if (isdigit(dirp->d_name[0]))
4991 int open_dev_cpu_msr(int dummy1)
4996 void topology_probe()
4999 int max_core_id = 0;
5000 int max_package_id = 0;
5002 int max_siblings = 0;
5004 /* Initialize num_cpus, max_cpu_num */
5007 for_all_proc_cpus(count_cpus);
5008 if (!summary_only && topo.num_cpus > 1)
5009 BIC_PRESENT(BIC_CPU);
5012 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num);
5014 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology));
5016 err(1, "calloc cpus");
5019 * Allocate and initialize cpu_present_set
5021 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1));
5022 if (cpu_present_set == NULL)
5023 err(3, "CPU_ALLOC");
5024 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
5025 CPU_ZERO_S(cpu_present_setsize, cpu_present_set);
5026 for_all_proc_cpus(mark_cpu_present);
5029 * Validate that all cpus in cpu_subset are also in cpu_present_set
5031 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) {
5032 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset))
5033 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set))
5034 err(1, "cpu%d not present", i);
5038 * Allocate and initialize cpu_affinity_set
5040 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1));
5041 if (cpu_affinity_set == NULL)
5042 err(3, "CPU_ALLOC");
5043 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
5044 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
5046 for_all_proc_cpus(init_thread_id);
5050 * find max_core_id, max_package_id
5052 for (i = 0; i <= topo.max_cpu_num; ++i) {
5055 if (cpu_is_not_present(i)) {
5057 fprintf(outf, "cpu%d NOT PRESENT\n", i);
5061 cpus[i].logical_cpu_id = i;
5063 /* get package information */
5064 cpus[i].physical_package_id = get_physical_package_id(i);
5065 if (cpus[i].physical_package_id > max_package_id)
5066 max_package_id = cpus[i].physical_package_id;
5068 /* get die information */
5069 cpus[i].die_id = get_die_id(i);
5070 if (cpus[i].die_id > max_die_id)
5071 max_die_id = cpus[i].die_id;
5073 /* get numa node information */
5074 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]);
5075 if (cpus[i].physical_node_id > topo.max_node_num)
5076 topo.max_node_num = cpus[i].physical_node_id;
5078 /* get core information */
5079 cpus[i].physical_core_id = get_core_id(i);
5080 if (cpus[i].physical_core_id > max_core_id)
5081 max_core_id = cpus[i].physical_core_id;
5083 /* get thread information */
5084 siblings = get_thread_siblings(&cpus[i]);
5085 if (siblings > max_siblings)
5086 max_siblings = siblings;
5087 if (cpus[i].thread_id == 0)
5091 topo.cores_per_node = max_core_id + 1;
5093 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n",
5094 max_core_id, topo.cores_per_node);
5095 if (!summary_only && topo.cores_per_node > 1)
5096 BIC_PRESENT(BIC_Core);
5098 topo.num_die = max_die_id + 1;
5100 fprintf(outf, "max_die_id %d, sizing for %d die\n",
5101 max_die_id, topo.num_die);
5102 if (!summary_only && topo.num_die > 1)
5103 BIC_PRESENT(BIC_Die);
5105 topo.num_packages = max_package_id + 1;
5107 fprintf(outf, "max_package_id %d, sizing for %d packages\n",
5108 max_package_id, topo.num_packages);
5109 if (!summary_only && topo.num_packages > 1)
5110 BIC_PRESENT(BIC_Package);
5114 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg);
5115 if (!summary_only && topo.nodes_per_pkg > 1)
5116 BIC_PRESENT(BIC_Node);
5118 topo.threads_per_core = max_siblings;
5120 fprintf(outf, "max_siblings %d\n", max_siblings);
5125 for (i = 0; i <= topo.max_cpu_num; ++i) {
5126 if (cpu_is_not_present(i))
5129 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n",
5130 i, cpus[i].physical_package_id, cpus[i].die_id,
5131 cpus[i].physical_node_id,
5132 cpus[i].logical_node_id,
5133 cpus[i].physical_core_id,
5140 allocate_counters(struct thread_data **t, struct core_data **c,
5141 struct pkg_data **p)
5144 int num_cores = topo.cores_per_node * topo.nodes_per_pkg *
5146 int num_threads = topo.threads_per_core * num_cores;
5148 *t = calloc(num_threads, sizeof(struct thread_data));
5152 for (i = 0; i < num_threads; i++)
5153 (*t)[i].cpu_id = -1;
5155 *c = calloc(num_cores, sizeof(struct core_data));
5159 for (i = 0; i < num_cores; i++)
5160 (*c)[i].core_id = -1;
5162 *p = calloc(topo.num_packages, sizeof(struct pkg_data));
5166 for (i = 0; i < topo.num_packages; i++)
5167 (*p)[i].package_id = i;
5171 err(1, "calloc counters");
5176 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE
5178 void init_counter(struct thread_data *thread_base, struct core_data *core_base,
5179 struct pkg_data *pkg_base, int cpu_id)
5181 int pkg_id = cpus[cpu_id].physical_package_id;
5182 int node_id = cpus[cpu_id].logical_node_id;
5183 int core_id = cpus[cpu_id].physical_core_id;
5184 int thread_id = cpus[cpu_id].thread_id;
5185 struct thread_data *t;
5186 struct core_data *c;
5190 /* Workaround for systems where physical_node_id==-1
5191 * and logical_node_id==(-1 - topo.num_cpus)
5196 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id);
5197 c = GET_CORE(core_base, core_id, node_id, pkg_id);
5198 p = GET_PKG(pkg_base, pkg_id);
5201 if (thread_id == 0) {
5202 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE;
5203 if (cpu_is_first_core_in_package(cpu_id))
5204 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE;
5207 c->core_id = core_id;
5208 p->package_id = pkg_id;
5212 int initialize_counters(int cpu_id)
5214 init_counter(EVEN_COUNTERS, cpu_id);
5215 init_counter(ODD_COUNTERS, cpu_id);
5219 void allocate_output_buffer()
5221 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048);
5222 outp = output_buffer;
5224 err(-1, "calloc output buffer");
5226 void allocate_fd_percpu(void)
5228 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
5229 if (fd_percpu == NULL)
5230 err(-1, "calloc fd_percpu");
5232 void allocate_irq_buffers(void)
5234 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int));
5235 if (irq_column_2_cpu == NULL)
5236 err(-1, "calloc %d", topo.num_cpus);
5238 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int));
5239 if (irqs_per_cpu == NULL)
5240 err(-1, "calloc %d", topo.max_cpu_num + 1);
5242 void setup_all_buffers(void)
5245 allocate_irq_buffers();
5246 allocate_fd_percpu();
5247 allocate_counters(&thread_even, &core_even, &package_even);
5248 allocate_counters(&thread_odd, &core_odd, &package_odd);
5249 allocate_output_buffer();
5250 for_all_proc_cpus(initialize_counters);
5253 void set_base_cpu(void)
5255 base_cpu = sched_getcpu();
5257 err(-ENODEV, "No valid cpus found");
5260 fprintf(outf, "base_cpu = %d\n", base_cpu);
5263 void turbostat_init()
5265 setup_all_buffers();
5268 check_permissions();
5273 for_all_cpus(print_hwp, ODD_COUNTERS);
5276 for_all_cpus(print_epb, ODD_COUNTERS);
5279 for_all_cpus(print_perf_limit, ODD_COUNTERS);
5282 for_all_cpus(print_rapl, ODD_COUNTERS);
5284 for_all_cpus(set_temperature_target, ODD_COUNTERS);
5287 for_all_cpus(print_thermal, ODD_COUNTERS);
5289 if (!quiet && do_irtl_snb)
5293 int fork_it(char **argv)
5298 snapshot_proc_sysfs_files();
5299 status = for_all_cpus(get_counters, EVEN_COUNTERS);
5300 first_counter_read = 0;
5303 /* clear affinity side-effect of get_counters() */
5304 sched_setaffinity(0, cpu_present_setsize, cpu_present_set);
5305 gettimeofday(&tv_even, (struct timezone *)NULL);
5310 execvp(argv[0], argv);
5311 err(errno, "exec %s", argv[0]);
5315 if (child_pid == -1)
5318 signal(SIGINT, SIG_IGN);
5319 signal(SIGQUIT, SIG_IGN);
5320 if (waitpid(child_pid, &status, 0) == -1)
5321 err(status, "waitpid");
5323 if (WIFEXITED(status))
5324 status = WEXITSTATUS(status);
5327 * n.b. fork_it() does not check for errors from for_all_cpus()
5328 * because re-starting is problematic when forking
5330 snapshot_proc_sysfs_files();
5331 for_all_cpus(get_counters, ODD_COUNTERS);
5332 gettimeofday(&tv_odd, (struct timezone *)NULL);
5333 timersub(&tv_odd, &tv_even, &tv_delta);
5334 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS))
5335 fprintf(outf, "%s: Counter reset detected\n", progname);
5337 compute_average(EVEN_COUNTERS);
5338 format_all_counters(EVEN_COUNTERS);
5341 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0);
5343 flush_output_stderr();
5348 int get_and_dump_counters(void)
5352 snapshot_proc_sysfs_files();
5353 status = for_all_cpus(get_counters, ODD_COUNTERS);
5357 status = for_all_cpus(dump_counters, ODD_COUNTERS);
5361 flush_output_stdout();
5366 void print_version() {
5367 fprintf(outf, "turbostat version 19.08.31"
5368 " - Len Brown <lenb@kernel.org>\n");
5371 int add_counter(unsigned int msr_num, char *path, char *name,
5372 unsigned int width, enum counter_scope scope,
5373 enum counter_type type, enum counter_format format, int flags)
5375 struct msr_counter *msrp;
5377 msrp = calloc(1, sizeof(struct msr_counter));
5383 msrp->msr_num = msr_num;
5384 strncpy(msrp->name, name, NAME_BYTES - 1);
5386 strncpy(msrp->path, path, PATH_BYTES - 1);
5387 msrp->width = width;
5389 msrp->format = format;
5390 msrp->flags = flags;
5395 msrp->next = sys.tp;
5397 sys.added_thread_counters++;
5398 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) {
5399 fprintf(stderr, "exceeded max %d added thread counters\n",
5400 MAX_ADDED_COUNTERS);
5406 msrp->next = sys.cp;
5408 sys.added_core_counters++;
5409 if (sys.added_core_counters > MAX_ADDED_COUNTERS) {
5410 fprintf(stderr, "exceeded max %d added core counters\n",
5411 MAX_ADDED_COUNTERS);
5417 msrp->next = sys.pp;
5419 sys.added_package_counters++;
5420 if (sys.added_package_counters > MAX_ADDED_COUNTERS) {
5421 fprintf(stderr, "exceeded max %d added package counters\n",
5422 MAX_ADDED_COUNTERS);
5431 void parse_add_command(char *add_command)
5435 char name_buffer[NAME_BYTES] = "";
5438 enum counter_scope scope = SCOPE_CPU;
5439 enum counter_type type = COUNTER_CYCLES;
5440 enum counter_format format = FORMAT_DELTA;
5442 while (add_command) {
5444 if (sscanf(add_command, "msr0x%x", &msr_num) == 1)
5447 if (sscanf(add_command, "msr%d", &msr_num) == 1)
5450 if (*add_command == '/') {
5455 if (sscanf(add_command, "u%d", &width) == 1) {
5456 if ((width == 32) || (width == 64))
5460 if (!strncmp(add_command, "cpu", strlen("cpu"))) {
5464 if (!strncmp(add_command, "core", strlen("core"))) {
5468 if (!strncmp(add_command, "package", strlen("package"))) {
5469 scope = SCOPE_PACKAGE;
5472 if (!strncmp(add_command, "cycles", strlen("cycles"))) {
5473 type = COUNTER_CYCLES;
5476 if (!strncmp(add_command, "seconds", strlen("seconds"))) {
5477 type = COUNTER_SECONDS;
5480 if (!strncmp(add_command, "usec", strlen("usec"))) {
5481 type = COUNTER_USEC;
5484 if (!strncmp(add_command, "raw", strlen("raw"))) {
5485 format = FORMAT_RAW;
5488 if (!strncmp(add_command, "delta", strlen("delta"))) {
5489 format = FORMAT_DELTA;
5492 if (!strncmp(add_command, "percent", strlen("percent"))) {
5493 format = FORMAT_PERCENT;
5497 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */
5500 eos = strchr(name_buffer, ',');
5507 add_command = strchr(add_command, ',');
5509 *add_command = '\0';
5514 if ((msr_num == 0) && (path == NULL)) {
5515 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n");
5519 /* generate default column header */
5520 if (*name_buffer == '\0') {
5522 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
5524 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
5527 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0))
5536 int is_deferred_skip(char *name)
5540 for (i = 0; i < deferred_skip_index; ++i)
5541 if (!strcmp(name, deferred_skip_names[i]))
5546 void probe_sysfs(void)
5554 if (!DO_BIC(BIC_sysfs))
5557 for (state = 10; state >= 0; --state) {
5559 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name",
5561 input = fopen(path, "r");
5564 if (!fgets(name_buf, sizeof(name_buf), input))
5565 err(1, "%s: failed to read file", path);
5567 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
5568 sp = strchr(name_buf, '-');
5570 sp = strchrnul(name_buf, '\n');
5576 sprintf(path, "cpuidle/state%d/time", state);
5578 if (is_deferred_skip(name_buf))
5581 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC,
5582 FORMAT_PERCENT, SYSFS_PERCPU);
5585 for (state = 10; state >= 0; --state) {
5587 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name",
5589 input = fopen(path, "r");
5592 if (!fgets(name_buf, sizeof(name_buf), input))
5593 err(1, "%s: failed to read file", path);
5594 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
5595 sp = strchr(name_buf, '-');
5597 sp = strchrnul(name_buf, '\n');
5601 sprintf(path, "cpuidle/state%d/usage", state);
5603 if (is_deferred_skip(name_buf))
5606 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS,
5607 FORMAT_DELTA, SYSFS_PERCPU);
5614 * parse cpuset with following syntax
5615 * 1,2,4..6,8-10 and set bits in cpu_subset
5617 void parse_cpu_command(char *optarg)
5619 unsigned int start, end;
5622 if (!strcmp(optarg, "core")) {
5628 if (!strcmp(optarg, "package")) {
5634 if (show_core_only || show_pkg_only)
5637 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS);
5638 if (cpu_subset == NULL)
5639 err(3, "CPU_ALLOC");
5640 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS);
5642 CPU_ZERO_S(cpu_subset_size, cpu_subset);
5646 while (next && *next) {
5648 if (*next == '-') /* no negative cpu numbers */
5651 start = strtoul(next, &next, 10);
5653 if (start >= CPU_SUBSET_MAXCPUS)
5655 CPU_SET_S(start, cpu_subset_size, cpu_subset);
5666 next += 1; /* start range */
5667 } else if (*next == '.') {
5670 next += 1; /* start range */
5675 end = strtoul(next, &next, 10);
5679 while (++start <= end) {
5680 if (start >= CPU_SUBSET_MAXCPUS)
5682 CPU_SET_S(start, cpu_subset_size, cpu_subset);
5687 else if (*next != '\0')
5694 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg);
5700 void cmdline(int argc, char **argv)
5703 int option_index = 0;
5704 static struct option long_options[] = {
5705 {"add", required_argument, 0, 'a'},
5706 {"cpu", required_argument, 0, 'c'},
5707 {"Dump", no_argument, 0, 'D'},
5708 {"debug", no_argument, 0, 'd'}, /* internal, not documented */
5709 {"enable", required_argument, 0, 'e'},
5710 {"interval", required_argument, 0, 'i'},
5711 {"num_iterations", required_argument, 0, 'n'},
5712 {"help", no_argument, 0, 'h'},
5713 {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help
5714 {"Joules", no_argument, 0, 'J'},
5715 {"list", no_argument, 0, 'l'},
5716 {"out", required_argument, 0, 'o'},
5717 {"quiet", no_argument, 0, 'q'},
5718 {"show", required_argument, 0, 's'},
5719 {"Summary", no_argument, 0, 'S'},
5720 {"TCC", required_argument, 0, 'T'},
5721 {"version", no_argument, 0, 'v' },
5727 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v",
5728 long_options, &option_index)) != -1) {
5731 parse_add_command(optarg);
5734 parse_cpu_command(optarg);
5740 /* --enable specified counter */
5741 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST);
5745 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT);
5749 * --hide: do not show those specified
5750 * multiple invocations simply clear more bits in enabled mask
5752 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST);
5760 double interval = strtod(optarg, NULL);
5762 if (interval < 0.001) {
5763 fprintf(outf, "interval %f seconds is too small\n",
5768 interval_tv.tv_sec = interval_ts.tv_sec = interval;
5769 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000;
5770 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000;
5777 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT);
5782 outf = fopen_or_die(optarg, "w");
5788 num_iterations = strtod(optarg, NULL);
5790 if (num_iterations <= 0) {
5791 fprintf(outf, "iterations %d should be positive number\n",
5798 * --show: show only those specified
5799 * The 1st invocation will clear and replace the enabled mask
5800 * subsequent invocations can add to it.
5803 bic_enabled = bic_lookup(optarg, SHOW_LIST);
5805 bic_enabled |= bic_lookup(optarg, SHOW_LIST);
5812 tcc_activation_temp_override = atoi(optarg);
5822 int main(int argc, char **argv)
5825 cmdline(argc, argv);
5834 /* dump counters and exit */
5836 return get_and_dump_counters();
5838 /* list header and exit */
5839 if (list_header_only) {
5841 flush_output_stdout();
5846 * if any params left, it must be a command to fork
5849 return fork_it(argv + optind);