3 turbostat \- Report processor frequency and idle statistics
12 .RB [ "\-i interval_sec" ]
14 \fBturbostat \fP reports processor topology, frequency,
15 idle power-state statistics, temperature and power on modern X86 processors.
16 Either \fBcommand\fP is forked and statistics are printed
17 upon its completion, or statistics are printed periodically.
20 must be run on root, and
21 minimally requires that the processor
22 supports an "invariant" TSC, plus the APERF and MPERF MSRs.
23 Additional information is reported depending on hardware counter support.
26 The \fB-p\fP option limits output to the 1st thread in 1st core of each package.
28 The \fB-P\fP option limits output to the 1st thread in each Package.
30 The \fB-S\fP option limits output to a 1-line System Summary for each interval.
32 The \fB-v\fP option increases verbosity.
34 The \fB-c MSR#\fP option includes the delta of the specified 32-bit MSR counter.
36 The \fB-C MSR#\fP option includes the delta of the specified 64-bit MSR counter.
38 The \fB-m MSR#\fP option includes the the specified 32-bit MSR value.
40 The \fB-M MSR#\fP option includes the the specified 64-bit MSR value.
42 The \fB-i interval_sec\fP option prints statistics every \fiinterval_sec\fP seconds.
43 The default is 5 seconds.
45 The \fBcommand\fP parameter forks \fBcommand\fP and upon its exit,
46 displays the statistics gathered since it was forked.
48 .SH FIELD DESCRIPTIONS
50 \fBPackage\fP processor package number.
51 \fBCore\fP processor core number.
52 \fBCPU\fP Linux CPU (logical processor) number.
53 Note that multiple CPUs per core indicate support for Intel(R) Hyper-Threading Technology.
54 \fBAVG_MHz\fP number of cycles executed divided by time elapsed.
55 \fB%Buzy\fP percent of the interval that the CPU retired instructions, aka. % of time in "C0" state.
56 \fBBzy_MHz\fP average clock rate while the CPU was busy (in "c0" state).
57 \fBTSC_MHz\fP average MHz that the TSC ran during the entire interval.
58 \fBCPU%c1, CPU%c3, CPU%c6, CPU%c7\fP show the percentage residency in hardware core idle states.
59 \fBCoreTmp\fP Degrees Celsius reported by the per-core Digital Thermal Sensor.
60 \fBPkgTtmp\fP Degrees Celsius reported by the per-package Package Thermal Monitor.
61 \fBPkg%pc2, Pkg%pc3, Pkg%pc6, Pkg%pc7\fP percentage residency in hardware package idle states.
62 \fBPkgWatt\fP Watts consumed by the whole package.
63 \fBCorWatt\fP Watts consumed by the core part of the package.
64 \fBGFXWatt\fP Watts consumed by the Graphics part of the package -- available only on client processors.
65 \fBRAMWatt\fP Watts consumed by the DRAM DIMMS -- available only on server processors.
66 \fBPKG_%\fP percent of the interval that RAPL throttling was active on the Package.
67 \fBRAM_%\fP percent of the interval that RAPL throttling was active on DRAM.
71 Without any parameters, turbostat prints out counters ever 5 seconds.
72 (override interval with "-i sec" option, or specify a command
73 for turbostat to fork).
75 The first row of statistics is a summary for the entire system.
76 For residency % columns, the summary is a weighted average.
77 For Temperature columns, the summary is the column maximum.
78 For Watts columns, the summary is a system total.
79 Subsequent rows show per-CPU statistics.
82 [root@ivy]# ./turbostat
83 Core CPU Avg_MHz %Busy Bzy_MHz TSC_MHz SMI CPU%c1 CPU%c3 CPU%c6 CPU%c7 CoreTmp PkgTmp Pkg%pc2 Pkg%pc3 Pkg%pc6 Pkg%pc7 PkgWatt CorWatt GFXWatt
84 - - 6 0.36 1596 3492 0 0.59 0.01 99.04 0.00 23 24 23.82 0.01 72.47 0.00 6.40 1.01 0.00
85 0 0 9 0.58 1596 3492 0 0.28 0.01 99.13 0.00 23 24 23.82 0.01 72.47 0.00 6.40 1.01 0.00
86 0 4 1 0.07 1596 3492 0 0.79
87 1 1 10 0.65 1596 3492 0 0.59 0.00 98.76 0.00 23
88 1 5 5 0.28 1596 3492 0 0.95
89 2 2 10 0.66 1596 3492 0 0.41 0.01 98.92 0.00 23
90 2 6 2 0.10 1597 3492 0 0.97
91 3 3 3 0.20 1596 3492 0 0.44 0.00 99.37 0.00 23
92 3 7 5 0.31 1596 3492 0 0.33
95 The "-v" option adds verbosity to the output:
98 [root@ivy]# turbostat -v
99 turbostat v3.0 November 23, 2012 - Len Brown <lenb@kernel.org>
100 CPUID(0): GenuineIntel 13 CPUID levels; family:model:stepping 0x6:3a:9 (6:58:9)
101 CPUID(6): APERF, DTS, PTM, EPB
102 RAPL: 851 sec. Joule Counter Range
103 cpu0: MSR_NHM_PLATFORM_INFO: 0x81010f0012300
104 16 * 100 = 1600 MHz max efficiency
105 35 * 100 = 3500 MHz TSC frequency
106 cpu0: MSR_NHM_SNB_PKG_CST_CFG_CTL: 0x1e008402 (UNdemote-C3, UNdemote-C1, demote-C3, demote-C1, locked: pkg-cstate-limit=2: pc6-noret)
107 cpu0: MSR_NHM_TURBO_RATIO_LIMIT: 0x25262727
108 37 * 100 = 3700 MHz max turbo 4 active cores
109 38 * 100 = 3800 MHz max turbo 3 active cores
110 39 * 100 = 3900 MHz max turbo 2 active cores
111 39 * 100 = 3900 MHz max turbo 1 active cores
112 cpu0: MSR_IA32_ENERGY_PERF_BIAS: 0x00000006 (balanced)
113 cpu0: MSR_RAPL_POWER_UNIT: 0x000a1003 (0.125000 Watts, 0.000015 Joules, 0.000977 sec.)
114 cpu0: MSR_PKG_POWER_INFO: 0x01e00268 (77 W TDP, RAPL 60 - 0 W, 0.000000 sec.)
115 cpu0: MSR_PKG_POWER_LIMIT: 0x830000148268 (UNlocked)
116 cpu0: PKG Limit #1: ENabled (77.000000 Watts, 1.000000 sec, clamp DISabled)
117 cpu0: PKG Limit #2: ENabled (96.000000 Watts, 0.000977* sec, clamp DISabled)
118 cpu0: MSR_PP0_POLICY: 0
119 cpu0: MSR_PP0_POWER_LIMIT: 0x00000000 (UNlocked)
120 cpu0: Cores Limit: DISabled (0.000000 Watts, 0.000977 sec, clamp DISabled)
121 cpu0: MSR_PP1_POLICY: 0
122 cpu0: MSR_PP1_POWER_LIMIT: 0x00000000 (UNlocked)
123 cpu0: GFX Limit: DISabled (0.000000 Watts, 0.000977 sec, clamp DISabled)
124 cpu0: MSR_IA32_TEMPERATURE_TARGET: 0x00691400 (105 C)
125 cpu0: MSR_IA32_PACKAGE_THERM_STATUS: 0x884e0000 (27 C)
126 cpu0: MSR_IA32_THERM_STATUS: 0x88560000 (19 C +/- 1)
127 cpu1: MSR_IA32_THERM_STATUS: 0x88560000 (19 C +/- 1)
128 cpu2: MSR_IA32_THERM_STATUS: 0x88540000 (21 C +/- 1)
129 cpu3: MSR_IA32_THERM_STATUS: 0x884e0000 (27 C +/- 1)
132 The \fBmax efficiency\fP frequency, a.k.a. Low Frequency Mode, is the frequency
133 available at the minimum package voltage. The \fBTSC frequency\fP is the nominal
134 maximum frequency of the processor if turbo-mode were not available. This frequency
135 should be sustainable on all CPUs indefinitely, given nominal power and cooling.
136 The remaining rows show what maximum turbo frequency is possible
137 depending on the number of idle cores. Note that this information is
138 not available on all processors.
140 If turbostat is invoked with a command, it will fork that command
141 and output the statistics gathered when the command exits.
142 eg. Here a cycle soaker is run on 1 CPU (see %c0) for a few seconds
143 until ^C while the other CPUs are mostly idle:
146 root@ivy: turbostat cat /dev/zero > /dev/null
148 Core CPU Avg_MHz %Busy Bzy_MHz TSC_MHz SMI CPU%c1 CPU%c3 CPU%c6 CPU%c7 CoreTmp PkgTmp Pkg%pc2 Pkg%pc3 Pkg%pc6 Pkg%pc7 PkgWatt CorWatt GFXWatt
149 - - 496 12.75 3886 3492 0 13.16 0.04 74.04 0.00 36 36 0.00 0.00 0.00 0.00 23.15 17.65 0.00
150 0 0 22 0.57 3830 3492 0 0.83 0.02 98.59 0.00 27 36 0.00 0.00 0.00 0.00 23.15 17.65 0.00
151 0 4 9 0.24 3829 3492 0 1.15
152 1 1 4 0.09 3783 3492 0 99.91 0.00 0.00 0.00 36
153 1 5 3880 99.82 3888 3492 0 0.18
154 2 2 17 0.44 3813 3492 0 0.77 0.04 98.75 0.00 28
155 2 6 12 0.32 3823 3492 0 0.89
156 3 3 16 0.43 3844 3492 0 0.63 0.11 98.84 0.00 30
157 3 7 4 0.11 3827 3492 0 0.94
161 Above the cycle soaker drives cpu5 up its 3.8 GHz turbo limit
162 while the other processors are generally in various states of idle.
164 Note that cpu1 and cpu5 are HT siblings within core1.
165 As cpu5 is very busy, it prevents its sibling, cpu1,
166 from entering a c-state deeper than c1.
168 Note that the Avg_MHz column reflects the total number of cycles executed
169 divided by the measurement interval. If the %Busy column is 100%,
170 then the processor was running at that speed the entire interval.
171 The Avg_MHz multiplied by the %Busy results in the Bzy_MHz --
172 which is the average frequency while the processor was executing --
173 not including any non-busy idle time.
181 reads hardware counters, but doesn't write them.
182 So it will not interfere with the OS or other programs, including
183 multiple invocations of itself.
186 may work poorly on Linux-2.6.20 through 2.6.29,
187 as \fBacpi-cpufreq \fPperiodically cleared the APERF and MPERF
190 If the TSC column does not make sense, then
191 the other numbers will also make no sense.
192 Turbostat is lightweight, and its data collection is not atomic.
193 These issues are usually caused by an extremely short measurement
194 interval (much less than 1 second), or system activity that prevents
195 turbostat from being able to run on all CPUS to quickly collect data.
197 The APERF, MPERF MSRs are defined to count non-halted cycles.
198 Although it is not guaranteed by the architecture, turbostat assumes
199 that they count at TSC rate, which is true on all processors tested to date.
202 "Intel® Turbo Boost Technology
203 in Intel® Core™ Microarchitecture (Nehalem) Based Processors"
204 http://download.intel.com/design/processor/applnots/320354.pdf
206 "Intel® 64 and IA-32 Architectures Software Developer's Manual
207 Volume 3B: System Programming Guide"
208 http://www.intel.com/products/processor/manuals/
221 Written by Len Brown <len.brown@intel.com>