1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel_pt.c: Intel Processor Trace support
4 * Copyright (c) 2013-2015, Intel Corporation.
11 #include <linux/kernel.h>
12 #include <linux/string.h>
13 #include <linux/types.h>
14 #include <linux/zalloc.h>
27 #include "thread-stack.h"
29 #include "callchain.h"
36 #include "util/perf_api_probe.h"
37 #include "util/synthetic-events.h"
38 #include "time-utils.h"
40 #include "../arch/x86/include/uapi/asm/perf_regs.h"
42 #include "intel-pt-decoder/intel-pt-log.h"
43 #include "intel-pt-decoder/intel-pt-decoder.h"
44 #include "intel-pt-decoder/intel-pt-insn-decoder.h"
45 #include "intel-pt-decoder/intel-pt-pkt-decoder.h"
47 #define MAX_TIMESTAMP (~0ULL)
55 struct auxtrace auxtrace;
56 struct auxtrace_queues queues;
57 struct auxtrace_heap heap;
59 struct perf_session *session;
60 struct machine *machine;
61 struct evsel *switch_evsel;
62 struct thread *unknown_thread;
63 bool timeless_decoding;
72 bool use_thread_stack;
74 unsigned int br_stack_sz;
75 unsigned int br_stack_sz_plus;
76 int have_sched_switch;
82 struct perf_tsc_conversion tc;
83 bool cap_user_time_zero;
85 struct itrace_synth_opts synth_opts;
87 bool sample_instructions;
88 u64 instructions_sample_type;
93 u64 branches_sample_type;
96 bool sample_transactions;
97 u64 transactions_sample_type;
100 bool sample_ptwrites;
101 u64 ptwrites_sample_type;
104 bool sample_pwr_events;
105 u64 pwr_events_sample_type;
114 struct evsel *pebs_evsel;
123 unsigned max_non_turbo_ratio;
126 unsigned long num_events;
129 struct addr_filters filts;
131 struct range *time_ranges;
132 unsigned int range_cnt;
134 struct ip_callchain *chain;
135 struct branch_stack *br_stack;
139 INTEL_PT_SS_NOT_TRACING,
142 INTEL_PT_SS_EXPECTING_SWITCH_EVENT,
143 INTEL_PT_SS_EXPECTING_SWITCH_IP,
146 struct intel_pt_queue {
148 unsigned int queue_nr;
149 struct auxtrace_buffer *buffer;
150 struct auxtrace_buffer *old_buffer;
152 const struct intel_pt_state *state;
153 struct ip_callchain *chain;
154 struct branch_stack *last_branch;
155 union perf_event *event_buf;
158 bool step_through_buffers;
159 bool use_buffer_pid_tid;
165 struct thread *thread;
166 struct machine *guest_machine;
167 struct thread *unknown_guest_thread;
168 pid_t guest_machine_pid;
175 unsigned int sel_idx;
181 u64 last_in_insn_cnt;
183 u64 last_br_insn_cnt;
185 unsigned int cbr_seen;
186 char insn[INTEL_PT_INSN_BUF_SZ];
189 static void intel_pt_dump(struct intel_pt *pt __maybe_unused,
190 unsigned char *buf, size_t len)
192 struct intel_pt_pkt packet;
195 char desc[INTEL_PT_PKT_DESC_MAX];
196 const char *color = PERF_COLOR_BLUE;
197 enum intel_pt_pkt_ctx ctx = INTEL_PT_NO_CTX;
199 color_fprintf(stdout, color,
200 ". ... Intel Processor Trace data: size %zu bytes\n",
204 ret = intel_pt_get_packet(buf, len, &packet, &ctx);
210 color_fprintf(stdout, color, " %08x: ", pos);
211 for (i = 0; i < pkt_len; i++)
212 color_fprintf(stdout, color, " %02x", buf[i]);
214 color_fprintf(stdout, color, " ");
216 ret = intel_pt_pkt_desc(&packet, desc,
217 INTEL_PT_PKT_DESC_MAX);
219 color_fprintf(stdout, color, " %s\n", desc);
221 color_fprintf(stdout, color, " Bad packet!\n");
229 static void intel_pt_dump_event(struct intel_pt *pt, unsigned char *buf,
233 intel_pt_dump(pt, buf, len);
236 static void intel_pt_log_event(union perf_event *event)
238 FILE *f = intel_pt_log_fp();
240 if (!intel_pt_enable_logging || !f)
243 perf_event__fprintf(event, NULL, f);
246 static void intel_pt_dump_sample(struct perf_session *session,
247 struct perf_sample *sample)
249 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
253 intel_pt_dump(pt, sample->aux_sample.data, sample->aux_sample.size);
256 static bool intel_pt_log_events(struct intel_pt *pt, u64 tm)
258 struct perf_time_interval *range = pt->synth_opts.ptime_range;
259 int n = pt->synth_opts.range_num;
261 if (pt->synth_opts.log_plus_flags & AUXTRACE_LOG_FLG_ALL_PERF_EVTS)
264 if (pt->synth_opts.log_minus_flags & AUXTRACE_LOG_FLG_ALL_PERF_EVTS)
267 /* perf_time__ranges_skip_sample does not work if time is zero */
271 return !n || !perf_time__ranges_skip_sample(range, n, tm);
274 static int intel_pt_do_fix_overlap(struct intel_pt *pt, struct auxtrace_buffer *a,
275 struct auxtrace_buffer *b)
277 bool consecutive = false;
280 start = intel_pt_find_overlap(a->data, a->size, b->data, b->size,
281 pt->have_tsc, &consecutive);
284 b->use_size = b->data + b->size - start;
286 if (b->use_size && consecutive)
287 b->consecutive = true;
291 static int intel_pt_get_buffer(struct intel_pt_queue *ptq,
292 struct auxtrace_buffer *buffer,
293 struct auxtrace_buffer *old_buffer,
294 struct intel_pt_buffer *b)
299 int fd = perf_data__fd(ptq->pt->session->data);
301 buffer->data = auxtrace_buffer__get_data(buffer, fd);
306 might_overlap = ptq->pt->snapshot_mode || ptq->pt->sampling_mode;
307 if (might_overlap && !buffer->consecutive && old_buffer &&
308 intel_pt_do_fix_overlap(ptq->pt, old_buffer, buffer))
311 if (buffer->use_data) {
312 b->len = buffer->use_size;
313 b->buf = buffer->use_data;
315 b->len = buffer->size;
316 b->buf = buffer->data;
318 b->ref_timestamp = buffer->reference;
320 if (!old_buffer || (might_overlap && !buffer->consecutive)) {
321 b->consecutive = false;
322 b->trace_nr = buffer->buffer_nr + 1;
324 b->consecutive = true;
330 /* Do not drop buffers with references - refer intel_pt_get_trace() */
331 static void intel_pt_lookahead_drop_buffer(struct intel_pt_queue *ptq,
332 struct auxtrace_buffer *buffer)
334 if (!buffer || buffer == ptq->buffer || buffer == ptq->old_buffer)
337 auxtrace_buffer__drop_data(buffer);
340 /* Must be serialized with respect to intel_pt_get_trace() */
341 static int intel_pt_lookahead(void *data, intel_pt_lookahead_cb_t cb,
344 struct intel_pt_queue *ptq = data;
345 struct auxtrace_buffer *buffer = ptq->buffer;
346 struct auxtrace_buffer *old_buffer = ptq->old_buffer;
347 struct auxtrace_queue *queue;
350 queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
353 struct intel_pt_buffer b = { .len = 0 };
355 buffer = auxtrace_buffer__next(queue, buffer);
359 err = intel_pt_get_buffer(ptq, buffer, old_buffer, &b);
364 intel_pt_lookahead_drop_buffer(ptq, old_buffer);
367 intel_pt_lookahead_drop_buffer(ptq, buffer);
371 err = cb(&b, cb_data);
376 if (buffer != old_buffer)
377 intel_pt_lookahead_drop_buffer(ptq, buffer);
378 intel_pt_lookahead_drop_buffer(ptq, old_buffer);
384 * This function assumes data is processed sequentially only.
385 * Must be serialized with respect to intel_pt_lookahead()
387 static int intel_pt_get_trace(struct intel_pt_buffer *b, void *data)
389 struct intel_pt_queue *ptq = data;
390 struct auxtrace_buffer *buffer = ptq->buffer;
391 struct auxtrace_buffer *old_buffer = ptq->old_buffer;
392 struct auxtrace_queue *queue;
400 queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
402 buffer = auxtrace_buffer__next(queue, buffer);
405 auxtrace_buffer__drop_data(old_buffer);
410 ptq->buffer = buffer;
412 err = intel_pt_get_buffer(ptq, buffer, old_buffer, b);
416 if (ptq->step_through_buffers)
421 auxtrace_buffer__drop_data(old_buffer);
422 ptq->old_buffer = buffer;
424 auxtrace_buffer__drop_data(buffer);
425 return intel_pt_get_trace(b, data);
431 struct intel_pt_cache_entry {
432 struct auxtrace_cache_entry entry;
435 enum intel_pt_insn_op op;
436 enum intel_pt_insn_branch branch;
439 char insn[INTEL_PT_INSN_BUF_SZ];
442 static int intel_pt_config_div(const char *var, const char *value, void *data)
447 if (!strcmp(var, "intel-pt.cache-divisor")) {
448 val = strtol(value, NULL, 0);
449 if (val > 0 && val <= INT_MAX)
456 static int intel_pt_cache_divisor(void)
463 perf_config(intel_pt_config_div, &d);
471 static unsigned int intel_pt_cache_size(struct dso *dso,
472 struct machine *machine)
476 size = dso__data_size(dso, machine);
477 size /= intel_pt_cache_divisor();
480 if (size > (1 << 21))
482 return 32 - __builtin_clz(size);
485 static struct auxtrace_cache *intel_pt_cache(struct dso *dso,
486 struct machine *machine)
488 struct auxtrace_cache *c;
491 if (dso->auxtrace_cache)
492 return dso->auxtrace_cache;
494 bits = intel_pt_cache_size(dso, machine);
496 /* Ignoring cache creation failure */
497 c = auxtrace_cache__new(bits, sizeof(struct intel_pt_cache_entry), 200);
499 dso->auxtrace_cache = c;
504 static int intel_pt_cache_add(struct dso *dso, struct machine *machine,
505 u64 offset, u64 insn_cnt, u64 byte_cnt,
506 struct intel_pt_insn *intel_pt_insn)
508 struct auxtrace_cache *c = intel_pt_cache(dso, machine);
509 struct intel_pt_cache_entry *e;
515 e = auxtrace_cache__alloc_entry(c);
519 e->insn_cnt = insn_cnt;
520 e->byte_cnt = byte_cnt;
521 e->op = intel_pt_insn->op;
522 e->branch = intel_pt_insn->branch;
523 e->length = intel_pt_insn->length;
524 e->rel = intel_pt_insn->rel;
525 memcpy(e->insn, intel_pt_insn->buf, INTEL_PT_INSN_BUF_SZ);
527 err = auxtrace_cache__add(c, offset, &e->entry);
529 auxtrace_cache__free_entry(c, e);
534 static struct intel_pt_cache_entry *
535 intel_pt_cache_lookup(struct dso *dso, struct machine *machine, u64 offset)
537 struct auxtrace_cache *c = intel_pt_cache(dso, machine);
542 return auxtrace_cache__lookup(dso->auxtrace_cache, offset);
545 static void intel_pt_cache_invalidate(struct dso *dso, struct machine *machine,
548 struct auxtrace_cache *c = intel_pt_cache(dso, machine);
553 auxtrace_cache__remove(dso->auxtrace_cache, offset);
556 static inline bool intel_pt_guest_kernel_ip(uint64_t ip)
558 /* Assumes 64-bit kernel */
559 return ip & (1ULL << 63);
562 static inline u8 intel_pt_nr_cpumode(struct intel_pt_queue *ptq, uint64_t ip, bool nr)
565 return intel_pt_guest_kernel_ip(ip) ?
566 PERF_RECORD_MISC_GUEST_KERNEL :
567 PERF_RECORD_MISC_GUEST_USER;
570 return ip >= ptq->pt->kernel_start ?
571 PERF_RECORD_MISC_KERNEL :
572 PERF_RECORD_MISC_USER;
575 static inline u8 intel_pt_cpumode(struct intel_pt_queue *ptq, uint64_t from_ip, uint64_t to_ip)
577 /* No support for non-zero CS base */
579 return intel_pt_nr_cpumode(ptq, from_ip, ptq->state->from_nr);
580 return intel_pt_nr_cpumode(ptq, to_ip, ptq->state->to_nr);
583 static int intel_pt_get_guest(struct intel_pt_queue *ptq)
585 struct machines *machines = &ptq->pt->session->machines;
586 struct machine *machine;
587 pid_t pid = ptq->pid <= 0 ? DEFAULT_GUEST_KERNEL_ID : ptq->pid;
589 if (ptq->guest_machine && pid == ptq->guest_machine_pid)
592 ptq->guest_machine = NULL;
593 thread__zput(ptq->unknown_guest_thread);
595 machine = machines__find_guest(machines, pid);
599 ptq->unknown_guest_thread = machine__idle_thread(machine);
600 if (!ptq->unknown_guest_thread)
603 ptq->guest_machine = machine;
604 ptq->guest_machine_pid = pid;
609 static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn,
610 uint64_t *insn_cnt_ptr, uint64_t *ip,
611 uint64_t to_ip, uint64_t max_insn_cnt,
614 struct intel_pt_queue *ptq = data;
615 struct machine *machine = ptq->pt->machine;
616 struct thread *thread;
617 struct addr_location al;
618 unsigned char buf[INTEL_PT_INSN_BUF_SZ];
622 u64 offset, start_offset, start_ip;
627 intel_pt_insn->length = 0;
629 if (to_ip && *ip == to_ip)
632 nr = ptq->state->to_nr;
633 cpumode = intel_pt_nr_cpumode(ptq, *ip, nr);
636 if (cpumode != PERF_RECORD_MISC_GUEST_KERNEL ||
637 intel_pt_get_guest(ptq))
639 machine = ptq->guest_machine;
640 thread = ptq->unknown_guest_thread;
642 thread = ptq->thread;
644 if (cpumode != PERF_RECORD_MISC_KERNEL)
646 thread = ptq->pt->unknown_thread;
651 if (!thread__find_map(thread, cpumode, *ip, &al) || !al.map->dso)
654 if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR &&
655 dso__data_status_seen(al.map->dso,
656 DSO_DATA_STATUS_SEEN_ITRACE))
659 offset = al.map->map_ip(al.map, *ip);
661 if (!to_ip && one_map) {
662 struct intel_pt_cache_entry *e;
664 e = intel_pt_cache_lookup(al.map->dso, machine, offset);
666 (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) {
667 *insn_cnt_ptr = e->insn_cnt;
669 intel_pt_insn->op = e->op;
670 intel_pt_insn->branch = e->branch;
671 intel_pt_insn->length = e->length;
672 intel_pt_insn->rel = e->rel;
673 memcpy(intel_pt_insn->buf, e->insn,
674 INTEL_PT_INSN_BUF_SZ);
675 intel_pt_log_insn_no_data(intel_pt_insn, *ip);
680 start_offset = offset;
683 /* Load maps to ensure dso->is_64_bit has been updated */
686 x86_64 = al.map->dso->is_64_bit;
689 len = dso__data_read_offset(al.map->dso, machine,
691 INTEL_PT_INSN_BUF_SZ);
695 if (intel_pt_get_insn(buf, len, x86_64, intel_pt_insn))
698 intel_pt_log_insn(intel_pt_insn, *ip);
702 if (intel_pt_insn->branch != INTEL_PT_BR_NO_BRANCH)
705 if (max_insn_cnt && insn_cnt >= max_insn_cnt)
708 *ip += intel_pt_insn->length;
710 if (to_ip && *ip == to_ip)
713 if (*ip >= al.map->end)
716 offset += intel_pt_insn->length;
721 *insn_cnt_ptr = insn_cnt;
727 * Didn't lookup in the 'to_ip' case, so do it now to prevent duplicate
731 struct intel_pt_cache_entry *e;
733 e = intel_pt_cache_lookup(al.map->dso, machine, start_offset);
738 /* Ignore cache errors */
739 intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt,
740 *ip - start_ip, intel_pt_insn);
745 *insn_cnt_ptr = insn_cnt;
749 static bool intel_pt_match_pgd_ip(struct intel_pt *pt, uint64_t ip,
750 uint64_t offset, const char *filename)
752 struct addr_filter *filt;
753 bool have_filter = false;
754 bool hit_tracestop = false;
755 bool hit_filter = false;
757 list_for_each_entry(filt, &pt->filts.head, list) {
761 if ((filename && !filt->filename) ||
762 (!filename && filt->filename) ||
763 (filename && strcmp(filename, filt->filename)))
766 if (!(offset >= filt->addr && offset < filt->addr + filt->size))
769 intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s hit filter: %s offset %#"PRIx64" size %#"PRIx64"\n",
770 ip, offset, filename ? filename : "[kernel]",
771 filt->start ? "filter" : "stop",
772 filt->addr, filt->size);
777 hit_tracestop = true;
780 if (!hit_tracestop && !hit_filter)
781 intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s is not in a filter region\n",
782 ip, offset, filename ? filename : "[kernel]");
784 return hit_tracestop || (have_filter && !hit_filter);
787 static int __intel_pt_pgd_ip(uint64_t ip, void *data)
789 struct intel_pt_queue *ptq = data;
790 struct thread *thread;
791 struct addr_location al;
795 if (ptq->state->to_nr) {
796 if (intel_pt_guest_kernel_ip(ip))
797 return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL);
798 /* No support for decoding guest user space */
800 } else if (ip >= ptq->pt->kernel_start) {
801 return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL);
804 cpumode = PERF_RECORD_MISC_USER;
806 thread = ptq->thread;
810 if (!thread__find_map(thread, cpumode, ip, &al) || !al.map->dso)
813 offset = al.map->map_ip(al.map, ip);
815 return intel_pt_match_pgd_ip(ptq->pt, ip, offset,
816 al.map->dso->long_name);
819 static bool intel_pt_pgd_ip(uint64_t ip, void *data)
821 return __intel_pt_pgd_ip(ip, data) > 0;
824 static bool intel_pt_get_config(struct intel_pt *pt,
825 struct perf_event_attr *attr, u64 *config)
827 if (attr->type == pt->pmu_type) {
829 *config = attr->config;
836 static bool intel_pt_exclude_kernel(struct intel_pt *pt)
840 evlist__for_each_entry(pt->session->evlist, evsel) {
841 if (intel_pt_get_config(pt, &evsel->core.attr, NULL) &&
842 !evsel->core.attr.exclude_kernel)
848 static bool intel_pt_return_compression(struct intel_pt *pt)
853 if (!pt->noretcomp_bit)
856 evlist__for_each_entry(pt->session->evlist, evsel) {
857 if (intel_pt_get_config(pt, &evsel->core.attr, &config) &&
858 (config & pt->noretcomp_bit))
864 static bool intel_pt_branch_enable(struct intel_pt *pt)
869 evlist__for_each_entry(pt->session->evlist, evsel) {
870 if (intel_pt_get_config(pt, &evsel->core.attr, &config) &&
871 (config & 1) && !(config & 0x2000))
877 static unsigned int intel_pt_mtc_period(struct intel_pt *pt)
883 if (!pt->mtc_freq_bits)
886 for (shift = 0, config = pt->mtc_freq_bits; !(config & 1); shift++)
889 evlist__for_each_entry(pt->session->evlist, evsel) {
890 if (intel_pt_get_config(pt, &evsel->core.attr, &config))
891 return (config & pt->mtc_freq_bits) >> shift;
896 static bool intel_pt_timeless_decoding(struct intel_pt *pt)
899 bool timeless_decoding = true;
902 if (!pt->tsc_bit || !pt->cap_user_time_zero)
905 evlist__for_each_entry(pt->session->evlist, evsel) {
906 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_TIME))
908 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) {
909 if (config & pt->tsc_bit)
910 timeless_decoding = false;
915 return timeless_decoding;
918 static bool intel_pt_tracing_kernel(struct intel_pt *pt)
922 evlist__for_each_entry(pt->session->evlist, evsel) {
923 if (intel_pt_get_config(pt, &evsel->core.attr, NULL) &&
924 !evsel->core.attr.exclude_kernel)
930 static bool intel_pt_have_tsc(struct intel_pt *pt)
933 bool have_tsc = false;
939 evlist__for_each_entry(pt->session->evlist, evsel) {
940 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) {
941 if (config & pt->tsc_bit)
950 static bool intel_pt_sampling_mode(struct intel_pt *pt)
954 evlist__for_each_entry(pt->session->evlist, evsel) {
955 if ((evsel->core.attr.sample_type & PERF_SAMPLE_AUX) &&
956 evsel->core.attr.aux_sample_size)
962 static u64 intel_pt_ctl(struct intel_pt *pt)
967 evlist__for_each_entry(pt->session->evlist, evsel) {
968 if (intel_pt_get_config(pt, &evsel->core.attr, &config))
974 static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns)
978 quot = ns / pt->tc.time_mult;
979 rem = ns % pt->tc.time_mult;
980 return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) /
984 static struct ip_callchain *intel_pt_alloc_chain(struct intel_pt *pt)
986 size_t sz = sizeof(struct ip_callchain);
988 /* Add 1 to callchain_sz for callchain context */
989 sz += (pt->synth_opts.callchain_sz + 1) * sizeof(u64);
993 static int intel_pt_callchain_init(struct intel_pt *pt)
997 evlist__for_each_entry(pt->session->evlist, evsel) {
998 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_CALLCHAIN))
999 evsel->synth_sample_type |= PERF_SAMPLE_CALLCHAIN;
1002 pt->chain = intel_pt_alloc_chain(pt);
1009 static void intel_pt_add_callchain(struct intel_pt *pt,
1010 struct perf_sample *sample)
1012 struct thread *thread = machine__findnew_thread(pt->machine,
1016 thread_stack__sample_late(thread, sample->cpu, pt->chain,
1017 pt->synth_opts.callchain_sz + 1, sample->ip,
1020 sample->callchain = pt->chain;
1023 static struct branch_stack *intel_pt_alloc_br_stack(unsigned int entry_cnt)
1025 size_t sz = sizeof(struct branch_stack);
1027 sz += entry_cnt * sizeof(struct branch_entry);
1031 static int intel_pt_br_stack_init(struct intel_pt *pt)
1033 struct evsel *evsel;
1035 evlist__for_each_entry(pt->session->evlist, evsel) {
1036 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_BRANCH_STACK))
1037 evsel->synth_sample_type |= PERF_SAMPLE_BRANCH_STACK;
1040 pt->br_stack = intel_pt_alloc_br_stack(pt->br_stack_sz);
1047 static void intel_pt_add_br_stack(struct intel_pt *pt,
1048 struct perf_sample *sample)
1050 struct thread *thread = machine__findnew_thread(pt->machine,
1054 thread_stack__br_sample_late(thread, sample->cpu, pt->br_stack,
1055 pt->br_stack_sz, sample->ip,
1058 sample->branch_stack = pt->br_stack;
1061 /* INTEL_PT_LBR_0, INTEL_PT_LBR_1 and INTEL_PT_LBR_2 */
1062 #define LBRS_MAX (INTEL_PT_BLK_ITEM_ID_CNT * 3U)
1064 static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt,
1065 unsigned int queue_nr)
1067 struct intel_pt_params params = { .get_trace = 0, };
1068 struct perf_env *env = pt->machine->env;
1069 struct intel_pt_queue *ptq;
1071 ptq = zalloc(sizeof(struct intel_pt_queue));
1075 if (pt->synth_opts.callchain) {
1076 ptq->chain = intel_pt_alloc_chain(pt);
1081 if (pt->synth_opts.last_branch || pt->synth_opts.other_events) {
1082 unsigned int entry_cnt = max(LBRS_MAX, pt->br_stack_sz);
1084 ptq->last_branch = intel_pt_alloc_br_stack(entry_cnt);
1085 if (!ptq->last_branch)
1089 ptq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE);
1090 if (!ptq->event_buf)
1094 ptq->queue_nr = queue_nr;
1095 ptq->exclude_kernel = intel_pt_exclude_kernel(pt);
1101 params.get_trace = intel_pt_get_trace;
1102 params.walk_insn = intel_pt_walk_next_insn;
1103 params.lookahead = intel_pt_lookahead;
1105 params.return_compression = intel_pt_return_compression(pt);
1106 params.branch_enable = intel_pt_branch_enable(pt);
1107 params.ctl = intel_pt_ctl(pt);
1108 params.max_non_turbo_ratio = pt->max_non_turbo_ratio;
1109 params.mtc_period = intel_pt_mtc_period(pt);
1110 params.tsc_ctc_ratio_n = pt->tsc_ctc_ratio_n;
1111 params.tsc_ctc_ratio_d = pt->tsc_ctc_ratio_d;
1112 params.quick = pt->synth_opts.quick;
1114 if (pt->filts.cnt > 0)
1115 params.pgd_ip = intel_pt_pgd_ip;
1117 if (pt->synth_opts.instructions) {
1118 if (pt->synth_opts.period) {
1119 switch (pt->synth_opts.period_type) {
1120 case PERF_ITRACE_PERIOD_INSTRUCTIONS:
1121 params.period_type =
1122 INTEL_PT_PERIOD_INSTRUCTIONS;
1123 params.period = pt->synth_opts.period;
1125 case PERF_ITRACE_PERIOD_TICKS:
1126 params.period_type = INTEL_PT_PERIOD_TICKS;
1127 params.period = pt->synth_opts.period;
1129 case PERF_ITRACE_PERIOD_NANOSECS:
1130 params.period_type = INTEL_PT_PERIOD_TICKS;
1131 params.period = intel_pt_ns_to_ticks(pt,
1132 pt->synth_opts.period);
1139 if (!params.period) {
1140 params.period_type = INTEL_PT_PERIOD_INSTRUCTIONS;
1145 if (env->cpuid && !strncmp(env->cpuid, "GenuineIntel,6,92,", 18))
1146 params.flags |= INTEL_PT_FUP_WITH_NLIP;
1148 ptq->decoder = intel_pt_decoder_new(¶ms);
1155 zfree(&ptq->event_buf);
1156 zfree(&ptq->last_branch);
1162 static void intel_pt_free_queue(void *priv)
1164 struct intel_pt_queue *ptq = priv;
1168 thread__zput(ptq->thread);
1169 thread__zput(ptq->unknown_guest_thread);
1170 intel_pt_decoder_free(ptq->decoder);
1171 zfree(&ptq->event_buf);
1172 zfree(&ptq->last_branch);
1177 static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt,
1178 struct auxtrace_queue *queue)
1180 struct intel_pt_queue *ptq = queue->priv;
1182 if (queue->tid == -1 || pt->have_sched_switch) {
1183 ptq->tid = machine__get_current_tid(pt->machine, ptq->cpu);
1186 thread__zput(ptq->thread);
1189 if (!ptq->thread && ptq->tid != -1)
1190 ptq->thread = machine__find_thread(pt->machine, -1, ptq->tid);
1193 ptq->pid = ptq->thread->pid_;
1194 if (queue->cpu == -1)
1195 ptq->cpu = ptq->thread->cpu;
1199 static void intel_pt_sample_flags(struct intel_pt_queue *ptq)
1201 if (ptq->state->flags & INTEL_PT_ABORT_TX) {
1202 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT;
1203 } else if (ptq->state->flags & INTEL_PT_ASYNC) {
1204 if (!ptq->state->to_ip)
1205 ptq->flags = PERF_IP_FLAG_BRANCH |
1206 PERF_IP_FLAG_TRACE_END;
1207 else if (ptq->state->from_nr && !ptq->state->to_nr)
1208 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL |
1209 PERF_IP_FLAG_VMEXIT;
1211 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL |
1212 PERF_IP_FLAG_ASYNC |
1213 PERF_IP_FLAG_INTERRUPT;
1216 if (ptq->state->from_ip)
1217 ptq->flags = intel_pt_insn_type(ptq->state->insn_op);
1219 ptq->flags = PERF_IP_FLAG_BRANCH |
1220 PERF_IP_FLAG_TRACE_BEGIN;
1221 if (ptq->state->flags & INTEL_PT_IN_TX)
1222 ptq->flags |= PERF_IP_FLAG_IN_TX;
1223 ptq->insn_len = ptq->state->insn_len;
1224 memcpy(ptq->insn, ptq->state->insn, INTEL_PT_INSN_BUF_SZ);
1227 if (ptq->state->type & INTEL_PT_TRACE_BEGIN)
1228 ptq->flags |= PERF_IP_FLAG_TRACE_BEGIN;
1229 if (ptq->state->type & INTEL_PT_TRACE_END)
1230 ptq->flags |= PERF_IP_FLAG_TRACE_END;
1233 static void intel_pt_setup_time_range(struct intel_pt *pt,
1234 struct intel_pt_queue *ptq)
1239 ptq->sel_timestamp = pt->time_ranges[0].start;
1242 if (ptq->sel_timestamp) {
1243 ptq->sel_start = true;
1245 ptq->sel_timestamp = pt->time_ranges[0].end;
1246 ptq->sel_start = false;
1250 static int intel_pt_setup_queue(struct intel_pt *pt,
1251 struct auxtrace_queue *queue,
1252 unsigned int queue_nr)
1254 struct intel_pt_queue *ptq = queue->priv;
1256 if (list_empty(&queue->head))
1260 ptq = intel_pt_alloc_queue(pt, queue_nr);
1265 if (queue->cpu != -1)
1266 ptq->cpu = queue->cpu;
1267 ptq->tid = queue->tid;
1269 ptq->cbr_seen = UINT_MAX;
1271 if (pt->sampling_mode && !pt->snapshot_mode &&
1272 pt->timeless_decoding)
1273 ptq->step_through_buffers = true;
1275 ptq->sync_switch = pt->sync_switch;
1277 intel_pt_setup_time_range(pt, ptq);
1280 if (!ptq->on_heap &&
1281 (!ptq->sync_switch ||
1282 ptq->switch_state != INTEL_PT_SS_EXPECTING_SWITCH_EVENT)) {
1283 const struct intel_pt_state *state;
1286 if (pt->timeless_decoding)
1289 intel_pt_log("queue %u getting timestamp\n", queue_nr);
1290 intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
1291 queue_nr, ptq->cpu, ptq->pid, ptq->tid);
1293 if (ptq->sel_start && ptq->sel_timestamp) {
1294 ret = intel_pt_fast_forward(ptq->decoder,
1295 ptq->sel_timestamp);
1301 state = intel_pt_decode(ptq->decoder);
1303 if (state->err == INTEL_PT_ERR_NODATA) {
1304 intel_pt_log("queue %u has no timestamp\n",
1310 if (state->timestamp)
1314 ptq->timestamp = state->timestamp;
1315 intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n",
1316 queue_nr, ptq->timestamp);
1318 ptq->have_sample = true;
1319 if (ptq->sel_start && ptq->sel_timestamp &&
1320 ptq->timestamp < ptq->sel_timestamp)
1321 ptq->have_sample = false;
1322 intel_pt_sample_flags(ptq);
1323 ret = auxtrace_heap__add(&pt->heap, queue_nr, ptq->timestamp);
1326 ptq->on_heap = true;
1332 static int intel_pt_setup_queues(struct intel_pt *pt)
1337 for (i = 0; i < pt->queues.nr_queues; i++) {
1338 ret = intel_pt_setup_queue(pt, &pt->queues.queue_array[i], i);
1345 static inline bool intel_pt_skip_event(struct intel_pt *pt)
1347 return pt->synth_opts.initial_skip &&
1348 pt->num_events++ < pt->synth_opts.initial_skip;
1352 * Cannot count CBR as skipped because it won't go away until cbr == cbr_seen.
1353 * Also ensure CBR is first non-skipped event by allowing for 4 more samples
1354 * from this decoder state.
1356 static inline bool intel_pt_skip_cbr_event(struct intel_pt *pt)
1358 return pt->synth_opts.initial_skip &&
1359 pt->num_events + 4 < pt->synth_opts.initial_skip;
1362 static void intel_pt_prep_a_sample(struct intel_pt_queue *ptq,
1363 union perf_event *event,
1364 struct perf_sample *sample)
1366 event->sample.header.type = PERF_RECORD_SAMPLE;
1367 event->sample.header.size = sizeof(struct perf_event_header);
1369 sample->pid = ptq->pid;
1370 sample->tid = ptq->tid;
1371 sample->cpu = ptq->cpu;
1372 sample->insn_len = ptq->insn_len;
1373 memcpy(sample->insn, ptq->insn, INTEL_PT_INSN_BUF_SZ);
1376 static void intel_pt_prep_b_sample(struct intel_pt *pt,
1377 struct intel_pt_queue *ptq,
1378 union perf_event *event,
1379 struct perf_sample *sample)
1381 intel_pt_prep_a_sample(ptq, event, sample);
1383 if (!pt->timeless_decoding)
1384 sample->time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
1386 sample->ip = ptq->state->from_ip;
1387 sample->addr = ptq->state->to_ip;
1388 sample->cpumode = intel_pt_cpumode(ptq, sample->ip, sample->addr);
1390 sample->flags = ptq->flags;
1392 event->sample.header.misc = sample->cpumode;
1395 static int intel_pt_inject_event(union perf_event *event,
1396 struct perf_sample *sample, u64 type)
1398 event->header.size = perf_event__sample_event_size(sample, type, 0);
1399 return perf_event__synthesize_sample(event, type, 0, sample);
1402 static inline int intel_pt_opt_inject(struct intel_pt *pt,
1403 union perf_event *event,
1404 struct perf_sample *sample, u64 type)
1406 if (!pt->synth_opts.inject)
1409 return intel_pt_inject_event(event, sample, type);
1412 static int intel_pt_deliver_synth_event(struct intel_pt *pt,
1413 union perf_event *event,
1414 struct perf_sample *sample, u64 type)
1418 ret = intel_pt_opt_inject(pt, event, sample, type);
1422 ret = perf_session__deliver_synth_event(pt->session, event, sample);
1424 pr_err("Intel PT: failed to deliver event, error %d\n", ret);
1429 static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq)
1431 struct intel_pt *pt = ptq->pt;
1432 union perf_event *event = ptq->event_buf;
1433 struct perf_sample sample = { .ip = 0, };
1434 struct dummy_branch_stack {
1437 struct branch_entry entries;
1440 if (pt->branches_filter && !(pt->branches_filter & ptq->flags))
1443 if (intel_pt_skip_event(pt))
1446 intel_pt_prep_b_sample(pt, ptq, event, &sample);
1448 sample.id = ptq->pt->branches_id;
1449 sample.stream_id = ptq->pt->branches_id;
1452 * perf report cannot handle events without a branch stack when using
1453 * SORT_MODE__BRANCH so make a dummy one.
1455 if (pt->synth_opts.last_branch && sort__mode == SORT_MODE__BRANCH) {
1456 dummy_bs = (struct dummy_branch_stack){
1464 sample.branch_stack = (struct branch_stack *)&dummy_bs;
1467 if (ptq->state->flags & INTEL_PT_SAMPLE_IPC)
1468 sample.cyc_cnt = ptq->ipc_cyc_cnt - ptq->last_br_cyc_cnt;
1469 if (sample.cyc_cnt) {
1470 sample.insn_cnt = ptq->ipc_insn_cnt - ptq->last_br_insn_cnt;
1471 ptq->last_br_insn_cnt = ptq->ipc_insn_cnt;
1472 ptq->last_br_cyc_cnt = ptq->ipc_cyc_cnt;
1475 return intel_pt_deliver_synth_event(pt, event, &sample,
1476 pt->branches_sample_type);
1479 static void intel_pt_prep_sample(struct intel_pt *pt,
1480 struct intel_pt_queue *ptq,
1481 union perf_event *event,
1482 struct perf_sample *sample)
1484 intel_pt_prep_b_sample(pt, ptq, event, sample);
1486 if (pt->synth_opts.callchain) {
1487 thread_stack__sample(ptq->thread, ptq->cpu, ptq->chain,
1488 pt->synth_opts.callchain_sz + 1,
1489 sample->ip, pt->kernel_start);
1490 sample->callchain = ptq->chain;
1493 if (pt->synth_opts.last_branch) {
1494 thread_stack__br_sample(ptq->thread, ptq->cpu, ptq->last_branch,
1496 sample->branch_stack = ptq->last_branch;
1500 static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq)
1502 struct intel_pt *pt = ptq->pt;
1503 union perf_event *event = ptq->event_buf;
1504 struct perf_sample sample = { .ip = 0, };
1506 if (intel_pt_skip_event(pt))
1509 intel_pt_prep_sample(pt, ptq, event, &sample);
1511 sample.id = ptq->pt->instructions_id;
1512 sample.stream_id = ptq->pt->instructions_id;
1513 if (pt->synth_opts.quick)
1516 sample.period = ptq->state->tot_insn_cnt - ptq->last_insn_cnt;
1518 if (ptq->state->flags & INTEL_PT_SAMPLE_IPC)
1519 sample.cyc_cnt = ptq->ipc_cyc_cnt - ptq->last_in_cyc_cnt;
1520 if (sample.cyc_cnt) {
1521 sample.insn_cnt = ptq->ipc_insn_cnt - ptq->last_in_insn_cnt;
1522 ptq->last_in_insn_cnt = ptq->ipc_insn_cnt;
1523 ptq->last_in_cyc_cnt = ptq->ipc_cyc_cnt;
1526 ptq->last_insn_cnt = ptq->state->tot_insn_cnt;
1528 return intel_pt_deliver_synth_event(pt, event, &sample,
1529 pt->instructions_sample_type);
1532 static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq)
1534 struct intel_pt *pt = ptq->pt;
1535 union perf_event *event = ptq->event_buf;
1536 struct perf_sample sample = { .ip = 0, };
1538 if (intel_pt_skip_event(pt))
1541 intel_pt_prep_sample(pt, ptq, event, &sample);
1543 sample.id = ptq->pt->transactions_id;
1544 sample.stream_id = ptq->pt->transactions_id;
1546 return intel_pt_deliver_synth_event(pt, event, &sample,
1547 pt->transactions_sample_type);
1550 static void intel_pt_prep_p_sample(struct intel_pt *pt,
1551 struct intel_pt_queue *ptq,
1552 union perf_event *event,
1553 struct perf_sample *sample)
1555 intel_pt_prep_sample(pt, ptq, event, sample);
1558 * Zero IP is used to mean "trace start" but that is not the case for
1559 * power or PTWRITE events with no IP, so clear the flags.
1565 static int intel_pt_synth_ptwrite_sample(struct intel_pt_queue *ptq)
1567 struct intel_pt *pt = ptq->pt;
1568 union perf_event *event = ptq->event_buf;
1569 struct perf_sample sample = { .ip = 0, };
1570 struct perf_synth_intel_ptwrite raw;
1572 if (intel_pt_skip_event(pt))
1575 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1577 sample.id = ptq->pt->ptwrites_id;
1578 sample.stream_id = ptq->pt->ptwrites_id;
1581 raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
1582 raw.payload = cpu_to_le64(ptq->state->ptw_payload);
1584 sample.raw_size = perf_synth__raw_size(raw);
1585 sample.raw_data = perf_synth__raw_data(&raw);
1587 return intel_pt_deliver_synth_event(pt, event, &sample,
1588 pt->ptwrites_sample_type);
1591 static int intel_pt_synth_cbr_sample(struct intel_pt_queue *ptq)
1593 struct intel_pt *pt = ptq->pt;
1594 union perf_event *event = ptq->event_buf;
1595 struct perf_sample sample = { .ip = 0, };
1596 struct perf_synth_intel_cbr raw;
1599 if (intel_pt_skip_cbr_event(pt))
1602 ptq->cbr_seen = ptq->state->cbr;
1604 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1606 sample.id = ptq->pt->cbr_id;
1607 sample.stream_id = ptq->pt->cbr_id;
1609 flags = (u16)ptq->state->cbr_payload | (pt->max_non_turbo_ratio << 16);
1610 raw.flags = cpu_to_le32(flags);
1611 raw.freq = cpu_to_le32(raw.cbr * pt->cbr2khz);
1614 sample.raw_size = perf_synth__raw_size(raw);
1615 sample.raw_data = perf_synth__raw_data(&raw);
1617 return intel_pt_deliver_synth_event(pt, event, &sample,
1618 pt->pwr_events_sample_type);
1621 static int intel_pt_synth_psb_sample(struct intel_pt_queue *ptq)
1623 struct intel_pt *pt = ptq->pt;
1624 union perf_event *event = ptq->event_buf;
1625 struct perf_sample sample = { .ip = 0, };
1626 struct perf_synth_intel_psb raw;
1628 if (intel_pt_skip_event(pt))
1631 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1633 sample.id = ptq->pt->psb_id;
1634 sample.stream_id = ptq->pt->psb_id;
1638 raw.offset = ptq->state->psb_offset;
1640 sample.raw_size = perf_synth__raw_size(raw);
1641 sample.raw_data = perf_synth__raw_data(&raw);
1643 return intel_pt_deliver_synth_event(pt, event, &sample,
1644 pt->pwr_events_sample_type);
1647 static int intel_pt_synth_mwait_sample(struct intel_pt_queue *ptq)
1649 struct intel_pt *pt = ptq->pt;
1650 union perf_event *event = ptq->event_buf;
1651 struct perf_sample sample = { .ip = 0, };
1652 struct perf_synth_intel_mwait raw;
1654 if (intel_pt_skip_event(pt))
1657 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1659 sample.id = ptq->pt->mwait_id;
1660 sample.stream_id = ptq->pt->mwait_id;
1663 raw.payload = cpu_to_le64(ptq->state->mwait_payload);
1665 sample.raw_size = perf_synth__raw_size(raw);
1666 sample.raw_data = perf_synth__raw_data(&raw);
1668 return intel_pt_deliver_synth_event(pt, event, &sample,
1669 pt->pwr_events_sample_type);
1672 static int intel_pt_synth_pwre_sample(struct intel_pt_queue *ptq)
1674 struct intel_pt *pt = ptq->pt;
1675 union perf_event *event = ptq->event_buf;
1676 struct perf_sample sample = { .ip = 0, };
1677 struct perf_synth_intel_pwre raw;
1679 if (intel_pt_skip_event(pt))
1682 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1684 sample.id = ptq->pt->pwre_id;
1685 sample.stream_id = ptq->pt->pwre_id;
1688 raw.payload = cpu_to_le64(ptq->state->pwre_payload);
1690 sample.raw_size = perf_synth__raw_size(raw);
1691 sample.raw_data = perf_synth__raw_data(&raw);
1693 return intel_pt_deliver_synth_event(pt, event, &sample,
1694 pt->pwr_events_sample_type);
1697 static int intel_pt_synth_exstop_sample(struct intel_pt_queue *ptq)
1699 struct intel_pt *pt = ptq->pt;
1700 union perf_event *event = ptq->event_buf;
1701 struct perf_sample sample = { .ip = 0, };
1702 struct perf_synth_intel_exstop raw;
1704 if (intel_pt_skip_event(pt))
1707 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1709 sample.id = ptq->pt->exstop_id;
1710 sample.stream_id = ptq->pt->exstop_id;
1713 raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
1715 sample.raw_size = perf_synth__raw_size(raw);
1716 sample.raw_data = perf_synth__raw_data(&raw);
1718 return intel_pt_deliver_synth_event(pt, event, &sample,
1719 pt->pwr_events_sample_type);
1722 static int intel_pt_synth_pwrx_sample(struct intel_pt_queue *ptq)
1724 struct intel_pt *pt = ptq->pt;
1725 union perf_event *event = ptq->event_buf;
1726 struct perf_sample sample = { .ip = 0, };
1727 struct perf_synth_intel_pwrx raw;
1729 if (intel_pt_skip_event(pt))
1732 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1734 sample.id = ptq->pt->pwrx_id;
1735 sample.stream_id = ptq->pt->pwrx_id;
1738 raw.payload = cpu_to_le64(ptq->state->pwrx_payload);
1740 sample.raw_size = perf_synth__raw_size(raw);
1741 sample.raw_data = perf_synth__raw_data(&raw);
1743 return intel_pt_deliver_synth_event(pt, event, &sample,
1744 pt->pwr_events_sample_type);
1748 * PEBS gp_regs array indexes plus 1 so that 0 means not present. Refer
1749 * intel_pt_add_gp_regs().
1751 static const int pebs_gp_regs[] = {
1752 [PERF_REG_X86_FLAGS] = 1,
1753 [PERF_REG_X86_IP] = 2,
1754 [PERF_REG_X86_AX] = 3,
1755 [PERF_REG_X86_CX] = 4,
1756 [PERF_REG_X86_DX] = 5,
1757 [PERF_REG_X86_BX] = 6,
1758 [PERF_REG_X86_SP] = 7,
1759 [PERF_REG_X86_BP] = 8,
1760 [PERF_REG_X86_SI] = 9,
1761 [PERF_REG_X86_DI] = 10,
1762 [PERF_REG_X86_R8] = 11,
1763 [PERF_REG_X86_R9] = 12,
1764 [PERF_REG_X86_R10] = 13,
1765 [PERF_REG_X86_R11] = 14,
1766 [PERF_REG_X86_R12] = 15,
1767 [PERF_REG_X86_R13] = 16,
1768 [PERF_REG_X86_R14] = 17,
1769 [PERF_REG_X86_R15] = 18,
1772 static u64 *intel_pt_add_gp_regs(struct regs_dump *intr_regs, u64 *pos,
1773 const struct intel_pt_blk_items *items,
1776 const u64 *gp_regs = items->val[INTEL_PT_GP_REGS_POS];
1777 u32 mask = items->mask[INTEL_PT_GP_REGS_POS];
1781 for (i = 0, bit = 1; i < PERF_REG_X86_64_MAX; i++, bit <<= 1) {
1782 /* Get the PEBS gp_regs array index */
1783 int n = pebs_gp_regs[i] - 1;
1788 * Add only registers that were requested (i.e. 'regs_mask') and
1789 * that were provided (i.e. 'mask'), and update the resulting
1790 * mask (i.e. 'intr_regs->mask') accordingly.
1792 if (mask & 1 << n && regs_mask & bit) {
1793 intr_regs->mask |= bit;
1794 *pos++ = gp_regs[n];
1801 #ifndef PERF_REG_X86_XMM0
1802 #define PERF_REG_X86_XMM0 32
1805 static void intel_pt_add_xmm(struct regs_dump *intr_regs, u64 *pos,
1806 const struct intel_pt_blk_items *items,
1809 u32 mask = items->has_xmm & (regs_mask >> PERF_REG_X86_XMM0);
1810 const u64 *xmm = items->xmm;
1813 * If there are any XMM registers, then there should be all of them.
1814 * Nevertheless, follow the logic to add only registers that were
1815 * requested (i.e. 'regs_mask') and that were provided (i.e. 'mask'),
1816 * and update the resulting mask (i.e. 'intr_regs->mask') accordingly.
1818 intr_regs->mask |= (u64)mask << PERF_REG_X86_XMM0;
1820 for (; mask; mask >>= 1, xmm++) {
1826 #define LBR_INFO_MISPRED (1ULL << 63)
1827 #define LBR_INFO_IN_TX (1ULL << 62)
1828 #define LBR_INFO_ABORT (1ULL << 61)
1829 #define LBR_INFO_CYCLES 0xffff
1831 /* Refer kernel's intel_pmu_store_pebs_lbrs() */
1832 static u64 intel_pt_lbr_flags(u64 info)
1835 struct branch_flags flags;
1840 u.flags.mispred = !!(info & LBR_INFO_MISPRED);
1841 u.flags.predicted = !(info & LBR_INFO_MISPRED);
1842 u.flags.in_tx = !!(info & LBR_INFO_IN_TX);
1843 u.flags.abort = !!(info & LBR_INFO_ABORT);
1844 u.flags.cycles = info & LBR_INFO_CYCLES;
1849 static void intel_pt_add_lbrs(struct branch_stack *br_stack,
1850 const struct intel_pt_blk_items *items)
1857 to = &br_stack->entries[0].from;
1859 for (i = INTEL_PT_LBR_0_POS; i <= INTEL_PT_LBR_2_POS; i++) {
1860 u32 mask = items->mask[i];
1861 const u64 *from = items->val[i];
1863 for (; mask; mask >>= 3, from += 3) {
1864 if ((mask & 7) == 7) {
1867 *to++ = intel_pt_lbr_flags(from[2]);
1874 static int intel_pt_synth_pebs_sample(struct intel_pt_queue *ptq)
1876 const struct intel_pt_blk_items *items = &ptq->state->items;
1877 struct perf_sample sample = { .ip = 0, };
1878 union perf_event *event = ptq->event_buf;
1879 struct intel_pt *pt = ptq->pt;
1880 struct evsel *evsel = pt->pebs_evsel;
1881 u64 sample_type = evsel->core.attr.sample_type;
1882 u64 id = evsel->core.id[0];
1884 u64 regs[8 * sizeof(sample.intr_regs.mask)];
1886 if (intel_pt_skip_event(pt))
1889 intel_pt_prep_a_sample(ptq, event, &sample);
1892 sample.stream_id = id;
1894 if (!evsel->core.attr.freq)
1895 sample.period = evsel->core.attr.sample_period;
1897 /* No support for non-zero CS base */
1899 sample.ip = items->ip;
1900 else if (items->has_rip)
1901 sample.ip = items->rip;
1903 sample.ip = ptq->state->from_ip;
1905 cpumode = intel_pt_cpumode(ptq, sample.ip, 0);
1907 event->sample.header.misc = cpumode | PERF_RECORD_MISC_EXACT_IP;
1909 sample.cpumode = cpumode;
1911 if (sample_type & PERF_SAMPLE_TIME) {
1914 if (items->has_timestamp)
1915 timestamp = items->timestamp;
1916 else if (!pt->timeless_decoding)
1917 timestamp = ptq->timestamp;
1919 sample.time = tsc_to_perf_time(timestamp, &pt->tc);
1922 if (sample_type & PERF_SAMPLE_CALLCHAIN &&
1923 pt->synth_opts.callchain) {
1924 thread_stack__sample(ptq->thread, ptq->cpu, ptq->chain,
1925 pt->synth_opts.callchain_sz, sample.ip,
1927 sample.callchain = ptq->chain;
1930 if (sample_type & PERF_SAMPLE_REGS_INTR &&
1931 (items->mask[INTEL_PT_GP_REGS_POS] ||
1932 items->mask[INTEL_PT_XMM_POS])) {
1933 u64 regs_mask = evsel->core.attr.sample_regs_intr;
1936 sample.intr_regs.abi = items->is_32_bit ?
1937 PERF_SAMPLE_REGS_ABI_32 :
1938 PERF_SAMPLE_REGS_ABI_64;
1939 sample.intr_regs.regs = regs;
1941 pos = intel_pt_add_gp_regs(&sample.intr_regs, regs, items, regs_mask);
1943 intel_pt_add_xmm(&sample.intr_regs, pos, items, regs_mask);
1946 if (sample_type & PERF_SAMPLE_BRANCH_STACK) {
1947 if (items->mask[INTEL_PT_LBR_0_POS] ||
1948 items->mask[INTEL_PT_LBR_1_POS] ||
1949 items->mask[INTEL_PT_LBR_2_POS]) {
1950 intel_pt_add_lbrs(ptq->last_branch, items);
1951 } else if (pt->synth_opts.last_branch) {
1952 thread_stack__br_sample(ptq->thread, ptq->cpu,
1956 ptq->last_branch->nr = 0;
1958 sample.branch_stack = ptq->last_branch;
1961 if (sample_type & PERF_SAMPLE_ADDR && items->has_mem_access_address)
1962 sample.addr = items->mem_access_address;
1964 if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) {
1966 * Refer kernel's setup_pebs_adaptive_sample_data() and
1967 * intel_hsw_weight().
1969 if (items->has_mem_access_latency) {
1970 u64 weight = items->mem_access_latency >> 32;
1973 * Starts from SPR, the mem access latency field
1974 * contains both cache latency [47:32] and instruction
1975 * latency [15:0]. The cache latency is the same as the
1976 * mem access latency on previous platforms.
1978 * In practice, no memory access could last than 4G
1979 * cycles. Use latency >> 32 to distinguish the
1980 * different format of the mem access latency field.
1983 sample.weight = weight & 0xffff;
1984 sample.ins_lat = items->mem_access_latency & 0xffff;
1986 sample.weight = items->mem_access_latency;
1988 if (!sample.weight && items->has_tsx_aux_info) {
1989 /* Cycles last block */
1990 sample.weight = (u32)items->tsx_aux_info;
1994 if (sample_type & PERF_SAMPLE_TRANSACTION && items->has_tsx_aux_info) {
1995 u64 ax = items->has_rax ? items->rax : 0;
1996 /* Refer kernel's intel_hsw_transaction() */
1997 u64 txn = (u8)(items->tsx_aux_info >> 32);
1999 /* For RTM XABORTs also log the abort code from AX */
2000 if (txn & PERF_TXN_TRANSACTION && ax & 1)
2001 txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
2002 sample.transaction = txn;
2005 return intel_pt_deliver_synth_event(pt, event, &sample, sample_type);
2008 static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu,
2009 pid_t pid, pid_t tid, u64 ip, u64 timestamp)
2011 union perf_event event;
2012 char msg[MAX_AUXTRACE_ERROR_MSG];
2015 if (pt->synth_opts.error_minus_flags) {
2016 if (code == INTEL_PT_ERR_OVR &&
2017 pt->synth_opts.error_minus_flags & AUXTRACE_ERR_FLG_OVERFLOW)
2019 if (code == INTEL_PT_ERR_LOST &&
2020 pt->synth_opts.error_minus_flags & AUXTRACE_ERR_FLG_DATA_LOST)
2024 intel_pt__strerror(code, msg, MAX_AUXTRACE_ERROR_MSG);
2026 auxtrace_synth_error(&event.auxtrace_error, PERF_AUXTRACE_ERROR_ITRACE,
2027 code, cpu, pid, tid, ip, msg, timestamp);
2029 err = perf_session__deliver_synth_event(pt->session, &event, NULL);
2031 pr_err("Intel Processor Trace: failed to deliver error event, error %d\n",
2037 static int intel_ptq_synth_error(struct intel_pt_queue *ptq,
2038 const struct intel_pt_state *state)
2040 struct intel_pt *pt = ptq->pt;
2041 u64 tm = ptq->timestamp;
2043 tm = pt->timeless_decoding ? 0 : tsc_to_perf_time(tm, &pt->tc);
2045 return intel_pt_synth_error(pt, state->err, ptq->cpu, ptq->pid,
2046 ptq->tid, state->from_ip, tm);
2049 static int intel_pt_next_tid(struct intel_pt *pt, struct intel_pt_queue *ptq)
2051 struct auxtrace_queue *queue;
2052 pid_t tid = ptq->next_tid;
2058 intel_pt_log("switch: cpu %d tid %d\n", ptq->cpu, tid);
2060 err = machine__set_current_tid(pt->machine, ptq->cpu, -1, tid);
2062 queue = &pt->queues.queue_array[ptq->queue_nr];
2063 intel_pt_set_pid_tid_cpu(pt, queue);
2070 static inline bool intel_pt_is_switch_ip(struct intel_pt_queue *ptq, u64 ip)
2072 struct intel_pt *pt = ptq->pt;
2074 return ip == pt->switch_ip &&
2075 (ptq->flags & PERF_IP_FLAG_BRANCH) &&
2076 !(ptq->flags & (PERF_IP_FLAG_CONDITIONAL | PERF_IP_FLAG_ASYNC |
2077 PERF_IP_FLAG_INTERRUPT | PERF_IP_FLAG_TX_ABORT));
2080 #define INTEL_PT_PWR_EVT (INTEL_PT_MWAIT_OP | INTEL_PT_PWR_ENTRY | \
2081 INTEL_PT_EX_STOP | INTEL_PT_PWR_EXIT)
2083 static int intel_pt_sample(struct intel_pt_queue *ptq)
2085 const struct intel_pt_state *state = ptq->state;
2086 struct intel_pt *pt = ptq->pt;
2089 if (!ptq->have_sample)
2092 ptq->have_sample = false;
2094 ptq->ipc_insn_cnt = ptq->state->tot_insn_cnt;
2095 ptq->ipc_cyc_cnt = ptq->state->tot_cyc_cnt;
2098 * Do PEBS first to allow for the possibility that the PEBS timestamp
2099 * precedes the current timestamp.
2101 if (pt->sample_pebs && state->type & INTEL_PT_BLK_ITEMS) {
2102 err = intel_pt_synth_pebs_sample(ptq);
2107 if (pt->sample_pwr_events) {
2108 if (state->type & INTEL_PT_PSB_EVT) {
2109 err = intel_pt_synth_psb_sample(ptq);
2113 if (ptq->state->cbr != ptq->cbr_seen) {
2114 err = intel_pt_synth_cbr_sample(ptq);
2118 if (state->type & INTEL_PT_PWR_EVT) {
2119 if (state->type & INTEL_PT_MWAIT_OP) {
2120 err = intel_pt_synth_mwait_sample(ptq);
2124 if (state->type & INTEL_PT_PWR_ENTRY) {
2125 err = intel_pt_synth_pwre_sample(ptq);
2129 if (state->type & INTEL_PT_EX_STOP) {
2130 err = intel_pt_synth_exstop_sample(ptq);
2134 if (state->type & INTEL_PT_PWR_EXIT) {
2135 err = intel_pt_synth_pwrx_sample(ptq);
2142 if (pt->sample_instructions && (state->type & INTEL_PT_INSTRUCTION)) {
2143 err = intel_pt_synth_instruction_sample(ptq);
2148 if (pt->sample_transactions && (state->type & INTEL_PT_TRANSACTION)) {
2149 err = intel_pt_synth_transaction_sample(ptq);
2154 if (pt->sample_ptwrites && (state->type & INTEL_PT_PTW)) {
2155 err = intel_pt_synth_ptwrite_sample(ptq);
2160 if (!(state->type & INTEL_PT_BRANCH))
2163 if (pt->use_thread_stack) {
2164 thread_stack__event(ptq->thread, ptq->cpu, ptq->flags,
2165 state->from_ip, state->to_ip, ptq->insn_len,
2166 state->trace_nr, pt->callstack,
2167 pt->br_stack_sz_plus,
2170 thread_stack__set_trace_nr(ptq->thread, ptq->cpu, state->trace_nr);
2173 if (pt->sample_branches) {
2174 if (state->from_nr != state->to_nr &&
2175 state->from_ip && state->to_ip) {
2176 struct intel_pt_state *st = (struct intel_pt_state *)state;
2177 u64 to_ip = st->to_ip;
2178 u64 from_ip = st->from_ip;
2181 * perf cannot handle having different machines for ip
2182 * and addr, so create 2 branches.
2185 err = intel_pt_synth_branch_sample(ptq);
2190 err = intel_pt_synth_branch_sample(ptq);
2191 st->from_ip = from_ip;
2193 err = intel_pt_synth_branch_sample(ptq);
2199 if (!ptq->sync_switch)
2202 if (intel_pt_is_switch_ip(ptq, state->to_ip)) {
2203 switch (ptq->switch_state) {
2204 case INTEL_PT_SS_NOT_TRACING:
2205 case INTEL_PT_SS_UNKNOWN:
2206 case INTEL_PT_SS_EXPECTING_SWITCH_IP:
2207 err = intel_pt_next_tid(pt, ptq);
2210 ptq->switch_state = INTEL_PT_SS_TRACING;
2213 ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_EVENT;
2216 } else if (!state->to_ip) {
2217 ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
2218 } else if (ptq->switch_state == INTEL_PT_SS_NOT_TRACING) {
2219 ptq->switch_state = INTEL_PT_SS_UNKNOWN;
2220 } else if (ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
2221 state->to_ip == pt->ptss_ip &&
2222 (ptq->flags & PERF_IP_FLAG_CALL)) {
2223 ptq->switch_state = INTEL_PT_SS_TRACING;
2229 static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip)
2231 struct machine *machine = pt->machine;
2233 struct symbol *sym, *start;
2234 u64 ip, switch_ip = 0;
2240 map = machine__kernel_map(machine);
2247 start = dso__first_symbol(map->dso);
2249 for (sym = start; sym; sym = dso__next_symbol(sym)) {
2250 if (sym->binding == STB_GLOBAL &&
2251 !strcmp(sym->name, "__switch_to")) {
2252 ip = map->unmap_ip(map, sym->start);
2253 if (ip >= map->start && ip < map->end) {
2260 if (!switch_ip || !ptss_ip)
2263 if (pt->have_sched_switch == 1)
2264 ptss = "perf_trace_sched_switch";
2266 ptss = "__perf_event_task_sched_out";
2268 for (sym = start; sym; sym = dso__next_symbol(sym)) {
2269 if (!strcmp(sym->name, ptss)) {
2270 ip = map->unmap_ip(map, sym->start);
2271 if (ip >= map->start && ip < map->end) {
2281 static void intel_pt_enable_sync_switch(struct intel_pt *pt)
2285 pt->sync_switch = true;
2287 for (i = 0; i < pt->queues.nr_queues; i++) {
2288 struct auxtrace_queue *queue = &pt->queues.queue_array[i];
2289 struct intel_pt_queue *ptq = queue->priv;
2292 ptq->sync_switch = true;
2297 * To filter against time ranges, it is only necessary to look at the next start
2300 static bool intel_pt_next_time(struct intel_pt_queue *ptq)
2302 struct intel_pt *pt = ptq->pt;
2304 if (ptq->sel_start) {
2305 /* Next time is an end time */
2306 ptq->sel_start = false;
2307 ptq->sel_timestamp = pt->time_ranges[ptq->sel_idx].end;
2309 } else if (ptq->sel_idx + 1 < pt->range_cnt) {
2310 /* Next time is a start time */
2311 ptq->sel_start = true;
2313 ptq->sel_timestamp = pt->time_ranges[ptq->sel_idx].start;
2321 static int intel_pt_time_filter(struct intel_pt_queue *ptq, u64 *ff_timestamp)
2326 if (ptq->sel_start) {
2327 if (ptq->timestamp >= ptq->sel_timestamp) {
2328 /* After start time, so consider next time */
2329 intel_pt_next_time(ptq);
2330 if (!ptq->sel_timestamp) {
2334 /* Check against end time */
2337 /* Before start time, so fast forward */
2338 ptq->have_sample = false;
2339 if (ptq->sel_timestamp > *ff_timestamp) {
2340 if (ptq->sync_switch) {
2341 intel_pt_next_tid(ptq->pt, ptq);
2342 ptq->switch_state = INTEL_PT_SS_UNKNOWN;
2344 *ff_timestamp = ptq->sel_timestamp;
2345 err = intel_pt_fast_forward(ptq->decoder,
2346 ptq->sel_timestamp);
2351 } else if (ptq->timestamp > ptq->sel_timestamp) {
2352 /* After end time, so consider next time */
2353 if (!intel_pt_next_time(ptq)) {
2354 /* No next time range, so stop decoding */
2355 ptq->have_sample = false;
2356 ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
2359 /* Check against next start time */
2362 /* Before end time */
2368 static int intel_pt_run_decoder(struct intel_pt_queue *ptq, u64 *timestamp)
2370 const struct intel_pt_state *state = ptq->state;
2371 struct intel_pt *pt = ptq->pt;
2372 u64 ff_timestamp = 0;
2375 if (!pt->kernel_start) {
2376 pt->kernel_start = machine__kernel_start(pt->machine);
2377 if (pt->per_cpu_mmaps &&
2378 (pt->have_sched_switch == 1 || pt->have_sched_switch == 3) &&
2379 !pt->timeless_decoding && intel_pt_tracing_kernel(pt) &&
2380 !pt->sampling_mode) {
2381 pt->switch_ip = intel_pt_switch_ip(pt, &pt->ptss_ip);
2382 if (pt->switch_ip) {
2383 intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n",
2384 pt->switch_ip, pt->ptss_ip);
2385 intel_pt_enable_sync_switch(pt);
2390 intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
2391 ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
2393 err = intel_pt_sample(ptq);
2397 state = intel_pt_decode(ptq->decoder);
2399 if (state->err == INTEL_PT_ERR_NODATA)
2401 if (ptq->sync_switch &&
2402 state->from_ip >= pt->kernel_start) {
2403 ptq->sync_switch = false;
2404 intel_pt_next_tid(pt, ptq);
2406 if (pt->synth_opts.errors) {
2407 err = intel_ptq_synth_error(ptq, state);
2415 ptq->have_sample = true;
2416 intel_pt_sample_flags(ptq);
2418 /* Use estimated TSC upon return to user space */
2420 (state->from_ip >= pt->kernel_start || !state->from_ip) &&
2421 state->to_ip && state->to_ip < pt->kernel_start) {
2422 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
2423 state->timestamp, state->est_timestamp);
2424 ptq->timestamp = state->est_timestamp;
2425 /* Use estimated TSC in unknown switch state */
2426 } else if (ptq->sync_switch &&
2427 ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
2428 intel_pt_is_switch_ip(ptq, state->to_ip) &&
2429 ptq->next_tid == -1) {
2430 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
2431 state->timestamp, state->est_timestamp);
2432 ptq->timestamp = state->est_timestamp;
2433 } else if (state->timestamp > ptq->timestamp) {
2434 ptq->timestamp = state->timestamp;
2437 if (ptq->sel_timestamp) {
2438 err = intel_pt_time_filter(ptq, &ff_timestamp);
2443 if (!pt->timeless_decoding && ptq->timestamp >= *timestamp) {
2444 *timestamp = ptq->timestamp;
2451 static inline int intel_pt_update_queues(struct intel_pt *pt)
2453 if (pt->queues.new_data) {
2454 pt->queues.new_data = false;
2455 return intel_pt_setup_queues(pt);
2460 static int intel_pt_process_queues(struct intel_pt *pt, u64 timestamp)
2462 unsigned int queue_nr;
2467 struct auxtrace_queue *queue;
2468 struct intel_pt_queue *ptq;
2470 if (!pt->heap.heap_cnt)
2473 if (pt->heap.heap_array[0].ordinal >= timestamp)
2476 queue_nr = pt->heap.heap_array[0].queue_nr;
2477 queue = &pt->queues.queue_array[queue_nr];
2480 intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n",
2481 queue_nr, pt->heap.heap_array[0].ordinal,
2484 auxtrace_heap__pop(&pt->heap);
2486 if (pt->heap.heap_cnt) {
2487 ts = pt->heap.heap_array[0].ordinal + 1;
2494 intel_pt_set_pid_tid_cpu(pt, queue);
2496 ret = intel_pt_run_decoder(ptq, &ts);
2499 auxtrace_heap__add(&pt->heap, queue_nr, ts);
2504 ret = auxtrace_heap__add(&pt->heap, queue_nr, ts);
2508 ptq->on_heap = false;
2515 static int intel_pt_process_timeless_queues(struct intel_pt *pt, pid_t tid,
2518 struct auxtrace_queues *queues = &pt->queues;
2522 for (i = 0; i < queues->nr_queues; i++) {
2523 struct auxtrace_queue *queue = &pt->queues.queue_array[i];
2524 struct intel_pt_queue *ptq = queue->priv;
2526 if (ptq && (tid == -1 || ptq->tid == tid)) {
2528 intel_pt_set_pid_tid_cpu(pt, queue);
2529 intel_pt_run_decoder(ptq, &ts);
2535 static void intel_pt_sample_set_pid_tid_cpu(struct intel_pt_queue *ptq,
2536 struct auxtrace_queue *queue,
2537 struct perf_sample *sample)
2539 struct machine *m = ptq->pt->machine;
2541 ptq->pid = sample->pid;
2542 ptq->tid = sample->tid;
2543 ptq->cpu = queue->cpu;
2545 intel_pt_log("queue %u cpu %d pid %d tid %d\n",
2546 ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
2548 thread__zput(ptq->thread);
2553 if (ptq->pid == -1) {
2554 ptq->thread = machine__find_thread(m, -1, ptq->tid);
2556 ptq->pid = ptq->thread->pid_;
2560 ptq->thread = machine__findnew_thread(m, ptq->pid, ptq->tid);
2563 static int intel_pt_process_timeless_sample(struct intel_pt *pt,
2564 struct perf_sample *sample)
2566 struct auxtrace_queue *queue;
2567 struct intel_pt_queue *ptq;
2570 queue = auxtrace_queues__sample_queue(&pt->queues, sample, pt->session);
2579 ptq->time = sample->time;
2580 intel_pt_sample_set_pid_tid_cpu(ptq, queue, sample);
2581 intel_pt_run_decoder(ptq, &ts);
2585 static int intel_pt_lost(struct intel_pt *pt, struct perf_sample *sample)
2587 return intel_pt_synth_error(pt, INTEL_PT_ERR_LOST, sample->cpu,
2588 sample->pid, sample->tid, 0, sample->time);
2591 static struct intel_pt_queue *intel_pt_cpu_to_ptq(struct intel_pt *pt, int cpu)
2595 if (cpu < 0 || !pt->queues.nr_queues)
2598 if ((unsigned)cpu >= pt->queues.nr_queues)
2599 i = pt->queues.nr_queues - 1;
2603 if (pt->queues.queue_array[i].cpu == cpu)
2604 return pt->queues.queue_array[i].priv;
2606 for (j = 0; i > 0; j++) {
2607 if (pt->queues.queue_array[--i].cpu == cpu)
2608 return pt->queues.queue_array[i].priv;
2611 for (; j < pt->queues.nr_queues; j++) {
2612 if (pt->queues.queue_array[j].cpu == cpu)
2613 return pt->queues.queue_array[j].priv;
2619 static int intel_pt_sync_switch(struct intel_pt *pt, int cpu, pid_t tid,
2622 struct intel_pt_queue *ptq;
2625 if (!pt->sync_switch)
2628 ptq = intel_pt_cpu_to_ptq(pt, cpu);
2629 if (!ptq || !ptq->sync_switch)
2632 switch (ptq->switch_state) {
2633 case INTEL_PT_SS_NOT_TRACING:
2635 case INTEL_PT_SS_UNKNOWN:
2636 case INTEL_PT_SS_TRACING:
2637 ptq->next_tid = tid;
2638 ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_IP;
2640 case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
2641 if (!ptq->on_heap) {
2642 ptq->timestamp = perf_time_to_tsc(timestamp,
2644 err = auxtrace_heap__add(&pt->heap, ptq->queue_nr,
2648 ptq->on_heap = true;
2650 ptq->switch_state = INTEL_PT_SS_TRACING;
2652 case INTEL_PT_SS_EXPECTING_SWITCH_IP:
2653 intel_pt_log("ERROR: cpu %d expecting switch ip\n", cpu);
2664 static int intel_pt_process_switch(struct intel_pt *pt,
2665 struct perf_sample *sample)
2669 struct evsel *evsel = evlist__id2evsel(pt->session->evlist, sample->id);
2671 if (evsel != pt->switch_evsel)
2674 tid = evsel__intval(evsel, sample, "next_pid");
2677 intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
2678 cpu, tid, sample->time, perf_time_to_tsc(sample->time,
2681 ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
2685 return machine__set_current_tid(pt->machine, cpu, -1, tid);
2688 static int intel_pt_context_switch_in(struct intel_pt *pt,
2689 struct perf_sample *sample)
2691 pid_t pid = sample->pid;
2692 pid_t tid = sample->tid;
2693 int cpu = sample->cpu;
2695 if (pt->sync_switch) {
2696 struct intel_pt_queue *ptq;
2698 ptq = intel_pt_cpu_to_ptq(pt, cpu);
2699 if (ptq && ptq->sync_switch) {
2701 switch (ptq->switch_state) {
2702 case INTEL_PT_SS_NOT_TRACING:
2703 case INTEL_PT_SS_UNKNOWN:
2704 case INTEL_PT_SS_TRACING:
2706 case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
2707 case INTEL_PT_SS_EXPECTING_SWITCH_IP:
2708 ptq->switch_state = INTEL_PT_SS_TRACING;
2717 * If the current tid has not been updated yet, ensure it is now that
2718 * a "switch in" event has occurred.
2720 if (machine__get_current_tid(pt->machine, cpu) == tid)
2723 return machine__set_current_tid(pt->machine, cpu, pid, tid);
2726 static int intel_pt_context_switch(struct intel_pt *pt, union perf_event *event,
2727 struct perf_sample *sample)
2729 bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT;
2735 if (pt->have_sched_switch == 3) {
2737 return intel_pt_context_switch_in(pt, sample);
2738 if (event->header.type != PERF_RECORD_SWITCH_CPU_WIDE) {
2739 pr_err("Expecting CPU-wide context switch event\n");
2742 pid = event->context_switch.next_prev_pid;
2743 tid = event->context_switch.next_prev_tid;
2752 intel_pt_log("context_switch event has no tid\n");
2754 ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
2758 return machine__set_current_tid(pt->machine, cpu, pid, tid);
2761 static int intel_pt_process_itrace_start(struct intel_pt *pt,
2762 union perf_event *event,
2763 struct perf_sample *sample)
2765 if (!pt->per_cpu_mmaps)
2768 intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
2769 sample->cpu, event->itrace_start.pid,
2770 event->itrace_start.tid, sample->time,
2771 perf_time_to_tsc(sample->time, &pt->tc));
2773 return machine__set_current_tid(pt->machine, sample->cpu,
2774 event->itrace_start.pid,
2775 event->itrace_start.tid);
2778 static int intel_pt_find_map(struct thread *thread, u8 cpumode, u64 addr,
2779 struct addr_location *al)
2781 if (!al->map || addr < al->map->start || addr >= al->map->end) {
2782 if (!thread__find_map(thread, cpumode, addr, al))
2789 /* Invalidate all instruction cache entries that overlap the text poke */
2790 static int intel_pt_text_poke(struct intel_pt *pt, union perf_event *event)
2792 u8 cpumode = event->header.misc & PERF_RECORD_MISC_CPUMODE_MASK;
2793 u64 addr = event->text_poke.addr + event->text_poke.new_len - 1;
2794 /* Assume text poke begins in a basic block no more than 4096 bytes */
2795 int cnt = 4096 + event->text_poke.new_len;
2796 struct thread *thread = pt->unknown_thread;
2797 struct addr_location al = { .map = NULL };
2798 struct machine *machine = pt->machine;
2799 struct intel_pt_cache_entry *e;
2802 if (!event->text_poke.new_len)
2805 for (; cnt; cnt--, addr--) {
2806 if (intel_pt_find_map(thread, cpumode, addr, &al)) {
2807 if (addr < event->text_poke.addr)
2812 if (!al.map->dso || !al.map->dso->auxtrace_cache)
2815 offset = al.map->map_ip(al.map, addr);
2817 e = intel_pt_cache_lookup(al.map->dso, machine, offset);
2821 if (addr + e->byte_cnt + e->length <= event->text_poke.addr) {
2823 * No overlap. Working backwards there cannot be another
2824 * basic block that overlaps the text poke if there is a
2825 * branch instruction before the text poke address.
2827 if (e->branch != INTEL_PT_BR_NO_BRANCH)
2830 intel_pt_cache_invalidate(al.map->dso, machine, offset);
2831 intel_pt_log("Invalidated instruction cache for %s at %#"PRIx64"\n",
2832 al.map->dso->long_name, addr);
2839 static int intel_pt_process_event(struct perf_session *session,
2840 union perf_event *event,
2841 struct perf_sample *sample,
2842 struct perf_tool *tool)
2844 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2852 if (!tool->ordered_events) {
2853 pr_err("Intel Processor Trace requires ordered events\n");
2857 if (sample->time && sample->time != (u64)-1)
2858 timestamp = perf_time_to_tsc(sample->time, &pt->tc);
2862 if (timestamp || pt->timeless_decoding) {
2863 err = intel_pt_update_queues(pt);
2868 if (pt->timeless_decoding) {
2869 if (pt->sampling_mode) {
2870 if (sample->aux_sample.size)
2871 err = intel_pt_process_timeless_sample(pt,
2873 } else if (event->header.type == PERF_RECORD_EXIT) {
2874 err = intel_pt_process_timeless_queues(pt,
2878 } else if (timestamp) {
2879 err = intel_pt_process_queues(pt, timestamp);
2884 if (event->header.type == PERF_RECORD_SAMPLE) {
2885 if (pt->synth_opts.add_callchain && !sample->callchain)
2886 intel_pt_add_callchain(pt, sample);
2887 if (pt->synth_opts.add_last_branch && !sample->branch_stack)
2888 intel_pt_add_br_stack(pt, sample);
2891 if (event->header.type == PERF_RECORD_AUX &&
2892 (event->aux.flags & PERF_AUX_FLAG_TRUNCATED) &&
2893 pt->synth_opts.errors) {
2894 err = intel_pt_lost(pt, sample);
2899 if (pt->switch_evsel && event->header.type == PERF_RECORD_SAMPLE)
2900 err = intel_pt_process_switch(pt, sample);
2901 else if (event->header.type == PERF_RECORD_ITRACE_START)
2902 err = intel_pt_process_itrace_start(pt, event, sample);
2903 else if (event->header.type == PERF_RECORD_SWITCH ||
2904 event->header.type == PERF_RECORD_SWITCH_CPU_WIDE)
2905 err = intel_pt_context_switch(pt, event, sample);
2907 if (!err && event->header.type == PERF_RECORD_TEXT_POKE)
2908 err = intel_pt_text_poke(pt, event);
2910 if (intel_pt_enable_logging && intel_pt_log_events(pt, sample->time)) {
2911 intel_pt_log("event %u: cpu %d time %"PRIu64" tsc %#"PRIx64" ",
2912 event->header.type, sample->cpu, sample->time, timestamp);
2913 intel_pt_log_event(event);
2919 static int intel_pt_flush(struct perf_session *session, struct perf_tool *tool)
2921 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2928 if (!tool->ordered_events)
2931 ret = intel_pt_update_queues(pt);
2935 if (pt->timeless_decoding)
2936 return intel_pt_process_timeless_queues(pt, -1,
2939 return intel_pt_process_queues(pt, MAX_TIMESTAMP);
2942 static void intel_pt_free_events(struct perf_session *session)
2944 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2946 struct auxtrace_queues *queues = &pt->queues;
2949 for (i = 0; i < queues->nr_queues; i++) {
2950 intel_pt_free_queue(queues->queue_array[i].priv);
2951 queues->queue_array[i].priv = NULL;
2953 intel_pt_log_disable();
2954 auxtrace_queues__free(queues);
2957 static void intel_pt_free(struct perf_session *session)
2959 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2962 auxtrace_heap__free(&pt->heap);
2963 intel_pt_free_events(session);
2964 session->auxtrace = NULL;
2965 thread__put(pt->unknown_thread);
2966 addr_filters__exit(&pt->filts);
2969 zfree(&pt->time_ranges);
2973 static bool intel_pt_evsel_is_auxtrace(struct perf_session *session,
2974 struct evsel *evsel)
2976 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2979 return evsel->core.attr.type == pt->pmu_type;
2982 static int intel_pt_process_auxtrace_event(struct perf_session *session,
2983 union perf_event *event,
2984 struct perf_tool *tool __maybe_unused)
2986 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2989 if (!pt->data_queued) {
2990 struct auxtrace_buffer *buffer;
2992 int fd = perf_data__fd(session->data);
2995 if (perf_data__is_pipe(session->data)) {
2998 data_offset = lseek(fd, 0, SEEK_CUR);
2999 if (data_offset == -1)
3003 err = auxtrace_queues__add_event(&pt->queues, session, event,
3004 data_offset, &buffer);
3008 /* Dump here now we have copied a piped trace out of the pipe */
3010 if (auxtrace_buffer__get_data(buffer, fd)) {
3011 intel_pt_dump_event(pt, buffer->data,
3013 auxtrace_buffer__put_data(buffer);
3021 static int intel_pt_queue_data(struct perf_session *session,
3022 struct perf_sample *sample,
3023 union perf_event *event, u64 data_offset)
3025 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
3030 return auxtrace_queues__add_event(&pt->queues, session, event,
3034 if (sample->time && sample->time != (u64)-1)
3035 timestamp = perf_time_to_tsc(sample->time, &pt->tc);
3039 return auxtrace_queues__add_sample(&pt->queues, session, sample,
3040 data_offset, timestamp);
3043 struct intel_pt_synth {
3044 struct perf_tool dummy_tool;
3045 struct perf_session *session;
3048 static int intel_pt_event_synth(struct perf_tool *tool,
3049 union perf_event *event,
3050 struct perf_sample *sample __maybe_unused,
3051 struct machine *machine __maybe_unused)
3053 struct intel_pt_synth *intel_pt_synth =
3054 container_of(tool, struct intel_pt_synth, dummy_tool);
3056 return perf_session__deliver_synth_event(intel_pt_synth->session, event,
3060 static int intel_pt_synth_event(struct perf_session *session, const char *name,
3061 struct perf_event_attr *attr, u64 id)
3063 struct intel_pt_synth intel_pt_synth;
3066 pr_debug("Synthesizing '%s' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
3067 name, id, (u64)attr->sample_type);
3069 memset(&intel_pt_synth, 0, sizeof(struct intel_pt_synth));
3070 intel_pt_synth.session = session;
3072 err = perf_event__synthesize_attr(&intel_pt_synth.dummy_tool, attr, 1,
3073 &id, intel_pt_event_synth);
3075 pr_err("%s: failed to synthesize '%s' event type\n",
3081 static void intel_pt_set_event_name(struct evlist *evlist, u64 id,
3084 struct evsel *evsel;
3086 evlist__for_each_entry(evlist, evsel) {
3087 if (evsel->core.id && evsel->core.id[0] == id) {
3089 zfree(&evsel->name);
3090 evsel->name = strdup(name);
3096 static struct evsel *intel_pt_evsel(struct intel_pt *pt,
3097 struct evlist *evlist)
3099 struct evsel *evsel;
3101 evlist__for_each_entry(evlist, evsel) {
3102 if (evsel->core.attr.type == pt->pmu_type && evsel->core.ids)
3109 static int intel_pt_synth_events(struct intel_pt *pt,
3110 struct perf_session *session)
3112 struct evlist *evlist = session->evlist;
3113 struct evsel *evsel = intel_pt_evsel(pt, evlist);
3114 struct perf_event_attr attr;
3119 pr_debug("There are no selected events with Intel Processor Trace data\n");
3123 memset(&attr, 0, sizeof(struct perf_event_attr));
3124 attr.size = sizeof(struct perf_event_attr);
3125 attr.type = PERF_TYPE_HARDWARE;
3126 attr.sample_type = evsel->core.attr.sample_type & PERF_SAMPLE_MASK;
3127 attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID |
3129 if (pt->timeless_decoding)
3130 attr.sample_type &= ~(u64)PERF_SAMPLE_TIME;
3132 attr.sample_type |= PERF_SAMPLE_TIME;
3133 if (!pt->per_cpu_mmaps)
3134 attr.sample_type &= ~(u64)PERF_SAMPLE_CPU;
3135 attr.exclude_user = evsel->core.attr.exclude_user;
3136 attr.exclude_kernel = evsel->core.attr.exclude_kernel;
3137 attr.exclude_hv = evsel->core.attr.exclude_hv;
3138 attr.exclude_host = evsel->core.attr.exclude_host;
3139 attr.exclude_guest = evsel->core.attr.exclude_guest;
3140 attr.sample_id_all = evsel->core.attr.sample_id_all;
3141 attr.read_format = evsel->core.attr.read_format;
3143 id = evsel->core.id[0] + 1000000000;
3147 if (pt->synth_opts.branches) {
3148 attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
3149 attr.sample_period = 1;
3150 attr.sample_type |= PERF_SAMPLE_ADDR;
3151 err = intel_pt_synth_event(session, "branches", &attr, id);
3154 pt->sample_branches = true;
3155 pt->branches_sample_type = attr.sample_type;
3156 pt->branches_id = id;
3158 attr.sample_type &= ~(u64)PERF_SAMPLE_ADDR;
3161 if (pt->synth_opts.callchain)
3162 attr.sample_type |= PERF_SAMPLE_CALLCHAIN;
3163 if (pt->synth_opts.last_branch) {
3164 attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
3166 * We don't use the hardware index, but the sample generation
3167 * code uses the new format branch_stack with this field,
3168 * so the event attributes must indicate that it's present.
3170 attr.branch_sample_type |= PERF_SAMPLE_BRANCH_HW_INDEX;
3173 if (pt->synth_opts.instructions) {
3174 attr.config = PERF_COUNT_HW_INSTRUCTIONS;
3175 if (pt->synth_opts.period_type == PERF_ITRACE_PERIOD_NANOSECS)
3176 attr.sample_period =
3177 intel_pt_ns_to_ticks(pt, pt->synth_opts.period);
3179 attr.sample_period = pt->synth_opts.period;
3180 err = intel_pt_synth_event(session, "instructions", &attr, id);
3183 pt->sample_instructions = true;
3184 pt->instructions_sample_type = attr.sample_type;
3185 pt->instructions_id = id;
3189 attr.sample_type &= ~(u64)PERF_SAMPLE_PERIOD;
3190 attr.sample_period = 1;
3192 if (pt->synth_opts.transactions) {
3193 attr.config = PERF_COUNT_HW_INSTRUCTIONS;
3194 err = intel_pt_synth_event(session, "transactions", &attr, id);
3197 pt->sample_transactions = true;
3198 pt->transactions_sample_type = attr.sample_type;
3199 pt->transactions_id = id;
3200 intel_pt_set_event_name(evlist, id, "transactions");
3204 attr.type = PERF_TYPE_SYNTH;
3205 attr.sample_type |= PERF_SAMPLE_RAW;
3207 if (pt->synth_opts.ptwrites) {
3208 attr.config = PERF_SYNTH_INTEL_PTWRITE;
3209 err = intel_pt_synth_event(session, "ptwrite", &attr, id);
3212 pt->sample_ptwrites = true;
3213 pt->ptwrites_sample_type = attr.sample_type;
3214 pt->ptwrites_id = id;
3215 intel_pt_set_event_name(evlist, id, "ptwrite");
3219 if (pt->synth_opts.pwr_events) {
3220 pt->sample_pwr_events = true;
3221 pt->pwr_events_sample_type = attr.sample_type;
3223 attr.config = PERF_SYNTH_INTEL_CBR;
3224 err = intel_pt_synth_event(session, "cbr", &attr, id);
3228 intel_pt_set_event_name(evlist, id, "cbr");
3231 attr.config = PERF_SYNTH_INTEL_PSB;
3232 err = intel_pt_synth_event(session, "psb", &attr, id);
3236 intel_pt_set_event_name(evlist, id, "psb");
3240 if (pt->synth_opts.pwr_events && (evsel->core.attr.config & 0x10)) {
3241 attr.config = PERF_SYNTH_INTEL_MWAIT;
3242 err = intel_pt_synth_event(session, "mwait", &attr, id);
3246 intel_pt_set_event_name(evlist, id, "mwait");
3249 attr.config = PERF_SYNTH_INTEL_PWRE;
3250 err = intel_pt_synth_event(session, "pwre", &attr, id);
3254 intel_pt_set_event_name(evlist, id, "pwre");
3257 attr.config = PERF_SYNTH_INTEL_EXSTOP;
3258 err = intel_pt_synth_event(session, "exstop", &attr, id);
3262 intel_pt_set_event_name(evlist, id, "exstop");
3265 attr.config = PERF_SYNTH_INTEL_PWRX;
3266 err = intel_pt_synth_event(session, "pwrx", &attr, id);
3270 intel_pt_set_event_name(evlist, id, "pwrx");
3277 static void intel_pt_setup_pebs_events(struct intel_pt *pt)
3279 struct evsel *evsel;
3281 if (!pt->synth_opts.other_events)
3284 evlist__for_each_entry(pt->session->evlist, evsel) {
3285 if (evsel->core.attr.aux_output && evsel->core.id) {
3286 pt->sample_pebs = true;
3287 pt->pebs_evsel = evsel;
3293 static struct evsel *intel_pt_find_sched_switch(struct evlist *evlist)
3295 struct evsel *evsel;
3297 evlist__for_each_entry_reverse(evlist, evsel) {
3298 const char *name = evsel__name(evsel);
3300 if (!strcmp(name, "sched:sched_switch"))
3307 static bool intel_pt_find_switch(struct evlist *evlist)
3309 struct evsel *evsel;
3311 evlist__for_each_entry(evlist, evsel) {
3312 if (evsel->core.attr.context_switch)
3319 static int intel_pt_perf_config(const char *var, const char *value, void *data)
3321 struct intel_pt *pt = data;
3323 if (!strcmp(var, "intel-pt.mispred-all"))
3324 pt->mispred_all = perf_config_bool(var, value);
3329 /* Find least TSC which converts to ns or later */
3330 static u64 intel_pt_tsc_start(u64 ns, struct intel_pt *pt)
3334 tsc = perf_time_to_tsc(ns, &pt->tc);
3337 tm = tsc_to_perf_time(tsc, &pt->tc);
3344 tm = tsc_to_perf_time(++tsc, &pt->tc);
3349 /* Find greatest TSC which converts to ns or earlier */
3350 static u64 intel_pt_tsc_end(u64 ns, struct intel_pt *pt)
3354 tsc = perf_time_to_tsc(ns, &pt->tc);
3357 tm = tsc_to_perf_time(tsc, &pt->tc);
3364 tm = tsc_to_perf_time(--tsc, &pt->tc);
3369 static int intel_pt_setup_time_ranges(struct intel_pt *pt,
3370 struct itrace_synth_opts *opts)
3372 struct perf_time_interval *p = opts->ptime_range;
3373 int n = opts->range_num;
3376 if (!n || !p || pt->timeless_decoding)
3379 pt->time_ranges = calloc(n, sizeof(struct range));
3380 if (!pt->time_ranges)
3385 intel_pt_log("%s: %u range(s)\n", __func__, n);
3387 for (i = 0; i < n; i++) {
3388 struct range *r = &pt->time_ranges[i];
3389 u64 ts = p[i].start;
3393 * Take care to ensure the TSC range matches the perf-time range
3394 * when converted back to perf-time.
3396 r->start = ts ? intel_pt_tsc_start(ts, pt) : 0;
3397 r->end = te ? intel_pt_tsc_end(te, pt) : 0;
3399 intel_pt_log("range %d: perf time interval: %"PRIu64" to %"PRIu64"\n",
3401 intel_pt_log("range %d: TSC time interval: %#"PRIx64" to %#"PRIx64"\n",
3402 i, r->start, r->end);
3408 static const char * const intel_pt_info_fmts[] = {
3409 [INTEL_PT_PMU_TYPE] = " PMU Type %"PRId64"\n",
3410 [INTEL_PT_TIME_SHIFT] = " Time Shift %"PRIu64"\n",
3411 [INTEL_PT_TIME_MULT] = " Time Muliplier %"PRIu64"\n",
3412 [INTEL_PT_TIME_ZERO] = " Time Zero %"PRIu64"\n",
3413 [INTEL_PT_CAP_USER_TIME_ZERO] = " Cap Time Zero %"PRId64"\n",
3414 [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n",
3415 [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n",
3416 [INTEL_PT_HAVE_SCHED_SWITCH] = " Have sched_switch %"PRId64"\n",
3417 [INTEL_PT_SNAPSHOT_MODE] = " Snapshot mode %"PRId64"\n",
3418 [INTEL_PT_PER_CPU_MMAPS] = " Per-cpu maps %"PRId64"\n",
3419 [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n",
3420 [INTEL_PT_TSC_CTC_N] = " TSC:CTC numerator %"PRIu64"\n",
3421 [INTEL_PT_TSC_CTC_D] = " TSC:CTC denominator %"PRIu64"\n",
3422 [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n",
3423 [INTEL_PT_MAX_NONTURBO_RATIO] = " Max non-turbo ratio %"PRIu64"\n",
3424 [INTEL_PT_FILTER_STR_LEN] = " Filter string len. %"PRIu64"\n",
3427 static void intel_pt_print_info(__u64 *arr, int start, int finish)
3434 for (i = start; i <= finish; i++)
3435 fprintf(stdout, intel_pt_info_fmts[i], arr[i]);
3438 static void intel_pt_print_info_str(const char *name, const char *str)
3443 fprintf(stdout, " %-20s%s\n", name, str ? str : "");
3446 static bool intel_pt_has(struct perf_record_auxtrace_info *auxtrace_info, int pos)
3448 return auxtrace_info->header.size >=
3449 sizeof(struct perf_record_auxtrace_info) + (sizeof(u64) * (pos + 1));
3452 int intel_pt_process_auxtrace_info(union perf_event *event,
3453 struct perf_session *session)
3455 struct perf_record_auxtrace_info *auxtrace_info = &event->auxtrace_info;
3456 size_t min_sz = sizeof(u64) * INTEL_PT_PER_CPU_MMAPS;
3457 struct intel_pt *pt;
3462 if (auxtrace_info->header.size < sizeof(struct perf_record_auxtrace_info) +
3466 pt = zalloc(sizeof(struct intel_pt));
3470 addr_filters__init(&pt->filts);
3472 err = perf_config(intel_pt_perf_config, pt);
3476 err = auxtrace_queues__init(&pt->queues);
3480 intel_pt_log_set_name(INTEL_PT_PMU_NAME);
3482 pt->session = session;
3483 pt->machine = &session->machines.host; /* No kvm support */
3484 pt->auxtrace_type = auxtrace_info->type;
3485 pt->pmu_type = auxtrace_info->priv[INTEL_PT_PMU_TYPE];
3486 pt->tc.time_shift = auxtrace_info->priv[INTEL_PT_TIME_SHIFT];
3487 pt->tc.time_mult = auxtrace_info->priv[INTEL_PT_TIME_MULT];
3488 pt->tc.time_zero = auxtrace_info->priv[INTEL_PT_TIME_ZERO];
3489 pt->cap_user_time_zero = auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO];
3490 pt->tsc_bit = auxtrace_info->priv[INTEL_PT_TSC_BIT];
3491 pt->noretcomp_bit = auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT];
3492 pt->have_sched_switch = auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH];
3493 pt->snapshot_mode = auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE];
3494 pt->per_cpu_mmaps = auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS];
3495 intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_PMU_TYPE,
3496 INTEL_PT_PER_CPU_MMAPS);
3498 if (intel_pt_has(auxtrace_info, INTEL_PT_CYC_BIT)) {
3499 pt->mtc_bit = auxtrace_info->priv[INTEL_PT_MTC_BIT];
3500 pt->mtc_freq_bits = auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS];
3501 pt->tsc_ctc_ratio_n = auxtrace_info->priv[INTEL_PT_TSC_CTC_N];
3502 pt->tsc_ctc_ratio_d = auxtrace_info->priv[INTEL_PT_TSC_CTC_D];
3503 pt->cyc_bit = auxtrace_info->priv[INTEL_PT_CYC_BIT];
3504 intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_MTC_BIT,
3508 if (intel_pt_has(auxtrace_info, INTEL_PT_MAX_NONTURBO_RATIO)) {
3509 pt->max_non_turbo_ratio =
3510 auxtrace_info->priv[INTEL_PT_MAX_NONTURBO_RATIO];
3511 intel_pt_print_info(&auxtrace_info->priv[0],
3512 INTEL_PT_MAX_NONTURBO_RATIO,
3513 INTEL_PT_MAX_NONTURBO_RATIO);
3516 info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1;
3517 info_end = (void *)info + auxtrace_info->header.size;
3519 if (intel_pt_has(auxtrace_info, INTEL_PT_FILTER_STR_LEN)) {
3522 len = auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN];
3523 intel_pt_print_info(&auxtrace_info->priv[0],
3524 INTEL_PT_FILTER_STR_LEN,
3525 INTEL_PT_FILTER_STR_LEN);
3527 const char *filter = (const char *)info;
3529 len = roundup(len + 1, 8);
3531 if ((void *)info > info_end) {
3532 pr_err("%s: bad filter string length\n", __func__);
3534 goto err_free_queues;
3536 pt->filter = memdup(filter, len);
3539 goto err_free_queues;
3541 if (session->header.needs_swap)
3542 mem_bswap_64(pt->filter, len);
3543 if (pt->filter[len - 1]) {
3544 pr_err("%s: filter string not null terminated\n", __func__);
3546 goto err_free_queues;
3548 err = addr_filters__parse_bare_filter(&pt->filts,
3551 goto err_free_queues;
3553 intel_pt_print_info_str("Filter string", pt->filter);
3556 pt->timeless_decoding = intel_pt_timeless_decoding(pt);
3557 if (pt->timeless_decoding && !pt->tc.time_mult)
3558 pt->tc.time_mult = 1;
3559 pt->have_tsc = intel_pt_have_tsc(pt);
3560 pt->sampling_mode = intel_pt_sampling_mode(pt);
3561 pt->est_tsc = !pt->timeless_decoding;
3563 pt->unknown_thread = thread__new(999999999, 999999999);
3564 if (!pt->unknown_thread) {
3566 goto err_free_queues;
3570 * Since this thread will not be kept in any rbtree not in a
3571 * list, initialize its list node so that at thread__put() the
3572 * current thread lifetime assumption is kept and we don't segfault
3573 * at list_del_init().
3575 INIT_LIST_HEAD(&pt->unknown_thread->node);
3577 err = thread__set_comm(pt->unknown_thread, "unknown", 0);
3579 goto err_delete_thread;
3580 if (thread__init_maps(pt->unknown_thread, pt->machine)) {
3582 goto err_delete_thread;
3585 pt->auxtrace.process_event = intel_pt_process_event;
3586 pt->auxtrace.process_auxtrace_event = intel_pt_process_auxtrace_event;
3587 pt->auxtrace.queue_data = intel_pt_queue_data;
3588 pt->auxtrace.dump_auxtrace_sample = intel_pt_dump_sample;
3589 pt->auxtrace.flush_events = intel_pt_flush;
3590 pt->auxtrace.free_events = intel_pt_free_events;
3591 pt->auxtrace.free = intel_pt_free;
3592 pt->auxtrace.evsel_is_auxtrace = intel_pt_evsel_is_auxtrace;
3593 session->auxtrace = &pt->auxtrace;
3598 if (pt->have_sched_switch == 1) {
3599 pt->switch_evsel = intel_pt_find_sched_switch(session->evlist);
3600 if (!pt->switch_evsel) {
3601 pr_err("%s: missing sched_switch event\n", __func__);
3603 goto err_delete_thread;
3605 } else if (pt->have_sched_switch == 2 &&
3606 !intel_pt_find_switch(session->evlist)) {
3607 pr_err("%s: missing context_switch attribute flag\n", __func__);
3609 goto err_delete_thread;
3612 if (session->itrace_synth_opts->set) {
3613 pt->synth_opts = *session->itrace_synth_opts;
3615 itrace_synth_opts__set_default(&pt->synth_opts,
3616 session->itrace_synth_opts->default_no_sample);
3617 if (!session->itrace_synth_opts->default_no_sample &&
3618 !session->itrace_synth_opts->inject) {
3619 pt->synth_opts.branches = false;
3620 pt->synth_opts.callchain = true;
3621 pt->synth_opts.add_callchain = true;
3623 pt->synth_opts.thread_stack =
3624 session->itrace_synth_opts->thread_stack;
3627 if (pt->synth_opts.log)
3628 intel_pt_log_enable();
3630 /* Maximum non-turbo ratio is TSC freq / 100 MHz */
3631 if (pt->tc.time_mult) {
3632 u64 tsc_freq = intel_pt_ns_to_ticks(pt, 1000000000);
3634 if (!pt->max_non_turbo_ratio)
3635 pt->max_non_turbo_ratio =
3636 (tsc_freq + 50000000) / 100000000;
3637 intel_pt_log("TSC frequency %"PRIu64"\n", tsc_freq);
3638 intel_pt_log("Maximum non-turbo ratio %u\n",
3639 pt->max_non_turbo_ratio);
3640 pt->cbr2khz = tsc_freq / pt->max_non_turbo_ratio / 1000;
3643 err = intel_pt_setup_time_ranges(pt, session->itrace_synth_opts);
3645 goto err_delete_thread;
3647 if (pt->synth_opts.calls)
3648 pt->branches_filter |= PERF_IP_FLAG_CALL | PERF_IP_FLAG_ASYNC |
3649 PERF_IP_FLAG_TRACE_END;
3650 if (pt->synth_opts.returns)
3651 pt->branches_filter |= PERF_IP_FLAG_RETURN |
3652 PERF_IP_FLAG_TRACE_BEGIN;
3654 if ((pt->synth_opts.callchain || pt->synth_opts.add_callchain) &&
3655 !symbol_conf.use_callchain) {
3656 symbol_conf.use_callchain = true;
3657 if (callchain_register_param(&callchain_param) < 0) {
3658 symbol_conf.use_callchain = false;
3659 pt->synth_opts.callchain = false;
3660 pt->synth_opts.add_callchain = false;
3664 if (pt->synth_opts.add_callchain) {
3665 err = intel_pt_callchain_init(pt);
3667 goto err_delete_thread;
3670 if (pt->synth_opts.last_branch || pt->synth_opts.add_last_branch) {
3671 pt->br_stack_sz = pt->synth_opts.last_branch_sz;
3672 pt->br_stack_sz_plus = pt->br_stack_sz;
3675 if (pt->synth_opts.add_last_branch) {
3676 err = intel_pt_br_stack_init(pt);
3678 goto err_delete_thread;
3680 * Additional branch stack size to cater for tracing from the
3681 * actual sample ip to where the sample time is recorded.
3682 * Measured at about 200 branches, but generously set to 1024.
3683 * If kernel space is not being traced, then add just 1 for the
3684 * branch to kernel space.
3686 if (intel_pt_tracing_kernel(pt))
3687 pt->br_stack_sz_plus += 1024;
3689 pt->br_stack_sz_plus += 1;
3692 pt->use_thread_stack = pt->synth_opts.callchain ||
3693 pt->synth_opts.add_callchain ||
3694 pt->synth_opts.thread_stack ||
3695 pt->synth_opts.last_branch ||
3696 pt->synth_opts.add_last_branch;
3698 pt->callstack = pt->synth_opts.callchain ||
3699 pt->synth_opts.add_callchain ||
3700 pt->synth_opts.thread_stack;
3702 err = intel_pt_synth_events(pt, session);
3704 goto err_delete_thread;
3706 intel_pt_setup_pebs_events(pt);
3708 if (pt->sampling_mode || list_empty(&session->auxtrace_index))
3709 err = auxtrace_queue_data(session, true, true);
3711 err = auxtrace_queues__process_index(&pt->queues, session);
3713 goto err_delete_thread;
3715 if (pt->queues.populated)
3716 pt->data_queued = true;
3718 if (pt->timeless_decoding)
3719 pr_debug2("Intel PT decoding without timestamps\n");
3725 thread__zput(pt->unknown_thread);
3727 intel_pt_log_disable();
3728 auxtrace_queues__free(&pt->queues);
3729 session->auxtrace = NULL;
3731 addr_filters__exit(&pt->filts);
3733 zfree(&pt->time_ranges);