tools/perf/util/cs-etm.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright(C) 2015 Linaro Limited. All rights reserved.
   4  * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
   5  */
   6
   7 #ifndef INCLUDE__UTIL_PERF_CS_ETM_H__
   8 #define INCLUDE__UTIL_PERF_CS_ETM_H__
   9
  10 #include "util/event.h"
  11 #include "util/session.h"
  12 #include <linux/bits.h>
  13
  14 /* Versionning header in case things need tro change in the future.  That way
  15  * decoding of old snapshot is still possible.
  16  */
  17 enum {
  18         /* Starting with 0x0 */
  19         CS_HEADER_VERSION_0,
  20         /* PMU->type (32 bit), total # of CPUs (32 bit) */
  21         CS_PMU_TYPE_CPUS,
  22         CS_ETM_SNAPSHOT,
  23         CS_HEADER_VERSION_0_MAX,
  24 };
  25
  26 /* Beginning of header common to both ETMv3 and V4 */
  27 enum {
  28         CS_ETM_MAGIC,
  29         CS_ETM_CPU,
  30 };
  31
  32 /* ETMv3/PTM metadata */
  33 enum {
  34         /* Dynamic, configurable parameters */
  35         CS_ETM_ETMCR = CS_ETM_CPU + 1,
  36         CS_ETM_ETMTRACEIDR,
  37         /* RO, taken from sysFS */
  38         CS_ETM_ETMCCER,
  39         CS_ETM_ETMIDR,
  40         CS_ETM_PRIV_MAX,
  41 };
  42
  43 /* ETMv4 metadata */
  44 enum {
  45         /* Dynamic, configurable parameters */
  46         CS_ETMV4_TRCCONFIGR = CS_ETM_CPU + 1,
  47         CS_ETMV4_TRCTRACEIDR,
  48         /* RO, taken from sysFS */
  49         CS_ETMV4_TRCIDR0,
  50         CS_ETMV4_TRCIDR1,
  51         CS_ETMV4_TRCIDR2,
  52         CS_ETMV4_TRCIDR8,
  53         CS_ETMV4_TRCAUTHSTATUS,
  54         CS_ETMV4_PRIV_MAX,
  55 };
  56
  57 /*
  58  * ETMv3 exception encoding number:
  59  * See Embedded Trace Macrocell spcification (ARM IHI 0014Q)
  60  * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
  61  */
  62 enum {
  63         CS_ETMV3_EXC_NONE = 0,
  64         CS_ETMV3_EXC_DEBUG_HALT = 1,
  65         CS_ETMV3_EXC_SMC = 2,
  66         CS_ETMV3_EXC_HYP = 3,
  67         CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4,
  68         CS_ETMV3_EXC_JAZELLE_THUMBEE = 5,
  69         CS_ETMV3_EXC_PE_RESET = 8,
  70         CS_ETMV3_EXC_UNDEFINED_INSTR = 9,
  71         CS_ETMV3_EXC_SVC = 10,
  72         CS_ETMV3_EXC_PREFETCH_ABORT = 11,
  73         CS_ETMV3_EXC_DATA_FAULT = 12,
  74         CS_ETMV3_EXC_GENERIC = 13,
  75         CS_ETMV3_EXC_IRQ = 14,
  76         CS_ETMV3_EXC_FIQ = 15,
  77 };
  78
  79 /*
  80  * ETMv4 exception encoding number:
  81  * See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D)
  82  * table 6-12 Possible values for the TYPE field in an Exception instruction
  83  * trace packet, for ARMv7-A/R and ARMv8-A/R PEs.
  84  */
  85 enum {
  86         CS_ETMV4_EXC_RESET = 0,
  87         CS_ETMV4_EXC_DEBUG_HALT = 1,
  88         CS_ETMV4_EXC_CALL = 2,
  89         CS_ETMV4_EXC_TRAP = 3,
  90         CS_ETMV4_EXC_SYSTEM_ERROR = 4,
  91         CS_ETMV4_EXC_INST_DEBUG = 6,
  92         CS_ETMV4_EXC_DATA_DEBUG = 7,
  93         CS_ETMV4_EXC_ALIGNMENT = 10,
  94         CS_ETMV4_EXC_INST_FAULT = 11,
  95         CS_ETMV4_EXC_DATA_FAULT = 12,
  96         CS_ETMV4_EXC_IRQ = 14,
  97         CS_ETMV4_EXC_FIQ = 15,
  98         CS_ETMV4_EXC_END = 31,
  99 };
 100
 101 enum cs_etm_sample_type {
 102         CS_ETM_EMPTY,
 103         CS_ETM_RANGE,
 104         CS_ETM_DISCONTINUITY,
 105         CS_ETM_EXCEPTION,
 106         CS_ETM_EXCEPTION_RET,
 107 };
 108
 109 enum cs_etm_isa {
 110         CS_ETM_ISA_UNKNOWN,
 111         CS_ETM_ISA_A64,
 112         CS_ETM_ISA_A32,
 113         CS_ETM_ISA_T32,
 114 };
 115
 116 /* RB tree for quick conversion between traceID and metadata pointers */
 117 struct intlist *traceid_list;
 118
 119 struct cs_etm_queue;
 120
 121 struct cs_etm_packet {
 122         enum cs_etm_sample_type sample_type;
 123         enum cs_etm_isa isa;
 124         u64 start_addr;
 125         u64 end_addr;
 126         u32 instr_count;
 127         u32 last_instr_type;
 128         u32 last_instr_subtype;
 129         u32 flags;
 130         u32 exception_number;
 131         u8 last_instr_cond;
 132         u8 last_instr_taken_branch;
 133         u8 last_instr_size;
 134         u8 trace_chan_id;
 135         int cpu;
 136 };
 137
 138 #define CS_ETM_PACKET_MAX_BUFFER 1024
 139
 140 /*
 141  * When working with per-thread scenarios the process under trace can
 142  * be scheduled on any CPU and as such, more than one traceID may be
 143  * associated with the same process.  Since a traceID of '0' is illegal
 144  * as per the CoreSight architecture, use that specific value to
 145  * identify the queue where all packets (with any traceID) are
 146  * aggregated.
 147  */
 148 #define CS_ETM_PER_THREAD_TRACEID 0
 149
 150 struct cs_etm_packet_queue {
 151         u32 packet_count;
 152         u32 head;
 153         u32 tail;
 154         u32 instr_count;
 155         u64 timestamp;
 156         u64 next_timestamp;
 157         struct cs_etm_packet packet_buffer[CS_ETM_PACKET_MAX_BUFFER];
 158 };
 159
 160 #define KiB(x) ((x) * 1024)
 161 #define MiB(x) ((x) * 1024 * 1024)
 162
 163 #define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL
 164
 165 #define BMVAL(val, lsb, msb)    ((val & GENMASK(msb, lsb)) >> lsb)
 166
 167 #define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_0_MAX * sizeof(u64))
 168
 169 #define __perf_cs_etmv3_magic 0x3030303030303030ULL
 170 #define __perf_cs_etmv4_magic 0x4040404040404040ULL
 171 #define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64))
 172 #define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64))
 173
 174 #ifdef HAVE_CSTRACE_SUPPORT
 175 int cs_etm__process_auxtrace_info(union perf_event *event,
 176                                   struct perf_session *session);
 177 int cs_etm__get_cpu(u8 trace_chan_id, int *cpu);
 178 int cs_etm__etmq_set_tid(struct cs_etm_queue *etmq,
 179                          pid_t tid, u8 trace_chan_id);
 180 bool cs_etm__etmq_is_timeless(struct cs_etm_queue *etmq);
 181 void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq,
 182                                               u8 trace_chan_id);
 183 struct cs_etm_packet_queue
 184 *cs_etm__etmq_get_packet_queue(struct cs_etm_queue *etmq, u8 trace_chan_id);
 185 #else
 186 static inline int
 187 cs_etm__process_auxtrace_info(union perf_event *event __maybe_unused,
 188                               struct perf_session *session __maybe_unused)
 189 {
 190         return -1;
 191 }
 192
 193 static inline int cs_etm__get_cpu(u8 trace_chan_id __maybe_unused,
 194                                   int *cpu __maybe_unused)
 195 {
 196         return -1;
 197 }
 198
 199 static inline int cs_etm__etmq_set_tid(
 200                                 struct cs_etm_queue *etmq __maybe_unused,
 201                                 pid_t tid __maybe_unused,
 202                                 u8 trace_chan_id __maybe_unused)
 203 {
 204         return -1;
 205 }
 206
 207 static inline bool cs_etm__etmq_is_timeless(
 208                                 struct cs_etm_queue *etmq __maybe_unused)
 209 {
 210         /* What else to return? */
 211         return true;
 212 }
 213
 214 static inline void cs_etm__etmq_set_traceid_queue_timestamp(
 215                                 struct cs_etm_queue *etmq __maybe_unused,
 216                                 u8 trace_chan_id __maybe_unused) {}
 217
 218 static inline struct cs_etm_packet_queue *cs_etm__etmq_get_packet_queue(
 219                                 struct cs_etm_queue *etmq __maybe_unused,
 220                                 u8 trace_chan_id __maybe_unused)
 221 {
 222         return NULL;
 223 }
 224 #endif
 225
 226 #endif