tools/perf/pmu-events/arch/x86/broadwellx/memory.json

   1 [
   2     {
   3         "BriefDescription": "Number of times HLE abort was triggered",
   4         "Counter": "0,1,2,3",
   5         "CounterHTOff": "0,1,2,3,4,5,6,7",
   6         "EventCode": "0xc8",
   7         "EventName": "HLE_RETIRED.ABORTED",
   8         "PEBS": "1",
   9         "PublicDescription": "Number of times HLE abort was triggered.",
  10         "SampleAfterValue": "2000003",
  11         "UMask": "0x4"
  12     },
  13     {
  14         "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
  15         "Counter": "0,1,2,3",
  16         "CounterHTOff": "0,1,2,3,4,5,6,7",
  17         "EventCode": "0xc8",
  18         "EventName": "HLE_RETIRED.ABORTED_MISC1",
  19         "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
  20         "SampleAfterValue": "2000003",
  21         "UMask": "0x8"
  22     },
  23     {
  24         "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
  25         "Counter": "0,1,2,3",
  26         "CounterHTOff": "0,1,2,3,4,5,6,7",
  27         "EventCode": "0xc8",
  28         "EventName": "HLE_RETIRED.ABORTED_MISC2",
  29         "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
  30         "SampleAfterValue": "2000003",
  31         "UMask": "0x10"
  32     },
  33     {
  34         "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
  35         "Counter": "0,1,2,3",
  36         "CounterHTOff": "0,1,2,3,4,5,6,7",
  37         "EventCode": "0xc8",
  38         "EventName": "HLE_RETIRED.ABORTED_MISC3",
  39         "PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
  40         "SampleAfterValue": "2000003",
  41         "UMask": "0x20"
  42     },
  43     {
  44         "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
  45         "Counter": "0,1,2,3",
  46         "CounterHTOff": "0,1,2,3,4,5,6,7",
  47         "EventCode": "0xc8",
  48         "EventName": "HLE_RETIRED.ABORTED_MISC4",
  49         "PublicDescription": "Number of times HLE caused a fault.",
  50         "SampleAfterValue": "2000003",
  51         "UMask": "0x40"
  52     },
  53     {
  54         "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
  55         "Counter": "0,1,2,3",
  56         "CounterHTOff": "0,1,2,3,4,5,6,7",
  57         "EventCode": "0xc8",
  58         "EventName": "HLE_RETIRED.ABORTED_MISC5",
  59         "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
  60         "SampleAfterValue": "2000003",
  61         "UMask": "0x80"
  62     },
  63     {
  64         "BriefDescription": "Number of times HLE commit succeeded",
  65         "Counter": "0,1,2,3",
  66         "CounterHTOff": "0,1,2,3,4,5,6,7",
  67         "EventCode": "0xc8",
  68         "EventName": "HLE_RETIRED.COMMIT",
  69         "PublicDescription": "Number of times HLE commit succeeded.",
  70         "SampleAfterValue": "2000003",
  71         "UMask": "0x2"
  72     },
  73     {
  74         "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
  75         "Counter": "0,1,2,3",
  76         "CounterHTOff": "0,1,2,3,4,5,6,7",
  77         "EventCode": "0xc8",
  78         "EventName": "HLE_RETIRED.START",
  79         "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
  80         "SampleAfterValue": "2000003",
  81         "UMask": "0x1"
  82     },
  83     {
  84         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
  85         "Counter": "0,1,2,3",
  86         "CounterHTOff": "0,1,2,3,4,5,6,7",
  87         "EventCode": "0xC3",
  88         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
  89         "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
  90         "SampleAfterValue": "100003",
  91         "UMask": "0x2"
  92     },
  93     {
  94         "BriefDescription": "Randomly selected loads with latency value being above 128",
  95         "Counter": "3",
  96         "CounterHTOff": "3",
  97         "Data_LA": "1",
  98         "Errata": "BDM100, BDM35",
  99         "EventCode": "0xcd",
 100         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
 101         "MSRIndex": "0x3F6",
 102         "MSRValue": "0x80",
 103         "PEBS": "2",
 104         "PublicDescription": "Counts randomly selected loads with latency value being above 128.",
 105         "SampleAfterValue": "1009",
 106         "TakenAlone": "1",
 107         "UMask": "0x1"
 108     },
 109     {
 110         "BriefDescription": "Randomly selected loads with latency value being above 16",
 111         "Counter": "3",
 112         "CounterHTOff": "3",
 113         "Data_LA": "1",
 114         "Errata": "BDM100, BDM35",
 115         "EventCode": "0xcd",
 116         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
 117         "MSRIndex": "0x3F6",
 118         "MSRValue": "0x10",
 119         "PEBS": "2",
 120         "PublicDescription": "Counts randomly selected loads with latency value being above 16.",
 121         "SampleAfterValue": "20011",
 122         "TakenAlone": "1",
 123         "UMask": "0x1"
 124     },
 125     {
 126         "BriefDescription": "Randomly selected loads with latency value being above 256",
 127         "Counter": "3",
 128         "CounterHTOff": "3",
 129         "Data_LA": "1",
 130         "Errata": "BDM100, BDM35",
 131         "EventCode": "0xcd",
 132         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
 133         "MSRIndex": "0x3F6",
 134         "MSRValue": "0x100",
 135         "PEBS": "2",
 136         "PublicDescription": "Counts randomly selected loads with latency value being above 256.",
 137         "SampleAfterValue": "503",
 138         "TakenAlone": "1",
 139         "UMask": "0x1"
 140     },
 141     {
 142         "BriefDescription": "Randomly selected loads with latency value being above 32",
 143         "Counter": "3",
 144         "CounterHTOff": "3",
 145         "Data_LA": "1",
 146         "Errata": "BDM100, BDM35",
 147         "EventCode": "0xcd",
 148         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
 149         "MSRIndex": "0x3F6",
 150         "MSRValue": "0x20",
 151         "PEBS": "2",
 152         "PublicDescription": "Counts randomly selected loads with latency value being above 32.",
 153         "SampleAfterValue": "100007",
 154         "TakenAlone": "1",
 155         "UMask": "0x1"
 156     },
 157     {
 158         "BriefDescription": "Randomly selected loads with latency value being above 4",
 159         "Counter": "3",
 160         "CounterHTOff": "3",
 161         "Data_LA": "1",
 162         "Errata": "BDM100, BDM35",
 163         "EventCode": "0xcd",
 164         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
 165         "MSRIndex": "0x3F6",
 166         "MSRValue": "0x4",
 167         "PEBS": "2",
 168         "PublicDescription": "Counts randomly selected loads with latency value being above four.",
 169         "SampleAfterValue": "100003",
 170         "TakenAlone": "1",
 171         "UMask": "0x1"
 172     },
 173     {
 174         "BriefDescription": "Randomly selected loads with latency value being above 512",
 175         "Counter": "3",
 176         "CounterHTOff": "3",
 177         "Data_LA": "1",
 178         "Errata": "BDM100, BDM35",
 179         "EventCode": "0xcd",
 180         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
 181         "MSRIndex": "0x3F6",
 182         "MSRValue": "0x200",
 183         "PEBS": "2",
 184         "PublicDescription": "Counts randomly selected loads with latency value being above 512.",
 185         "SampleAfterValue": "101",
 186         "TakenAlone": "1",
 187         "UMask": "0x1"
 188     },
 189     {
 190         "BriefDescription": "Randomly selected loads with latency value being above 64",
 191         "Counter": "3",
 192         "CounterHTOff": "3",
 193         "Data_LA": "1",
 194         "Errata": "BDM100, BDM35",
 195         "EventCode": "0xcd",
 196         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
 197         "MSRIndex": "0x3F6",
 198         "MSRValue": "0x40",
 199         "PEBS": "2",
 200         "PublicDescription": "Counts randomly selected loads with latency value being above 64.",
 201         "SampleAfterValue": "2003",
 202         "TakenAlone": "1",
 203         "UMask": "0x1"
 204     },
 205     {
 206         "BriefDescription": "Randomly selected loads with latency value being above 8",
 207         "Counter": "3",
 208         "CounterHTOff": "3",
 209         "Data_LA": "1",
 210         "Errata": "BDM100, BDM35",
 211         "EventCode": "0xcd",
 212         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
 213         "MSRIndex": "0x3F6",
 214         "MSRValue": "0x8",
 215         "PEBS": "2",
 216         "PublicDescription": "Counts randomly selected loads with latency value being above eight.",
 217         "SampleAfterValue": "50021",
 218         "TakenAlone": "1",
 219         "UMask": "0x1"
 220     },
 221     {
 222         "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
 223         "Counter": "0,1,2,3",
 224         "CounterHTOff": "0,1,2,3,4,5,6,7",
 225         "EventCode": "0x05",
 226         "EventName": "MISALIGN_MEM_REF.LOADS",
 227         "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
 228         "SampleAfterValue": "2000003",
 229         "UMask": "0x1"
 230     },
 231     {
 232         "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
 233         "Counter": "0,1,2,3",
 234         "CounterHTOff": "0,1,2,3,4,5,6,7",
 235         "EventCode": "0x05",
 236         "EventName": "MISALIGN_MEM_REF.STORES",
 237         "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
 238         "SampleAfterValue": "2000003",
 239         "UMask": "0x2"
 240     },
 241     {
 242         "BriefDescription": "Counts all demand & prefetch code reads miss in the L3",
 243         "Counter": "0,1,2,3",
 244         "CounterHTOff": "0,1,2,3",
 245         "EventCode": "0xB7, 0xBB",
 246         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
 247         "MSRIndex": "0x1a6,0x1a7",
 248         "MSRValue": "0x3FBFC00244",
 249         "Offcore": "1",
 250         "SampleAfterValue": "100003",
 251         "UMask": "0x1"
 252     },
 253     {
 254         "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
 255         "Counter": "0,1,2,3",
 256         "CounterHTOff": "0,1,2,3",
 257         "EventCode": "0xB7, 0xBB",
 258         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
 259         "MSRIndex": "0x1a6,0x1a7",
 260         "MSRValue": "0x604000244",
 261         "Offcore": "1",
 262         "SampleAfterValue": "100003",
 263         "UMask": "0x1"
 264     },
 265     {
 266         "BriefDescription": "Counts all demand & prefetch data reads miss in the L3",
 267         "Counter": "0,1,2,3",
 268         "CounterHTOff": "0,1,2,3",
 269         "EventCode": "0xB7, 0xBB",
 270         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
 271         "MSRIndex": "0x1a6,0x1a7",
 272         "MSRValue": "0x3FBFC00091",
 273         "Offcore": "1",
 274         "SampleAfterValue": "100003",
 275         "UMask": "0x1"
 276     },
 277     {
 278         "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
 279         "Counter": "0,1,2,3",
 280         "CounterHTOff": "0,1,2,3",
 281         "EventCode": "0xB7, 0xBB",
 282         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
 283         "MSRIndex": "0x1a6,0x1a7",
 284         "MSRValue": "0x604000091",
 285         "Offcore": "1",
 286         "SampleAfterValue": "100003",
 287         "UMask": "0x1"
 288     },
 289     {
 290         "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
 291         "Counter": "0,1,2,3",
 292         "CounterHTOff": "0,1,2,3",
 293         "EventCode": "0xB7, 0xBB",
 294         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
 295         "MSRIndex": "0x1a6,0x1a7",
 296         "MSRValue": "0x63BC00091",
 297         "Offcore": "1",
 298         "SampleAfterValue": "100003",
 299         "UMask": "0x1"
 300     },
 301     {
 302         "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
 303         "Counter": "0,1,2,3",
 304         "CounterHTOff": "0,1,2,3",
 305         "EventCode": "0xB7, 0xBB",
 306         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
 307         "MSRIndex": "0x1a6,0x1a7",
 308         "MSRValue": "0x103FC00091",
 309         "Offcore": "1",
 310         "SampleAfterValue": "100003",
 311         "UMask": "0x1"
 312     },
 313     {
 314         "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
 315         "Counter": "0,1,2,3",
 316         "CounterHTOff": "0,1,2,3",
 317         "EventCode": "0xB7, 0xBB",
 318         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
 319         "MSRIndex": "0x1a6,0x1a7",
 320         "MSRValue": "0x87FC00091",
 321         "Offcore": "1",
 322         "SampleAfterValue": "100003",
 323         "UMask": "0x1"
 324     },
 325     {
 326         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
 327         "Counter": "0,1,2,3",
 328         "CounterHTOff": "0,1,2,3",
 329         "EventCode": "0xB7, 0xBB",
 330         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
 331         "MSRIndex": "0x1a6,0x1a7",
 332         "MSRValue": "0x3FBFC007F7",
 333         "Offcore": "1",
 334         "SampleAfterValue": "100003",
 335         "UMask": "0x1"
 336     },
 337     {
 338         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
 339         "Counter": "0,1,2,3",
 340         "CounterHTOff": "0,1,2,3",
 341         "EventCode": "0xB7, 0xBB",
 342         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
 343         "MSRIndex": "0x1a6,0x1a7",
 344         "MSRValue": "0x6040007F7",
 345         "Offcore": "1",
 346         "SampleAfterValue": "100003",
 347         "UMask": "0x1"
 348     },
 349     {
 350         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
 351         "Counter": "0,1,2,3",
 352         "CounterHTOff": "0,1,2,3",
 353         "EventCode": "0xB7, 0xBB",
 354         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
 355         "MSRIndex": "0x1a6,0x1a7",
 356         "MSRValue": "0x63BC007F7",
 357         "Offcore": "1",
 358         "SampleAfterValue": "100003",
 359         "UMask": "0x1"
 360     },
 361     {
 362         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
 363         "Counter": "0,1,2,3",
 364         "CounterHTOff": "0,1,2,3",
 365         "EventCode": "0xB7, 0xBB",
 366         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
 367         "MSRIndex": "0x1a6,0x1a7",
 368         "MSRValue": "0x103FC007F7",
 369         "Offcore": "1",
 370         "SampleAfterValue": "100003",
 371         "UMask": "0x1"
 372     },
 373     {
 374         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
 375         "Counter": "0,1,2,3",
 376         "CounterHTOff": "0,1,2,3",
 377         "EventCode": "0xB7, 0xBB",
 378         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
 379         "MSRIndex": "0x1a6,0x1a7",
 380         "MSRValue": "0x87FC007F7",
 381         "Offcore": "1",
 382         "SampleAfterValue": "100003",
 383         "UMask": "0x1"
 384     },
 385     {
 386         "BriefDescription": "Counts all requests miss in the L3",
 387         "Counter": "0,1,2,3",
 388         "CounterHTOff": "0,1,2,3",
 389         "EventCode": "0xB7, 0xBB",
 390         "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
 391         "MSRIndex": "0x1a6,0x1a7",
 392         "MSRValue": "0x3FBFC08FFF",
 393         "Offcore": "1",
 394         "SampleAfterValue": "100003",
 395         "UMask": "0x1"
 396     },
 397     {
 398         "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3",
 399         "Counter": "0,1,2,3",
 400         "CounterHTOff": "0,1,2,3",
 401         "EventCode": "0xB7, 0xBB",
 402         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
 403         "MSRIndex": "0x1a6,0x1a7",
 404         "MSRValue": "0x3FBFC00122",
 405         "Offcore": "1",
 406         "SampleAfterValue": "100003",
 407         "UMask": "0x1"
 408     },
 409     {
 410         "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
 411         "Counter": "0,1,2,3",
 412         "CounterHTOff": "0,1,2,3",
 413         "EventCode": "0xB7, 0xBB",
 414         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
 415         "MSRIndex": "0x1a6,0x1a7",
 416         "MSRValue": "0x604000122",
 417         "Offcore": "1",
 418         "SampleAfterValue": "100003",
 419         "UMask": "0x1"
 420     },
 421     {
 422         "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3",
 423         "Counter": "0,1,2,3",
 424         "CounterHTOff": "0,1,2,3",
 425         "EventCode": "0xB7, 0xBB",
 426         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",
 427         "MSRIndex": "0x1a6,0x1a7",
 428         "MSRValue": "0x3FBFC00002",
 429         "Offcore": "1",
 430         "SampleAfterValue": "100003",
 431         "UMask": "0x1"
 432     },
 433     {
 434         "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
 435         "Counter": "0,1,2,3",
 436         "CounterHTOff": "0,1,2,3",
 437         "EventCode": "0xB7, 0xBB",
 438         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
 439         "MSRIndex": "0x1a6,0x1a7",
 440         "MSRValue": "0x103FC00002",
 441         "Offcore": "1",
 442         "SampleAfterValue": "100003",
 443         "UMask": "0x1"
 444     },
 445     {
 446         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
 447         "Counter": "0,1,2,3",
 448         "CounterHTOff": "0,1,2,3",
 449         "EventCode": "0xB7, 0xBB",
 450         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
 451         "MSRIndex": "0x1a6,0x1a7",
 452         "MSRValue": "0x3FBFC00200",
 453         "Offcore": "1",
 454         "SampleAfterValue": "100003",
 455         "UMask": "0x1"
 456     },
 457     {
 458         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
 459         "Counter": "0,1,2,3",
 460         "CounterHTOff": "0,1,2,3",
 461         "EventCode": "0xB7, 0xBB",
 462         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
 463         "MSRIndex": "0x1a6,0x1a7",
 464         "MSRValue": "0x3FBFC00100",
 465         "Offcore": "1",
 466         "SampleAfterValue": "100003",
 467         "UMask": "0x1"
 468     },
 469     {
 470         "BriefDescription": "Number of times RTM abort was triggered",
 471         "Counter": "0,1,2,3",
 472         "CounterHTOff": "0,1,2,3",
 473         "EventCode": "0xc9",
 474         "EventName": "RTM_RETIRED.ABORTED",
 475         "PEBS": "1",
 476         "PublicDescription": "Number of times RTM abort was triggered .",
 477         "SampleAfterValue": "2000003",
 478         "UMask": "0x4"
 479     },
 480     {
 481         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
 482         "Counter": "0,1,2,3",
 483         "CounterHTOff": "0,1,2,3",
 484         "EventCode": "0xc9",
 485         "EventName": "RTM_RETIRED.ABORTED_MISC1",
 486         "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
 487         "SampleAfterValue": "2000003",
 488         "UMask": "0x8"
 489     },
 490     {
 491         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
 492         "Counter": "0,1,2,3",
 493         "CounterHTOff": "0,1,2,3",
 494         "EventCode": "0xc9",
 495         "EventName": "RTM_RETIRED.ABORTED_MISC2",
 496         "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
 497         "SampleAfterValue": "2000003",
 498         "UMask": "0x10"
 499     },
 500     {
 501         "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
 502         "Counter": "0,1,2,3",
 503         "CounterHTOff": "0,1,2,3",
 504         "EventCode": "0xc9",
 505         "EventName": "RTM_RETIRED.ABORTED_MISC3",
 506         "PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
 507         "SampleAfterValue": "2000003",
 508         "UMask": "0x20"
 509     },
 510     {
 511         "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
 512         "Counter": "0,1,2,3",
 513         "CounterHTOff": "0,1,2,3",
 514         "EventCode": "0xc9",
 515         "EventName": "RTM_RETIRED.ABORTED_MISC4",
 516         "PublicDescription": "Number of times a RTM caused a fault.",
 517         "SampleAfterValue": "2000003",
 518         "UMask": "0x40"
 519     },
 520     {
 521         "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
 522         "Counter": "0,1,2,3",
 523         "CounterHTOff": "0,1,2,3",
 524         "EventCode": "0xc9",
 525         "EventName": "RTM_RETIRED.ABORTED_MISC5",
 526         "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
 527         "SampleAfterValue": "2000003",
 528         "UMask": "0x80"
 529     },
 530     {
 531         "BriefDescription": "Number of times RTM commit succeeded",
 532         "Counter": "0,1,2,3",
 533         "CounterHTOff": "0,1,2,3",
 534         "EventCode": "0xc9",
 535         "EventName": "RTM_RETIRED.COMMIT",
 536         "PublicDescription": "Number of times RTM commit succeeded.",
 537         "SampleAfterValue": "2000003",
 538         "UMask": "0x2"
 539     },
 540     {
 541         "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
 542         "Counter": "0,1,2,3",
 543         "CounterHTOff": "0,1,2,3",
 544         "EventCode": "0xc9",
 545         "EventName": "RTM_RETIRED.START",
 546         "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
 547         "SampleAfterValue": "2000003",
 548         "UMask": "0x1"
 549     },
 550     {
 551         "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
 552         "Counter": "0,1,2,3",
 553         "CounterHTOff": "0,1,2,3,4,5,6,7",
 554         "EventCode": "0x5d",
 555         "EventName": "TX_EXEC.MISC1",
 556         "SampleAfterValue": "2000003",
 557         "UMask": "0x1"
 558     },
 559     {
 560         "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
 561         "Counter": "0,1,2,3",
 562         "CounterHTOff": "0,1,2,3,4,5,6,7",
 563         "EventCode": "0x5d",
 564         "EventName": "TX_EXEC.MISC2",
 565         "PublicDescription": "Unfriendly TSX abort triggered by  a vzeroupper instruction.",
 566         "SampleAfterValue": "2000003",
 567         "UMask": "0x2"
 568     },
 569     {
 570         "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
 571         "Counter": "0,1,2,3",
 572         "CounterHTOff": "0,1,2,3,4,5,6,7",
 573         "EventCode": "0x5d",
 574         "EventName": "TX_EXEC.MISC3",
 575         "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
 576         "SampleAfterValue": "2000003",
 577         "UMask": "0x4"
 578     },
 579     {
 580         "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
 581         "Counter": "0,1,2,3",
 582         "CounterHTOff": "0,1,2,3,4,5,6,7",
 583         "EventCode": "0x5d",
 584         "EventName": "TX_EXEC.MISC4",
 585         "PublicDescription": "RTM region detected inside HLE.",
 586         "SampleAfterValue": "2000003",
 587         "UMask": "0x8"
 588     },
 589     {
 590         "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
 591         "Counter": "0,1,2,3",
 592         "CounterHTOff": "0,1,2,3,4,5,6,7",
 593         "EventCode": "0x5d",
 594         "EventName": "TX_EXEC.MISC5",
 595         "SampleAfterValue": "2000003",
 596         "UMask": "0x10"
 597     },
 598     {
 599         "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
 600         "Counter": "0,1,2,3",
 601         "CounterHTOff": "0,1,2,3,4,5,6,7",
 602         "EventCode": "0x54",
 603         "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
 604         "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
 605         "SampleAfterValue": "2000003",
 606         "UMask": "0x2"
 607     },
 608     {
 609         "BriefDescription": "Number of times a TSX line had a cache conflict",
 610         "Counter": "0,1,2,3",
 611         "CounterHTOff": "0,1,2,3,4,5,6,7",
 612         "EventCode": "0x54",
 613         "EventName": "TX_MEM.ABORT_CONFLICT",
 614         "PublicDescription": "Number of times a TSX line had a cache conflict.",
 615         "SampleAfterValue": "2000003",
 616         "UMask": "0x1"
 617     },
 618     {
 619         "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
 620         "Counter": "0,1,2,3",
 621         "CounterHTOff": "0,1,2,3,4,5,6,7",
 622         "EventCode": "0x54",
 623         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
 624         "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
 625         "SampleAfterValue": "2000003",
 626         "UMask": "0x10"
 627     },
 628     {
 629         "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
 630         "Counter": "0,1,2,3",
 631         "CounterHTOff": "0,1,2,3,4,5,6,7",
 632         "EventCode": "0x54",
 633         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
 634         "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
 635         "SampleAfterValue": "2000003",
 636         "UMask": "0x8"
 637     },
 638     {
 639         "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
 640         "Counter": "0,1,2,3",
 641         "CounterHTOff": "0,1,2,3,4,5,6,7",
 642         "EventCode": "0x54",
 643         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
 644         "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
 645         "SampleAfterValue": "2000003",
 646         "UMask": "0x20"
 647     },
 648     {
 649         "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
 650         "Counter": "0,1,2,3",
 651         "CounterHTOff": "0,1,2,3,4,5,6,7",
 652         "EventCode": "0x54",
 653         "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
 654         "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
 655         "SampleAfterValue": "2000003",
 656         "UMask": "0x4"
 657     },
 658     {
 659         "BriefDescription": "Number of times we could not allocate Lock Buffer",
 660         "Counter": "0,1,2,3",
 661         "CounterHTOff": "0,1,2,3,4,5,6,7",
 662         "EventCode": "0x54",
 663         "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
 664         "PublicDescription": "Number of times we could not allocate Lock Buffer.",
 665         "SampleAfterValue": "2000003",
 666         "UMask": "0x40"
 667     }
 668 ]