tools/perf/pmu-events/arch/x86/alderlake/floating-point.json

   1 [
   2     {
   3         "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
   4         "CollectPEBSRecord": "2",
   5         "Counter": "0,1,2,3,4,5",
   6         "EventCode": "0xc3",
   7         "EventName": "MACHINE_CLEARS.FP_ASSIST",
   8         "PEBScounters": "0,1,2,3,4,5",
   9         "SampleAfterValue": "20003",
  10         "UMask": "0x4",
  11         "Unit": "cpu_atom"
  12     },
  13     {
  14         "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",
  15         "CollectPEBSRecord": "2",
  16         "Counter": "0,1,2,3,4,5",
  17         "EventCode": "0xc2",
  18         "EventName": "UOPS_RETIRED.FPDIV",
  19         "PEBS": "1",
  20         "PEBScounters": "0,1,2,3,4,5",
  21         "SampleAfterValue": "2000003",
  22         "UMask": "0x8",
  23         "Unit": "cpu_atom"
  24     },
  25     {
  26         "BriefDescription": "TBD",
  27         "CollectPEBSRecord": "2",
  28         "Counter": "0,1,2,3,4,5,6,7",
  29         "CounterMask": "1",
  30         "EventCode": "0xb0",
  31         "EventName": "ARITH.FPDIV_ACTIVE",
  32         "PEBScounters": "0,1,2,3,4,5,6,7",
  33         "SampleAfterValue": "1000003",
  34         "UMask": "0x1",
  35         "Unit": "cpu_core"
  36     },
  37     {
  38         "BriefDescription": "Counts all microcode FP assists.",
  39         "CollectPEBSRecord": "2",
  40         "Counter": "0,1,2,3,4,5,6,7",
  41         "EventCode": "0xc1",
  42         "EventName": "ASSISTS.FP",
  43         "PEBScounters": "0,1,2,3,4,5,6,7",
  44         "SampleAfterValue": "100003",
  45         "UMask": "0x2",
  46         "Unit": "cpu_core"
  47     },
  48     {
  49         "BriefDescription": "TBD",
  50         "CollectPEBSRecord": "2",
  51         "Counter": "0,1,2,3,4,5,6,7",
  52         "EventCode": "0xc1",
  53         "EventName": "ASSISTS.SSE_AVX_MIX",
  54         "PEBScounters": "0,1,2,3,4,5,6,7",
  55         "SampleAfterValue": "1000003",
  56         "UMask": "0x10",
  57         "Unit": "cpu_core"
  58     },
  59     {
  60         "BriefDescription": "TBD",
  61         "CollectPEBSRecord": "2",
  62         "Counter": "0,1,2,3,4,5,6,7",
  63         "EventCode": "0xb3",
  64         "EventName": "FP_ARITH_DISPATCHED.PORT_0",
  65         "PEBScounters": "0,1,2,3,4,5,6,7",
  66         "SampleAfterValue": "2000003",
  67         "UMask": "0x1",
  68         "Unit": "cpu_core"
  69     },
  70     {
  71         "BriefDescription": "TBD",
  72         "CollectPEBSRecord": "2",
  73         "Counter": "0,1,2,3,4,5,6,7",
  74         "EventCode": "0xb3",
  75         "EventName": "FP_ARITH_DISPATCHED.PORT_1",
  76         "PEBScounters": "0,1,2,3,4,5,6,7",
  77         "SampleAfterValue": "2000003",
  78         "UMask": "0x2",
  79         "Unit": "cpu_core"
  80     },
  81     {
  82         "BriefDescription": "TBD",
  83         "CollectPEBSRecord": "2",
  84         "Counter": "0,1,2,3,4,5,6,7",
  85         "EventCode": "0xb3",
  86         "EventName": "FP_ARITH_DISPATCHED.PORT_5",
  87         "PEBScounters": "0,1,2,3,4,5,6,7",
  88         "SampleAfterValue": "2000003",
  89         "UMask": "0x4",
  90         "Unit": "cpu_core"
  91     },
  92     {
  93         "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
  94         "CollectPEBSRecord": "2",
  95         "Counter": "0,1,2,3,4,5,6,7",
  96         "EventCode": "0xc7",
  97         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
  98         "PEBScounters": "0,1,2,3,4,5,6,7",
  99         "SampleAfterValue": "100003",
 100         "UMask": "0x4",
 101         "Unit": "cpu_core"
 102     },
 103     {
 104         "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
 105         "CollectPEBSRecord": "2",
 106         "Counter": "0,1,2,3,4,5,6,7",
 107         "EventCode": "0xc7",
 108         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
 109         "PEBScounters": "0,1,2,3,4,5,6,7",
 110         "SampleAfterValue": "100003",
 111         "UMask": "0x8",
 112         "Unit": "cpu_core"
 113     },
 114     {
 115         "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
 116         "CollectPEBSRecord": "2",
 117         "Counter": "0,1,2,3,4,5,6,7",
 118         "EventCode": "0xc7",
 119         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
 120         "PEBScounters": "0,1,2,3,4,5,6,7",
 121         "SampleAfterValue": "100003",
 122         "UMask": "0x10",
 123         "Unit": "cpu_core"
 124     },
 125     {
 126         "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
 127         "CollectPEBSRecord": "2",
 128         "Counter": "0,1,2,3,4,5,6,7",
 129         "EventCode": "0xc7",
 130         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
 131         "PEBScounters": "0,1,2,3,4,5,6,7",
 132         "SampleAfterValue": "100003",
 133         "UMask": "0x20",
 134         "Unit": "cpu_core"
 135     },
 136     {
 137         "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
 138         "CollectPEBSRecord": "2",
 139         "Counter": "0,1,2,3,4,5,6,7",
 140         "EventCode": "0xc7",
 141         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
 142         "PEBScounters": "0,1,2,3,4,5,6,7",
 143         "SampleAfterValue": "100003",
 144         "UMask": "0x1",
 145         "Unit": "cpu_core"
 146     },
 147     {
 148         "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
 149         "CollectPEBSRecord": "2",
 150         "Counter": "0,1,2,3,4,5,6,7",
 151         "EventCode": "0xc7",
 152         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
 153         "PEBScounters": "0,1,2,3,4,5,6,7",
 154         "SampleAfterValue": "100003",
 155         "UMask": "0x2",
 156         "Unit": "cpu_core"
 157     }
 158 ]