6 perf-list - List all symbolic event types
11 'perf list' [--no-desc] [--long-desc]
12 [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob]
16 This command displays the symbolic event types which can be selected in the
17 various perf commands with the -e option.
23 Print extra event descriptions. (default)
26 Don't print descriptions.
30 Print longer event descriptions.
33 Enable debugging output.
36 Print how named events are resolved internally into perf events, and also
37 any extra expressions computed by perf stat.
43 Events can optionally have a modifier by appending a colon and one or
44 more modifiers. Modifiers allow the user to restrict the events to be
45 counted. The following modifiers exist:
47 u - user-space counting
49 h - hypervisor counting
51 G - guest counting (in KVM guests)
52 H - host counting (not in KVM guests)
54 P - use maximum detected precise level
55 S - read sample value (PERF_SAMPLE_READ)
56 D - pin the event to the PMU
57 W - group is weak and will fallback to non-group if not schedulable,
59 The 'p' modifier can be used for specifying how precise the instruction
60 address should be. The 'p' modifier can be specified multiple times:
62 0 - SAMPLE_IP can have arbitrary skid
63 1 - SAMPLE_IP must have constant skid
64 2 - SAMPLE_IP requested to have 0 skid
65 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
66 sample shadowing effects.
68 For Intel systems precise event sampling is implemented with PEBS
69 which supports up to precise-level 2, and precise level 3 for
72 On AMD systems it is implemented using IBS (up to precise-level 2).
73 The precise modifier works with event types 0x76 (cpu-cycles, CPU
74 clocks not halted) and 0xC1 (micro-ops retired). Both events map to
75 IBS execution sampling (IBS op) with the IBS Op Counter Control bit
76 (IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
77 Manual Volume 2: System Programming, 13.3 Instruction-Based
78 Sampling). Examples to use IBS:
80 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles
81 perf record -a -e r076:p ... # same as -e cpu-cycles:p
82 perf record -a -e r0C1:p ... # use ibs op counting micro-ops
84 RAW HARDWARE EVENT DESCRIPTOR
85 -----------------------------
86 Even when an event is not available in a symbolic form within perf right now,
87 it can be encoded in a per processor specific way.
89 For instance For x86 CPUs NNN represents the raw register encoding with the
90 layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
91 of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
92 Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
94 Note: Only the following bit fields can be set in x86 counter
95 registers: event, umask, edge, inv, cmask. Esp. guest/host only and
96 OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
101 If the Intel docs for a QM720 Core i7 describe an event as:
103 Event Umask Event Mask
104 Num. Value Mnemonic Description Comment
106 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
107 delivered by loop stream detector invert to count
110 raw encoding of 0x1A8 can be used:
112 perf stat -e r1a8 -a sleep 1
113 perf record -e r1a8 ...
115 You should refer to the processor specific documentation for getting these
116 details. Some of them are referenced in the SEE ALSO section below.
121 perf also supports an extended syntax for specifying raw parameters
122 to PMUs. Using this typically requires looking up the specific event
123 in the CPU vendor specific documentation.
125 The available PMUs and their raw parameters can be listed with
127 ls /sys/devices/*/format
129 For example the raw event "LSD.UOPS" core pmu event above could
132 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ...
134 or using extended name syntax
136 perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ...
141 Some PMUs are not associated with a core, but with a whole CPU socket.
142 Events on these PMUs generally cannot be sampled, but only counted globally
143 with perf stat -a. They can be bound to one logical CPU, but will measure
144 all the CPUs in the same socket.
146 This example measures memory bandwidth every second
147 on the first memory controller on socket 0 of a Intel Xeon system
149 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
151 Each memory controller has its own PMU. Measuring the complete system
152 bandwidth would require specifying all imc PMUs (see perf list output),
153 and adding the values together. To simplify creation of multiple events,
154 prefix and glob matching is supported in the PMU name, and the prefix
155 'uncore_' is also ignored when performing the match. So the command above
156 can be expanded to all memory controllers by using the syntaxes:
158 perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ...
159 perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ...
161 This example measures the combined core power every second
163 perf stat -I 1000 -e power/energy-cores/ -a
168 For non root users generally only context switched PMU events are available.
169 This is normally only the events in the cpu PMU, the predefined events
170 like cycles and instructions and some software events.
172 Other PMUs and global measurements are normally root only.
173 Some event qualifiers, such as "any", are also root only.
175 This can be overridden by setting the kernel.perf_event_paranoid
176 sysctl to -1, which allows non root to use these events.
178 For accessing trace point events perf needs to have read access to
179 /sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed
185 Some PMUs control advanced hardware tracing capabilities, such as Intel PT,
186 that allows low overhead execution tracing. These are described in a separate
187 intel-pt.txt document.
192 Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
195 hv_gpci/dtbp_ptitc,phys_processor_idx=?/
197 This means that when provided as an event, a value for '?' must
198 also be supplied. For example:
200 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
205 Perf supports time based multiplexing of events, when the number of events
206 active exceeds the number of hardware performance counters. Multiplexing
207 can cause measurement errors when the workload changes its execution
210 When metrics are computed using formulas from event counts, it is useful to
211 ensure some events are always measured together as a group to minimize multiplexing
212 errors. Event groups can be specified using { }.
214 perf stat -e '{instructions,cycles}' ...
216 The number of available performance counters depend on the CPU. A group
217 cannot contain more events than available counters.
218 For example Intel Core CPUs typically have four generic performance counters
219 for the core, plus three fixed counters for instructions, cycles and
220 ref-cycles. Some special events have restrictions on which counter they
221 can schedule, and may not support multiple instances in a single group.
222 When too many events are specified in the group some of them will not
225 Globally pinned events can limit the number of counters available for
226 other groups. On x86 systems, the NMI watchdog pins a counter by default.
227 The nmi watchdog can be disabled as root with
229 echo 0 > /proc/sys/kernel/nmi_watchdog
231 Events from multiple different PMUs cannot be mixed in a group, with
232 some exceptions for software events.
237 perf also supports group leader sampling using the :S specifier.
239 perf record -e '{cycles,instructions}:S' ...
242 Normally all events in an event group sample, but with :S only
243 the first event (the leader) samples, and it only reads the values of the
244 other events in the group.
249 Without options all known events will be listed.
251 To limit the list use:
253 . 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
255 . 'sw' or 'software' to list software events such as context switches, etc.
257 . 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
259 . 'tracepoint' to list all tracepoint events, alternatively use
260 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
263 . 'pmu' to print the kernel supplied PMU events.
265 . 'sdt' to list all Statically Defined Tracepoint events.
267 . 'metric' to list metrics
269 . 'metricgroup' to list metricgroups with metrics.
271 . If none of the above is matched, it will apply the supplied glob to all
272 events, printing the ones that match.
274 . As a last resort, it will do a substring search in all event names.
276 One or more types can be used at the same time, listing the events for the
281 . '--raw-dump', shows the raw-dump of all the events.
282 . '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
283 a certain kind of events.
287 linkperf:perf-stat[1], linkperf:perf-top[1],
288 linkperf:perf-record[1],
289 http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
290 http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]