1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015 Josh Poimboeuf <jpoimboe@redhat.com>
9 #define unlikely(cond) (cond)
11 #include "../../../arch/x86/lib/inat.c"
12 #include "../../../arch/x86/lib/insn.c"
14 #include "../../check.h"
15 #include "../../elf.h"
16 #include "../../arch.h"
17 #include "../../warn.h"
18 #include <asm/orc_types.h>
20 static unsigned char op_to_cfi_reg[][2] = {
31 static int is_x86_64(const struct elf *elf)
33 switch (elf->ehdr.e_machine) {
39 WARN("unexpected ELF machine type %d", elf->ehdr.e_machine);
44 bool arch_callee_saved_reg(unsigned char reg)
71 unsigned long arch_dest_reloc_offset(int addend)
76 unsigned long arch_jump_destination(struct instruction *insn)
78 return insn->offset + insn->len + insn->immediate;
82 if (!(op = calloc(1, sizeof(*op)))) \
84 else for (list_add_tail(&op->list, ops_list); op; op = NULL)
86 int arch_decode_instruction(const struct elf *elf, const struct section *sec,
87 unsigned long offset, unsigned int maxlen,
88 unsigned int *len, enum insn_type *type,
89 unsigned long *immediate,
90 struct list_head *ops_list)
94 unsigned char op1, op2, rex = 0, rex_b = 0, rex_r = 0, rex_w = 0,
95 rex_x = 0, modrm = 0, modrm_mod = 0, modrm_rm = 0,
96 modrm_reg = 0, sib = 0;
97 struct stack_op *op = NULL;
100 x86_64 = is_x86_64(elf);
104 insn_init(&insn, sec->data->d_buf + offset, maxlen, x86_64);
105 insn_get_length(&insn);
107 if (!insn_complete(&insn)) {
108 WARN("can't decode instruction at %s:0x%lx", sec->name, offset);
115 if (insn.vex_prefix.nbytes)
118 op1 = insn.opcode.bytes[0];
119 op2 = insn.opcode.bytes[1];
121 if (insn.rex_prefix.nbytes) {
122 rex = insn.rex_prefix.bytes[0];
123 rex_w = X86_REX_W(rex) >> 3;
124 rex_r = X86_REX_R(rex) >> 2;
125 rex_x = X86_REX_X(rex) >> 1;
126 rex_b = X86_REX_B(rex);
129 if (insn.modrm.nbytes) {
130 modrm = insn.modrm.bytes[0];
131 modrm_mod = X86_MODRM_MOD(modrm);
132 modrm_reg = X86_MODRM_REG(modrm);
133 modrm_rm = X86_MODRM_RM(modrm);
137 sib = insn.sib.bytes[0];
143 if (rex_w && !rex_b && modrm_mod == 3 && modrm_rm == 4) {
145 /* add/sub reg, %rsp */
147 op->src.type = OP_SRC_ADD;
148 op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
149 op->dest.type = OP_DEST_REG;
150 op->dest.reg = CFI_SP;
159 op->src.type = OP_SRC_REG;
160 op->src.reg = op_to_cfi_reg[op1 & 0x7][rex_b];
161 op->dest.type = OP_DEST_PUSH;
170 op->src.type = OP_SRC_POP;
171 op->dest.type = OP_DEST_REG;
172 op->dest.reg = op_to_cfi_reg[op1 & 0x7][rex_b];
181 op->src.type = OP_SRC_CONST;
182 op->dest.type = OP_DEST_PUSH;
187 *type = INSN_JUMP_CONDITIONAL;
198 op->src.type = OP_SRC_AND;
199 op->src.reg = CFI_SP;
200 op->src.offset = insn.immediate.value;
201 op->dest.type = OP_DEST_REG;
202 op->dest.reg = CFI_SP;
209 else if (modrm == 0xec)
214 /* add/sub imm, %rsp */
216 op->src.type = OP_SRC_ADD;
217 op->src.reg = CFI_SP;
218 op->src.offset = insn.immediate.value * sign;
219 op->dest.type = OP_DEST_REG;
220 op->dest.reg = CFI_SP;
225 if (rex_w && !rex_r && modrm_mod == 3 && modrm_reg == 4) {
229 op->src.type = OP_SRC_REG;
230 op->src.reg = CFI_SP;
231 op->dest.type = OP_DEST_REG;
232 op->dest.reg = op_to_cfi_reg[modrm_rm][rex_b];
237 if (rex_w && !rex_b && modrm_mod == 3 && modrm_rm == 4) {
241 op->src.type = OP_SRC_REG;
242 op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
243 op->dest.type = OP_DEST_REG;
244 op->dest.reg = CFI_SP;
252 (modrm_mod == 1 || modrm_mod == 2) && modrm_rm == 5) {
254 /* mov reg, disp(%rbp) */
256 op->src.type = OP_SRC_REG;
257 op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
258 op->dest.type = OP_DEST_REG_INDIRECT;
259 op->dest.reg = CFI_BP;
260 op->dest.offset = insn.displacement.value;
263 } else if (rex_w && !rex_b && modrm_rm == 4 && sib == 0x24) {
265 /* mov reg, disp(%rsp) */
267 op->src.type = OP_SRC_REG;
268 op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
269 op->dest.type = OP_DEST_REG_INDIRECT;
270 op->dest.reg = CFI_SP;
271 op->dest.offset = insn.displacement.value;
278 if (rex_w && !rex_b && modrm_mod == 1 && modrm_rm == 5) {
280 /* mov disp(%rbp), reg */
282 op->src.type = OP_SRC_REG_INDIRECT;
283 op->src.reg = CFI_BP;
284 op->src.offset = insn.displacement.value;
285 op->dest.type = OP_DEST_REG;
286 op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
289 } else if (rex_w && !rex_b && sib == 0x24 &&
290 modrm_mod != 3 && modrm_rm == 4) {
292 /* mov disp(%rsp), reg */
294 op->src.type = OP_SRC_REG_INDIRECT;
295 op->src.reg = CFI_SP;
296 op->src.offset = insn.displacement.value;
297 op->dest.type = OP_DEST_REG;
298 op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
305 if (sib == 0x24 && rex_w && !rex_b && !rex_x) {
308 if (!insn.displacement.value) {
309 /* lea (%rsp), reg */
310 op->src.type = OP_SRC_REG;
312 /* lea disp(%rsp), reg */
313 op->src.type = OP_SRC_ADD;
314 op->src.offset = insn.displacement.value;
316 op->src.reg = CFI_SP;
317 op->dest.type = OP_DEST_REG;
318 op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
321 } else if (rex == 0x48 && modrm == 0x65) {
323 /* lea disp(%rbp), %rsp */
325 op->src.type = OP_SRC_ADD;
326 op->src.reg = CFI_BP;
327 op->src.offset = insn.displacement.value;
328 op->dest.type = OP_DEST_REG;
329 op->dest.reg = CFI_SP;
332 } else if (rex == 0x49 && modrm == 0x62 &&
333 insn.displacement.value == -8) {
336 * lea -0x8(%r10), %rsp
338 * Restoring rsp back to its original value after a
342 op->src.type = OP_SRC_ADD;
343 op->src.reg = CFI_R10;
345 op->dest.type = OP_DEST_REG;
346 op->dest.reg = CFI_SP;
349 } else if (rex == 0x49 && modrm == 0x65 &&
350 insn.displacement.value == -16) {
353 * lea -0x10(%r13), %rsp
355 * Restoring rsp back to its original value after a
359 op->src.type = OP_SRC_ADD;
360 op->src.reg = CFI_R13;
361 op->src.offset = -16;
362 op->dest.type = OP_DEST_REG;
363 op->dest.reg = CFI_SP;
372 op->src.type = OP_SRC_POP;
373 op->dest.type = OP_DEST_MEM;
384 op->src.type = OP_SRC_CONST;
385 op->dest.type = OP_DEST_PUSHF;
392 op->src.type = OP_SRC_POPF;
393 op->dest.type = OP_DEST_MEM;
403 else if (modrm == 0xcb)
406 } else if (op2 >= 0x80 && op2 <= 0x8f) {
408 *type = INSN_JUMP_CONDITIONAL;
410 } else if (op2 == 0x05 || op2 == 0x07 || op2 == 0x34 ||
413 /* sysenter, sysret */
414 *type = INSN_CONTEXT_SWITCH;
416 } else if (op2 == 0x0b || op2 == 0xb9) {
421 } else if (op2 == 0x0d || op2 == 0x1f) {
426 } else if (op2 == 0xa0 || op2 == 0xa8) {
430 op->src.type = OP_SRC_CONST;
431 op->dest.type = OP_DEST_PUSH;
434 } else if (op2 == 0xa1 || op2 == 0xa9) {
438 op->src.type = OP_SRC_POP;
439 op->dest.type = OP_DEST_MEM;
454 op->dest.type = OP_DEST_LEAVE;
460 *type = INSN_JUMP_CONDITIONAL;
465 *type = INSN_JUMP_UNCONDITIONAL;
473 case 0xcf: /* iret */
475 * Handle sync_core(), which has an IRET to self.
476 * All other IRET are in STT_NONE entry code.
478 sym = find_symbol_containing(sec, offset);
479 if (sym && sym->type == STT_FUNC) {
482 op->src.type = OP_SRC_ADD;
483 op->src.reg = CFI_SP;
484 op->src.offset = 5*8;
485 op->dest.type = OP_DEST_REG;
486 op->dest.reg = CFI_SP;
493 case 0xca: /* retf */
494 case 0xcb: /* retf */
495 *type = INSN_CONTEXT_SWITCH;
501 * For the impact on the stack, a CALL behaves like
502 * a PUSH of an immediate value (the return address).
505 op->src.type = OP_SRC_CONST;
506 op->dest.type = OP_DEST_PUSH;
519 if (modrm_reg == 2 || modrm_reg == 3)
521 *type = INSN_CALL_DYNAMIC;
523 else if (modrm_reg == 4)
525 *type = INSN_JUMP_DYNAMIC;
527 else if (modrm_reg == 5)
530 *type = INSN_CONTEXT_SWITCH;
532 else if (modrm_reg == 6) {
536 op->src.type = OP_SRC_CONST;
537 op->dest.type = OP_DEST_PUSH;
547 *immediate = insn.immediate.nbytes ? insn.immediate.value : 0;
552 void arch_initial_func_cfi_state(struct cfi_init_state *state)
556 for (i = 0; i < CFI_NUM_REGS; i++) {
557 state->regs[i].base = CFI_UNDEFINED;
558 state->regs[i].offset = 0;
561 /* initial CFA (call frame address) */
562 state->cfa.base = CFI_SP;
563 state->cfa.offset = 8;
565 /* initial RA (return address) */
566 state->regs[16].base = CFI_CFA;
567 state->regs[16].offset = -8;
570 const char *arch_nop_insn(int len)
572 static const char nops[5][5] = {
574 /* 2 */ { 0x66, 0x90 },
575 /* 3 */ { 0x0f, 0x1f, 0x00 },
576 /* 4 */ { 0x0f, 0x1f, 0x40, 0x00 },
577 /* 5 */ { 0x0f, 0x1f, 0x44, 0x00, 0x00 },
580 if (len < 1 || len > 5) {
581 WARN("invalid NOP size: %d\n", len);
588 int arch_decode_hint_reg(struct instruction *insn, u8 sp_reg)
590 struct cfi_reg *cfa = &insn->cfi.cfa;
593 case ORC_REG_UNDEFINED:
594 cfa->base = CFI_UNDEFINED;
602 case ORC_REG_SP_INDIRECT:
603 cfa->base = CFI_SP_INDIRECT;