1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015 Josh Poimboeuf <jpoimboe@redhat.com>
9 #define unlikely(cond) (cond)
11 #include "../../../arch/x86/lib/inat.c"
12 #include "../../../arch/x86/lib/insn.c"
14 #include <asm/orc_types.h>
15 #include <objtool/check.h>
16 #include <objtool/elf.h>
17 #include <objtool/arch.h>
18 #include <objtool/warn.h>
20 static unsigned char op_to_cfi_reg[][2] = {
31 static int is_x86_64(const struct elf *elf)
33 switch (elf->ehdr.e_machine) {
39 WARN("unexpected ELF machine type %d", elf->ehdr.e_machine);
44 bool arch_callee_saved_reg(unsigned char reg)
71 unsigned long arch_dest_reloc_offset(int addend)
76 unsigned long arch_jump_destination(struct instruction *insn)
78 return insn->offset + insn->len + insn->immediate;
82 if (!(op = calloc(1, sizeof(*op)))) \
84 else for (list_add_tail(&op->list, ops_list); op; op = NULL)
86 int arch_decode_instruction(const struct elf *elf, const struct section *sec,
87 unsigned long offset, unsigned int maxlen,
88 unsigned int *len, enum insn_type *type,
89 unsigned long *immediate,
90 struct list_head *ops_list)
94 unsigned char op1, op2, rex = 0, rex_b = 0, rex_r = 0, rex_w = 0,
95 rex_x = 0, modrm = 0, modrm_mod = 0, modrm_rm = 0,
96 modrm_reg = 0, sib = 0;
97 struct stack_op *op = NULL;
100 x86_64 = is_x86_64(elf);
104 insn_init(&insn, sec->data->d_buf + offset, maxlen, x86_64);
105 insn_get_length(&insn);
107 if (!insn_complete(&insn)) {
108 WARN("can't decode instruction at %s:0x%lx", sec->name, offset);
115 if (insn.vex_prefix.nbytes)
118 op1 = insn.opcode.bytes[0];
119 op2 = insn.opcode.bytes[1];
121 if (insn.rex_prefix.nbytes) {
122 rex = insn.rex_prefix.bytes[0];
123 rex_w = X86_REX_W(rex) >> 3;
124 rex_r = X86_REX_R(rex) >> 2;
125 rex_x = X86_REX_X(rex) >> 1;
126 rex_b = X86_REX_B(rex);
129 if (insn.modrm.nbytes) {
130 modrm = insn.modrm.bytes[0];
131 modrm_mod = X86_MODRM_MOD(modrm);
132 modrm_reg = X86_MODRM_REG(modrm);
133 modrm_rm = X86_MODRM_RM(modrm);
137 sib = insn.sib.bytes[0];
143 if (rex_w && !rex_b && modrm_mod == 3 && modrm_rm == 4) {
145 /* add/sub reg, %rsp */
147 op->src.type = OP_SRC_ADD;
148 op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
149 op->dest.type = OP_DEST_REG;
150 op->dest.reg = CFI_SP;
159 op->src.type = OP_SRC_REG;
160 op->src.reg = op_to_cfi_reg[op1 & 0x7][rex_b];
161 op->dest.type = OP_DEST_PUSH;
170 op->src.type = OP_SRC_POP;
171 op->dest.type = OP_DEST_REG;
172 op->dest.reg = op_to_cfi_reg[op1 & 0x7][rex_b];
181 op->src.type = OP_SRC_CONST;
182 op->dest.type = OP_DEST_PUSH;
187 *type = INSN_JUMP_CONDITIONAL;
198 op->src.type = OP_SRC_AND;
199 op->src.reg = CFI_SP;
200 op->src.offset = insn.immediate.value;
201 op->dest.type = OP_DEST_REG;
202 op->dest.reg = CFI_SP;
209 else if (modrm == 0xec)
214 /* add/sub imm, %rsp */
216 op->src.type = OP_SRC_ADD;
217 op->src.reg = CFI_SP;
218 op->src.offset = insn.immediate.value * sign;
219 op->dest.type = OP_DEST_REG;
220 op->dest.reg = CFI_SP;
225 if (rex_w && !rex_r && modrm_reg == 4) {
227 if (modrm_mod == 3) {
230 op->src.type = OP_SRC_REG;
231 op->src.reg = CFI_SP;
232 op->dest.type = OP_DEST_REG;
233 op->dest.reg = op_to_cfi_reg[modrm_rm][rex_b];
238 /* skip nontrivial SIB */
239 if (modrm_rm == 4 && !(sib == 0x24 && rex_b == rex_x))
242 /* skip RIP relative displacement */
243 if (modrm_rm == 5 && modrm_mod == 0)
246 /* mov %rsp, disp(%reg) */
248 op->src.type = OP_SRC_REG;
249 op->src.reg = CFI_SP;
250 op->dest.type = OP_DEST_REG_INDIRECT;
251 op->dest.reg = op_to_cfi_reg[modrm_rm][rex_b];
252 op->dest.offset = insn.displacement.value;
260 if (rex_w && !rex_b && modrm_mod == 3 && modrm_rm == 4) {
264 op->src.type = OP_SRC_REG;
265 op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
266 op->dest.type = OP_DEST_REG;
267 op->dest.reg = CFI_SP;
275 (modrm_mod == 1 || modrm_mod == 2) && modrm_rm == 5) {
277 /* mov reg, disp(%rbp) */
279 op->src.type = OP_SRC_REG;
280 op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
281 op->dest.type = OP_DEST_REG_INDIRECT;
282 op->dest.reg = CFI_BP;
283 op->dest.offset = insn.displacement.value;
288 if (rex_w && !rex_b && modrm_rm == 4 && sib == 0x24) {
290 /* mov reg, disp(%rsp) */
292 op->src.type = OP_SRC_REG;
293 op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
294 op->dest.type = OP_DEST_REG_INDIRECT;
295 op->dest.reg = CFI_SP;
296 op->dest.offset = insn.displacement.value;
304 if (rex_w && !rex_b && modrm_mod == 1 && modrm_rm == 5) {
306 /* mov disp(%rbp), reg */
308 op->src.type = OP_SRC_REG_INDIRECT;
309 op->src.reg = CFI_BP;
310 op->src.offset = insn.displacement.value;
311 op->dest.type = OP_DEST_REG;
312 op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
315 } else if (rex_w && !rex_b && sib == 0x24 &&
316 modrm_mod != 3 && modrm_rm == 4) {
318 /* mov disp(%rsp), reg */
320 op->src.type = OP_SRC_REG_INDIRECT;
321 op->src.reg = CFI_SP;
322 op->src.offset = insn.displacement.value;
323 op->dest.type = OP_DEST_REG;
324 op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
331 if (sib == 0x24 && rex_w && !rex_b && !rex_x) {
334 if (!insn.displacement.value) {
335 /* lea (%rsp), reg */
336 op->src.type = OP_SRC_REG;
338 /* lea disp(%rsp), reg */
339 op->src.type = OP_SRC_ADD;
340 op->src.offset = insn.displacement.value;
342 op->src.reg = CFI_SP;
343 op->dest.type = OP_DEST_REG;
344 op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
347 } else if (rex == 0x48 && modrm == 0x65) {
349 /* lea disp(%rbp), %rsp */
351 op->src.type = OP_SRC_ADD;
352 op->src.reg = CFI_BP;
353 op->src.offset = insn.displacement.value;
354 op->dest.type = OP_DEST_REG;
355 op->dest.reg = CFI_SP;
358 } else if (rex == 0x49 && modrm == 0x62 &&
359 insn.displacement.value == -8) {
362 * lea -0x8(%r10), %rsp
364 * Restoring rsp back to its original value after a
368 op->src.type = OP_SRC_ADD;
369 op->src.reg = CFI_R10;
371 op->dest.type = OP_DEST_REG;
372 op->dest.reg = CFI_SP;
375 } else if (rex == 0x49 && modrm == 0x65 &&
376 insn.displacement.value == -16) {
379 * lea -0x10(%r13), %rsp
381 * Restoring rsp back to its original value after a
385 op->src.type = OP_SRC_ADD;
386 op->src.reg = CFI_R13;
387 op->src.offset = -16;
388 op->dest.type = OP_DEST_REG;
389 op->dest.reg = CFI_SP;
398 op->src.type = OP_SRC_POP;
399 op->dest.type = OP_DEST_MEM;
410 op->src.type = OP_SRC_CONST;
411 op->dest.type = OP_DEST_PUSHF;
418 op->src.type = OP_SRC_POPF;
419 op->dest.type = OP_DEST_MEM;
429 else if (modrm == 0xcb)
432 } else if (op2 >= 0x80 && op2 <= 0x8f) {
434 *type = INSN_JUMP_CONDITIONAL;
436 } else if (op2 == 0x05 || op2 == 0x07 || op2 == 0x34 ||
439 /* sysenter, sysret */
440 *type = INSN_CONTEXT_SWITCH;
442 } else if (op2 == 0x0b || op2 == 0xb9) {
447 } else if (op2 == 0x0d || op2 == 0x1f) {
452 } else if (op2 == 0xa0 || op2 == 0xa8) {
456 op->src.type = OP_SRC_CONST;
457 op->dest.type = OP_DEST_PUSH;
460 } else if (op2 == 0xa1 || op2 == 0xa9) {
464 op->src.type = OP_SRC_POP;
465 op->dest.type = OP_DEST_MEM;
480 op->dest.type = OP_DEST_LEAVE;
486 *type = INSN_JUMP_CONDITIONAL;
491 *type = INSN_JUMP_UNCONDITIONAL;
499 case 0xcf: /* iret */
501 * Handle sync_core(), which has an IRET to self.
502 * All other IRET are in STT_NONE entry code.
504 sym = find_symbol_containing(sec, offset);
505 if (sym && sym->type == STT_FUNC) {
508 op->src.type = OP_SRC_ADD;
509 op->src.reg = CFI_SP;
510 op->src.offset = 5*8;
511 op->dest.type = OP_DEST_REG;
512 op->dest.reg = CFI_SP;
519 case 0xca: /* retf */
520 case 0xcb: /* retf */
521 *type = INSN_CONTEXT_SWITCH;
527 * For the impact on the stack, a CALL behaves like
528 * a PUSH of an immediate value (the return address).
531 op->src.type = OP_SRC_CONST;
532 op->dest.type = OP_DEST_PUSH;
545 if (modrm_reg == 2 || modrm_reg == 3)
547 *type = INSN_CALL_DYNAMIC;
549 else if (modrm_reg == 4)
551 *type = INSN_JUMP_DYNAMIC;
553 else if (modrm_reg == 5)
556 *type = INSN_CONTEXT_SWITCH;
558 else if (modrm_reg == 6) {
562 op->src.type = OP_SRC_CONST;
563 op->dest.type = OP_DEST_PUSH;
573 *immediate = insn.immediate.nbytes ? insn.immediate.value : 0;
578 void arch_initial_func_cfi_state(struct cfi_init_state *state)
582 for (i = 0; i < CFI_NUM_REGS; i++) {
583 state->regs[i].base = CFI_UNDEFINED;
584 state->regs[i].offset = 0;
587 /* initial CFA (call frame address) */
588 state->cfa.base = CFI_SP;
589 state->cfa.offset = 8;
591 /* initial RA (return address) */
592 state->regs[CFI_RA].base = CFI_CFA;
593 state->regs[CFI_RA].offset = -8;
596 const char *arch_nop_insn(int len)
598 static const char nops[5][5] = {
600 /* 2 */ { 0x66, 0x90 },
601 /* 3 */ { 0x0f, 0x1f, 0x00 },
602 /* 4 */ { 0x0f, 0x1f, 0x40, 0x00 },
603 /* 5 */ { 0x0f, 0x1f, 0x44, 0x00, 0x00 },
606 if (len < 1 || len > 5) {
607 WARN("invalid NOP size: %d\n", len);
614 int arch_decode_hint_reg(struct instruction *insn, u8 sp_reg)
616 struct cfi_reg *cfa = &insn->cfi.cfa;
619 case ORC_REG_UNDEFINED:
620 cfa->base = CFI_UNDEFINED;
628 case ORC_REG_SP_INDIRECT:
629 cfa->base = CFI_SP_INDIRECT;