sound/x86/intel_hdmi_audio.c

   1 /*
   2  *   intel_hdmi_audio.c - Intel HDMI audio driver
   3  *
   4  *  Copyright (C) 2016 Intel Corp
   5  *  Authors:    Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
   6  *              Ramesh Babu K V <ramesh.babu@intel.com>
   7  *              Vaibhav Agarwal <vaibhav.agarwal@intel.com>
   8  *              Jerome Anand <jerome.anand@intel.com>
   9  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; version 2 of the License.
  14  *
  15  *  This program is distributed in the hope that it will be useful, but
  16  *  WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  *  General Public License for more details.
  19  *
  20  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  21  * ALSA driver for Intel HDMI audio
  22  */
  23
  24 #include <linux/types.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/io.h>
  27 #include <linux/slab.h>
  28 #include <linux/module.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/dma-mapping.h>
  32 #include <asm/cacheflush.h>
  33 #include <sound/core.h>
  34 #include <sound/asoundef.h>
  35 #include <sound/pcm.h>
  36 #include <sound/pcm_params.h>
  37 #include <sound/initval.h>
  38 #include <sound/control.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/intel_lpe_audio.h>
  41 #include "intel_hdmi_audio.h"
  42
  43 /*standard module options for ALSA. This module supports only one card*/
  44 static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
  45 static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
  46
  47 module_param_named(index, hdmi_card_index, int, 0444);
  48 MODULE_PARM_DESC(index,
  49                 "Index value for INTEL Intel HDMI Audio controller.");
  50 module_param_named(id, hdmi_card_id, charp, 0444);
  51 MODULE_PARM_DESC(id,
  52                 "ID string for INTEL Intel HDMI Audio controller.");
  53
  54 /*
  55  * ELD SA bits in the CEA Speaker Allocation data block
  56  */
  57 static const int eld_speaker_allocation_bits[] = {
  58         [0] = FL | FR,
  59         [1] = LFE,
  60         [2] = FC,
  61         [3] = RL | RR,
  62         [4] = RC,
  63         [5] = FLC | FRC,
  64         [6] = RLC | RRC,
  65         /* the following are not defined in ELD yet */
  66         [7] = 0,
  67 };
  68
  69 /*
  70  * This is an ordered list!
  71  *
  72  * The preceding ones have better chances to be selected by
  73  * hdmi_channel_allocation().
  74  */
  75 static struct cea_channel_speaker_allocation channel_allocations[] = {
  76 /*                        channel:   7     6    5    4    3     2    1    0  */
  77 { .ca_index = 0x00,  .speakers = {   0,    0,   0,   0,   0,    0,  FR,  FL } },
  78                                 /* 2.1 */
  79 { .ca_index = 0x01,  .speakers = {   0,    0,   0,   0,   0,  LFE,  FR,  FL } },
  80                                 /* Dolby Surround */
  81 { .ca_index = 0x02,  .speakers = {   0,    0,   0,   0,  FC,    0,  FR,  FL } },
  82                                 /* surround40 */
  83 { .ca_index = 0x08,  .speakers = {   0,    0,  RR,  RL,   0,    0,  FR,  FL } },
  84                                 /* surround41 */
  85 { .ca_index = 0x09,  .speakers = {   0,    0,  RR,  RL,   0,  LFE,  FR,  FL } },
  86                                 /* surround50 */
  87 { .ca_index = 0x0a,  .speakers = {   0,    0,  RR,  RL,  FC,    0,  FR,  FL } },
  88                                 /* surround51 */
  89 { .ca_index = 0x0b,  .speakers = {   0,    0,  RR,  RL,  FC,  LFE,  FR,  FL } },
  90                                 /* 6.1 */
  91 { .ca_index = 0x0f,  .speakers = {   0,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
  92                                 /* surround71 */
  93 { .ca_index = 0x13,  .speakers = { RRC,  RLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
  94
  95 { .ca_index = 0x03,  .speakers = {   0,    0,   0,   0,  FC,  LFE,  FR,  FL } },
  96 { .ca_index = 0x04,  .speakers = {   0,    0,   0,  RC,   0,    0,  FR,  FL } },
  97 { .ca_index = 0x05,  .speakers = {   0,    0,   0,  RC,   0,  LFE,  FR,  FL } },
  98 { .ca_index = 0x06,  .speakers = {   0,    0,   0,  RC,  FC,    0,  FR,  FL } },
  99 { .ca_index = 0x07,  .speakers = {   0,    0,   0,  RC,  FC,  LFE,  FR,  FL } },
 100 { .ca_index = 0x0c,  .speakers = {   0,   RC,  RR,  RL,   0,    0,  FR,  FL } },
 101 { .ca_index = 0x0d,  .speakers = {   0,   RC,  RR,  RL,   0,  LFE,  FR,  FL } },
 102 { .ca_index = 0x0e,  .speakers = {   0,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
 103 { .ca_index = 0x10,  .speakers = { RRC,  RLC,  RR,  RL,   0,    0,  FR,  FL } },
 104 { .ca_index = 0x11,  .speakers = { RRC,  RLC,  RR,  RL,   0,  LFE,  FR,  FL } },
 105 { .ca_index = 0x12,  .speakers = { RRC,  RLC,  RR,  RL,  FC,    0,  FR,  FL } },
 106 { .ca_index = 0x14,  .speakers = { FRC,  FLC,   0,   0,   0,    0,  FR,  FL } },
 107 { .ca_index = 0x15,  .speakers = { FRC,  FLC,   0,   0,   0,  LFE,  FR,  FL } },
 108 { .ca_index = 0x16,  .speakers = { FRC,  FLC,   0,   0,  FC,    0,  FR,  FL } },
 109 { .ca_index = 0x17,  .speakers = { FRC,  FLC,   0,   0,  FC,  LFE,  FR,  FL } },
 110 { .ca_index = 0x18,  .speakers = { FRC,  FLC,   0,  RC,   0,    0,  FR,  FL } },
 111 { .ca_index = 0x19,  .speakers = { FRC,  FLC,   0,  RC,   0,  LFE,  FR,  FL } },
 112 { .ca_index = 0x1a,  .speakers = { FRC,  FLC,   0,  RC,  FC,    0,  FR,  FL } },
 113 { .ca_index = 0x1b,  .speakers = { FRC,  FLC,   0,  RC,  FC,  LFE,  FR,  FL } },
 114 { .ca_index = 0x1c,  .speakers = { FRC,  FLC,  RR,  RL,   0,    0,  FR,  FL } },
 115 { .ca_index = 0x1d,  .speakers = { FRC,  FLC,  RR,  RL,   0,  LFE,  FR,  FL } },
 116 { .ca_index = 0x1e,  .speakers = { FRC,  FLC,  RR,  RL,  FC,    0,  FR,  FL } },
 117 { .ca_index = 0x1f,  .speakers = { FRC,  FLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 118 };
 119
 120 static const struct channel_map_table map_tables[] = {
 121         { SNDRV_CHMAP_FL,       0x00,   FL },
 122         { SNDRV_CHMAP_FR,       0x01,   FR },
 123         { SNDRV_CHMAP_RL,       0x04,   RL },
 124         { SNDRV_CHMAP_RR,       0x05,   RR },
 125         { SNDRV_CHMAP_LFE,      0x02,   LFE },
 126         { SNDRV_CHMAP_FC,       0x03,   FC },
 127         { SNDRV_CHMAP_RLC,      0x06,   RLC },
 128         { SNDRV_CHMAP_RRC,      0x07,   RRC },
 129         {} /* terminator */
 130 };
 131
 132 /* hardware capability structure */
 133 static const struct snd_pcm_hardware had_pcm_hardware = {
 134         .info = (SNDRV_PCM_INFO_INTERLEAVED |
 135                 SNDRV_PCM_INFO_DOUBLE |
 136                 SNDRV_PCM_INFO_MMAP|
 137                 SNDRV_PCM_INFO_MMAP_VALID |
 138                 SNDRV_PCM_INFO_BATCH),
 139         .formats = SNDRV_PCM_FMTBIT_S24,
 140         .rates = SNDRV_PCM_RATE_32000 |
 141                 SNDRV_PCM_RATE_44100 |
 142                 SNDRV_PCM_RATE_48000 |
 143                 SNDRV_PCM_RATE_88200 |
 144                 SNDRV_PCM_RATE_96000 |
 145                 SNDRV_PCM_RATE_176400 |
 146                 SNDRV_PCM_RATE_192000,
 147         .rate_min = HAD_MIN_RATE,
 148         .rate_max = HAD_MAX_RATE,
 149         .channels_min = HAD_MIN_CHANNEL,
 150         .channels_max = HAD_MAX_CHANNEL,
 151         .buffer_bytes_max = HAD_MAX_BUFFER,
 152         .period_bytes_min = HAD_MIN_PERIOD_BYTES,
 153         .period_bytes_max = HAD_MAX_PERIOD_BYTES,
 154         .periods_min = HAD_MIN_PERIODS,
 155         .periods_max = HAD_MAX_PERIODS,
 156         .fifo_size = HAD_FIFO_SIZE,
 157 };
 158
 159 /* Get the active PCM substream;
 160  * Call had_substream_put() for unreferecing.
 161  * Don't call this inside had_spinlock, as it takes by itself
 162  */
 163 static struct snd_pcm_substream *
 164 had_substream_get(struct snd_intelhad *intelhaddata)
 165 {
 166         struct snd_pcm_substream *substream;
 167         unsigned long flags;
 168
 169         spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
 170         substream = intelhaddata->stream_info.substream;
 171         if (substream)
 172                 intelhaddata->stream_info.substream_refcount++;
 173         spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
 174         return substream;
 175 }
 176
 177 /* Unref the active PCM substream;
 178  * Don't call this inside had_spinlock, as it takes by itself
 179  */
 180 static void had_substream_put(struct snd_intelhad *intelhaddata)
 181 {
 182         unsigned long flags;
 183
 184         spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
 185         intelhaddata->stream_info.substream_refcount--;
 186         spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
 187 }
 188
 189 /* Register access functions */
 190 static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val)
 191 {
 192         *val = ioread32(ctx->mmio_start + ctx->had_config_offset + reg);
 193 }
 194
 195 static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val)
 196 {
 197         iowrite32(val, ctx->mmio_start + ctx->had_config_offset + reg);
 198 }
 199
 200 /*
 201  * enable / disable audio configuration
 202  *
 203  * The normal read/modify should not directly be used on VLV2 for
 204  * updating AUD_CONFIG register.
 205  * This is because:
 206  * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2
 207  * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always
 208  * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the
 209  * register. This field should be 1xy binary for configuration with 6 or
 210  * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio)
 211  * causes the "channels" field to be updated as 0xy binary resulting in
 212  * bad audio. The fix is to always write the AUD_CONFIG[6:4] with
 213  * appropriate value when doing read-modify of AUD_CONFIG register.
 214  */
 215 static void had_enable_audio(struct snd_pcm_substream *substream,
 216                              struct snd_intelhad *intelhaddata,
 217                              bool enable)
 218 {
 219         union aud_cfg cfg_val = {.regval = 0};
 220         u8 channels;
 221         u32 mask, val;
 222
 223         /*
 224          * If substream is NULL, there is no active stream.
 225          * In this case just set channels to 2
 226          */
 227         channels = substream ? substream->runtime->channels : 2;
 228         dev_dbg(intelhaddata->dev, "enable %d, ch=%d\n", enable, channels);
 229
 230         cfg_val.regx.num_ch = channels - 2;
 231         if (enable)
 232                 cfg_val.regx.aud_en = 1;
 233         mask = AUD_CONFIG_CH_MASK | 1;
 234
 235         had_read_register(intelhaddata, AUD_CONFIG, &val);
 236         val &= ~mask;
 237         val |= cfg_val.regval;
 238         had_write_register(intelhaddata, AUD_CONFIG, val);
 239 }
 240
 241 /* enable / disable the audio interface */
 242 static void had_enable_audio_int(struct snd_intelhad *ctx, bool enable)
 243 {
 244         u32 status_reg;
 245
 246         if (enable) {
 247                 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
 248                 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
 249                 had_write_register(ctx, AUD_HDMI_STATUS, status_reg);
 250                 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
 251         }
 252 }
 253
 254 /* Reset buffer pointers */
 255 static void had_reset_audio(struct snd_intelhad *intelhaddata)
 256 {
 257         had_write_register(intelhaddata, AUD_HDMI_STATUS, 1);
 258         had_write_register(intelhaddata, AUD_HDMI_STATUS, 0);
 259 }
 260
 261 /*
 262  * initialize audio channel status registers
 263  * This function is called in the prepare callback
 264  */
 265 static int had_prog_status_reg(struct snd_pcm_substream *substream,
 266                         struct snd_intelhad *intelhaddata)
 267 {
 268         union aud_cfg cfg_val = {.regval = 0};
 269         union aud_ch_status_0 ch_stat0 = {.regval = 0};
 270         union aud_ch_status_1 ch_stat1 = {.regval = 0};
 271         int format;
 272
 273         ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits &
 274                                           IEC958_AES0_NONAUDIO) >> 1;
 275         ch_stat0.regx.clk_acc = (intelhaddata->aes_bits &
 276                                           IEC958_AES3_CON_CLOCK) >> 4;
 277         cfg_val.regx.val_bit = ch_stat0.regx.lpcm_id;
 278
 279         switch (substream->runtime->rate) {
 280         case AUD_SAMPLE_RATE_32:
 281                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ;
 282                 break;
 283
 284         case AUD_SAMPLE_RATE_44_1:
 285                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ;
 286                 break;
 287         case AUD_SAMPLE_RATE_48:
 288                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ;
 289                 break;
 290         case AUD_SAMPLE_RATE_88_2:
 291                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ;
 292                 break;
 293         case AUD_SAMPLE_RATE_96:
 294                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ;
 295                 break;
 296         case AUD_SAMPLE_RATE_176_4:
 297                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ;
 298                 break;
 299         case AUD_SAMPLE_RATE_192:
 300                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ;
 301                 break;
 302
 303         default:
 304                 /* control should never come here */
 305                 return -EINVAL;
 306         }
 307
 308         had_write_register(intelhaddata,
 309                            AUD_CH_STATUS_0, ch_stat0.regval);
 310
 311         format = substream->runtime->format;
 312
 313         if (format == SNDRV_PCM_FORMAT_S16_LE) {
 314                 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20;
 315                 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS;
 316         } else if (format == SNDRV_PCM_FORMAT_S24_LE) {
 317                 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24;
 318                 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS;
 319         } else {
 320                 ch_stat1.regx.max_wrd_len = 0;
 321                 ch_stat1.regx.wrd_len = 0;
 322         }
 323
 324         had_write_register(intelhaddata,
 325                            AUD_CH_STATUS_1, ch_stat1.regval);
 326         return 0;
 327 }
 328
 329 /*
 330  * function to initialize audio
 331  * registers and buffer confgiuration registers
 332  * This function is called in the prepare callback
 333  */
 334 static int had_init_audio_ctrl(struct snd_pcm_substream *substream,
 335                                struct snd_intelhad *intelhaddata)
 336 {
 337         union aud_cfg cfg_val = {.regval = 0};
 338         union aud_buf_config buf_cfg = {.regval = 0};
 339         u8 channels;
 340
 341         had_prog_status_reg(substream, intelhaddata);
 342
 343         buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD;
 344         buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
 345         buf_cfg.regx.aud_delay = 0;
 346         had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval);
 347
 348         channels = substream->runtime->channels;
 349         cfg_val.regx.num_ch = channels - 2;
 350         if (channels <= 2)
 351                 cfg_val.regx.layout = LAYOUT0;
 352         else
 353                 cfg_val.regx.layout = LAYOUT1;
 354
 355         cfg_val.regx.val_bit = 1;
 356
 357         /* fix up the DP bits */
 358         if (intelhaddata->dp_output) {
 359                 cfg_val.regx.dp_modei = 1;
 360                 cfg_val.regx.set = 1;
 361         }
 362
 363         had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval);
 364         return 0;
 365 }
 366
 367 /*
 368  * Compute derived values in channel_allocations[].
 369  */
 370 static void init_channel_allocations(void)
 371 {
 372         int i, j;
 373         struct cea_channel_speaker_allocation *p;
 374
 375         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 376                 p = channel_allocations + i;
 377                 p->channels = 0;
 378                 p->spk_mask = 0;
 379                 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
 380                         if (p->speakers[j]) {
 381                                 p->channels++;
 382                                 p->spk_mask |= p->speakers[j];
 383                         }
 384         }
 385 }
 386
 387 /*
 388  * The transformation takes two steps:
 389  *
 390  *      eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
 391  *            spk_mask => (channel_allocations[])         => ai->CA
 392  *
 393  * TODO: it could select the wrong CA from multiple candidates.
 394  */
 395 static int had_channel_allocation(struct snd_intelhad *intelhaddata,
 396                                   int channels)
 397 {
 398         int i;
 399         int ca = 0;
 400         int spk_mask = 0;
 401
 402         /*
 403          * CA defaults to 0 for basic stereo audio
 404          */
 405         if (channels <= 2)
 406                 return 0;
 407
 408         /*
 409          * expand ELD's speaker allocation mask
 410          *
 411          * ELD tells the speaker mask in a compact(paired) form,
 412          * expand ELD's notions to match the ones used by Audio InfoFrame.
 413          */
 414
 415         for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
 416                 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
 417                         spk_mask |= eld_speaker_allocation_bits[i];
 418         }
 419
 420         /* search for the first working match in the CA table */
 421         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 422                 if (channels == channel_allocations[i].channels &&
 423                 (spk_mask & channel_allocations[i].spk_mask) ==
 424                                 channel_allocations[i].spk_mask) {
 425                         ca = channel_allocations[i].ca_index;
 426                         break;
 427                 }
 428         }
 429
 430         dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels);
 431
 432         return ca;
 433 }
 434
 435 /* from speaker bit mask to ALSA API channel position */
 436 static int spk_to_chmap(int spk)
 437 {
 438         const struct channel_map_table *t = map_tables;
 439
 440         for (; t->map; t++) {
 441                 if (t->spk_mask == spk)
 442                         return t->map;
 443         }
 444         return 0;
 445 }
 446
 447 static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
 448 {
 449         int i, c;
 450         int spk_mask = 0;
 451         struct snd_pcm_chmap_elem *chmap;
 452         u8 eld_high, eld_high_mask = 0xF0;
 453         u8 high_msb;
 454
 455         chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
 456         if (!chmap) {
 457                 intelhaddata->chmap->chmap = NULL;
 458                 return;
 459         }
 460
 461         dev_dbg(intelhaddata->dev, "eld speaker = %x\n",
 462                 intelhaddata->eld[DRM_ELD_SPEAKER]);
 463
 464         /* WA: Fix the max channel supported to 8 */
 465
 466         /*
 467          * Sink may support more than 8 channels, if eld_high has more than
 468          * one bit set. SOC supports max 8 channels.
 469          * Refer eld_speaker_allocation_bits, for sink speaker allocation
 470          */
 471
 472         /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */
 473         eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask;
 474         if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
 475                 /* eld_high & (eld_high-1): if more than 1 bit set */
 476                 /* 0x1F: 7 channels */
 477                 for (i = 1; i < 4; i++) {
 478                         high_msb = eld_high & (0x80 >> i);
 479                         if (high_msb) {
 480                                 intelhaddata->eld[DRM_ELD_SPEAKER] &=
 481                                         high_msb | 0xF;
 482                                 break;
 483                         }
 484                 }
 485         }
 486
 487         for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
 488                 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
 489                         spk_mask |= eld_speaker_allocation_bits[i];
 490         }
 491
 492         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 493                 if (spk_mask == channel_allocations[i].spk_mask) {
 494                         for (c = 0; c < channel_allocations[i].channels; c++) {
 495                                 chmap->map[c] = spk_to_chmap(
 496                                         channel_allocations[i].speakers[
 497                                                 (MAX_SPEAKERS - 1) - c]);
 498                         }
 499                         chmap->channels = channel_allocations[i].channels;
 500                         intelhaddata->chmap->chmap = chmap;
 501                         break;
 502                 }
 503         }
 504         if (i >= ARRAY_SIZE(channel_allocations)) {
 505                 intelhaddata->chmap->chmap = NULL;
 506                 kfree(chmap);
 507         }
 508 }
 509
 510 /*
 511  * ALSA API channel-map control callbacks
 512  */
 513 static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
 514                                 struct snd_ctl_elem_info *uinfo)
 515 {
 516         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
 517         struct snd_intelhad *intelhaddata = info->private_data;
 518
 519         if (!intelhaddata->connected)
 520                 return -ENODEV;
 521         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 522         uinfo->count = HAD_MAX_CHANNEL;
 523         uinfo->value.integer.min = 0;
 524         uinfo->value.integer.max = SNDRV_CHMAP_LAST;
 525         return 0;
 526 }
 527
 528 static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
 529                                 struct snd_ctl_elem_value *ucontrol)
 530 {
 531         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
 532         struct snd_intelhad *intelhaddata = info->private_data;
 533         int i;
 534         const struct snd_pcm_chmap_elem *chmap;
 535
 536         if (!intelhaddata->connected)
 537                 return -ENODEV;
 538
 539         mutex_lock(&intelhaddata->mutex);
 540         if (!intelhaddata->chmap->chmap) {
 541                 mutex_unlock(&intelhaddata->mutex);
 542                 return -ENODATA;
 543         }
 544
 545         chmap = intelhaddata->chmap->chmap;
 546         for (i = 0; i < chmap->channels; i++)
 547                 ucontrol->value.integer.value[i] = chmap->map[i];
 548         mutex_unlock(&intelhaddata->mutex);
 549
 550         return 0;
 551 }
 552
 553 static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
 554                                                 struct snd_pcm *pcm)
 555 {
 556         int err;
 557
 558         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
 559                         NULL, 0, (unsigned long)intelhaddata,
 560                         &intelhaddata->chmap);
 561         if (err < 0)
 562                 return err;
 563
 564         intelhaddata->chmap->private_data = intelhaddata;
 565         intelhaddata->chmap->kctl->info = had_chmap_ctl_info;
 566         intelhaddata->chmap->kctl->get = had_chmap_ctl_get;
 567         intelhaddata->chmap->chmap = NULL;
 568         return 0;
 569 }
 570
 571 /*
 572  * Initialize Data Island Packets registers
 573  * This function is called in the prepare callback
 574  */
 575 static void had_prog_dip(struct snd_pcm_substream *substream,
 576                          struct snd_intelhad *intelhaddata)
 577 {
 578         int i;
 579         union aud_ctrl_st ctrl_state = {.regval = 0};
 580         union aud_info_frame2 frame2 = {.regval = 0};
 581         union aud_info_frame3 frame3 = {.regval = 0};
 582         u8 checksum = 0;
 583         u32 info_frame;
 584         int channels;
 585         int ca;
 586
 587         channels = substream->runtime->channels;
 588
 589         had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
 590
 591         ca = had_channel_allocation(intelhaddata, channels);
 592         if (intelhaddata->dp_output) {
 593                 info_frame = DP_INFO_FRAME_WORD1;
 594                 frame2.regval = (substream->runtime->channels - 1) | (ca << 24);
 595         } else {
 596                 info_frame = HDMI_INFO_FRAME_WORD1;
 597                 frame2.regx.chnl_cnt = substream->runtime->channels - 1;
 598                 frame3.regx.chnl_alloc = ca;
 599
 600                 /* Calculte the byte wide checksum for all valid DIP words */
 601                 for (i = 0; i < BYTES_PER_WORD; i++)
 602                         checksum += (info_frame >> (i * 8)) & 0xff;
 603                 for (i = 0; i < BYTES_PER_WORD; i++)
 604                         checksum += (frame2.regval >> (i * 8)) & 0xff;
 605                 for (i = 0; i < BYTES_PER_WORD; i++)
 606                         checksum += (frame3.regval >> (i * 8)) & 0xff;
 607
 608                 frame2.regx.chksum = -(checksum);
 609         }
 610
 611         had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame);
 612         had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval);
 613         had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval);
 614
 615         /* program remaining DIP words with zero */
 616         for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
 617                 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0);
 618
 619         ctrl_state.regx.dip_freq = 1;
 620         ctrl_state.regx.dip_en_sta = 1;
 621         had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
 622 }
 623
 624 static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
 625 {
 626         u32 maud_val;
 627
 628         /* Select maud according to DP 1.2 spec */
 629         if (link_rate == DP_2_7_GHZ) {
 630                 switch (aud_samp_freq) {
 631                 case AUD_SAMPLE_RATE_32:
 632                         maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
 633                         break;
 634
 635                 case AUD_SAMPLE_RATE_44_1:
 636                         maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
 637                         break;
 638
 639                 case AUD_SAMPLE_RATE_48:
 640                         maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
 641                         break;
 642
 643                 case AUD_SAMPLE_RATE_88_2:
 644                         maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
 645                         break;
 646
 647                 case AUD_SAMPLE_RATE_96:
 648                         maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
 649                         break;
 650
 651                 case AUD_SAMPLE_RATE_176_4:
 652                         maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
 653                         break;
 654
 655                 case HAD_MAX_RATE:
 656                         maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
 657                         break;
 658
 659                 default:
 660                         maud_val = -EINVAL;
 661                         break;
 662                 }
 663         } else if (link_rate == DP_1_62_GHZ) {
 664                 switch (aud_samp_freq) {
 665                 case AUD_SAMPLE_RATE_32:
 666                         maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
 667                         break;
 668
 669                 case AUD_SAMPLE_RATE_44_1:
 670                         maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
 671                         break;
 672
 673                 case AUD_SAMPLE_RATE_48:
 674                         maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
 675                         break;
 676
 677                 case AUD_SAMPLE_RATE_88_2:
 678                         maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
 679                         break;
 680
 681                 case AUD_SAMPLE_RATE_96:
 682                         maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
 683                         break;
 684
 685                 case AUD_SAMPLE_RATE_176_4:
 686                         maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
 687                         break;
 688
 689                 case HAD_MAX_RATE:
 690                         maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
 691                         break;
 692
 693                 default:
 694                         maud_val = -EINVAL;
 695                         break;
 696                 }
 697         } else
 698                 maud_val = -EINVAL;
 699
 700         return maud_val;
 701 }
 702
 703 /*
 704  * Program HDMI audio CTS value
 705  *
 706  * @aud_samp_freq: sampling frequency of audio data
 707  * @tmds: sampling frequency of the display data
 708  * @link_rate: DP link rate
 709  * @n_param: N value, depends on aud_samp_freq
 710  * @intelhaddata: substream private data
 711  *
 712  * Program CTS register based on the audio and display sampling frequency
 713  */
 714 static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate,
 715                          u32 n_param, struct snd_intelhad *intelhaddata)
 716 {
 717         u32 cts_val;
 718         u64 dividend, divisor;
 719
 720         if (intelhaddata->dp_output) {
 721                 /* Substitute cts_val with Maud according to DP 1.2 spec*/
 722                 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
 723         } else {
 724                 /* Calculate CTS according to HDMI 1.3a spec*/
 725                 dividend = (u64)tmds * n_param*1000;
 726                 divisor = 128 * aud_samp_freq;
 727                 cts_val = div64_u64(dividend, divisor);
 728         }
 729         dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n",
 730                  tmds, n_param, cts_val);
 731         had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
 732 }
 733
 734 static int had_calculate_n_value(u32 aud_samp_freq)
 735 {
 736         int n_val;
 737
 738         /* Select N according to HDMI 1.3a spec*/
 739         switch (aud_samp_freq) {
 740         case AUD_SAMPLE_RATE_32:
 741                 n_val = 4096;
 742                 break;
 743
 744         case AUD_SAMPLE_RATE_44_1:
 745                 n_val = 6272;
 746                 break;
 747
 748         case AUD_SAMPLE_RATE_48:
 749                 n_val = 6144;
 750                 break;
 751
 752         case AUD_SAMPLE_RATE_88_2:
 753                 n_val = 12544;
 754                 break;
 755
 756         case AUD_SAMPLE_RATE_96:
 757                 n_val = 12288;
 758                 break;
 759
 760         case AUD_SAMPLE_RATE_176_4:
 761                 n_val = 25088;
 762                 break;
 763
 764         case HAD_MAX_RATE:
 765                 n_val = 24576;
 766                 break;
 767
 768         default:
 769                 n_val = -EINVAL;
 770                 break;
 771         }
 772         return n_val;
 773 }
 774
 775 /*
 776  * Program HDMI audio N value
 777  *
 778  * @aud_samp_freq: sampling frequency of audio data
 779  * @n_param: N value, depends on aud_samp_freq
 780  * @intelhaddata: substream private data
 781  *
 782  * This function is called in the prepare callback.
 783  * It programs based on the audio and display sampling frequency
 784  */
 785 static int had_prog_n(u32 aud_samp_freq, u32 *n_param,
 786                       struct snd_intelhad *intelhaddata)
 787 {
 788         int n_val;
 789
 790         if (intelhaddata->dp_output) {
 791                 /*
 792                  * According to DP specs, Maud and Naud values hold
 793                  * a relationship, which is stated as:
 794                  * Maud/Naud = 512 * fs / f_LS_Clk
 795                  * where, fs is the sampling frequency of the audio stream
 796                  * and Naud is 32768 for Async clock.
 797                  */
 798
 799                 n_val = DP_NAUD_VAL;
 800         } else
 801                 n_val = had_calculate_n_value(aud_samp_freq);
 802
 803         if (n_val < 0)
 804                 return n_val;
 805
 806         had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
 807         *n_param = n_val;
 808         return 0;
 809 }
 810
 811 /*
 812  * PCM ring buffer handling
 813  *
 814  * The hardware provides a ring buffer with the fixed 4 buffer descriptors
 815  * (BDs).  The driver maps these 4 BDs onto the PCM ring buffer.  The mapping
 816  * moves at each period elapsed.  The below illustrates how it works:
 817  *
 818  * At time=0
 819  *  PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
 820  *  BD  | 0 | 1 | 2 | 3 |
 821  *
 822  * At time=1 (period elapsed)
 823  *  PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
 824  *  BD      | 1 | 2 | 3 | 0 |
 825  *
 826  * At time=2 (second period elapsed)
 827  *  PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
 828  *  BD          | 2 | 3 | 0 | 1 |
 829  *
 830  * The bd_head field points to the index of the BD to be read.  It's also the
 831  * position to be filled at next.  The pcm_head and the pcm_filled fields
 832  * point to the indices of the current position and of the next position to
 833  * be filled, respectively.  For PCM buffer there are both _head and _filled
 834  * because they may be difference when nperiods > 4.  For example, in the
 835  * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5:
 836  *
 837  * pcm_head (=1) --v               v-- pcm_filled (=5)
 838  *       PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
 839  *       BD      | 1 | 2 | 3 | 0 |
 840  *  bd_head (=1) --^               ^-- next to fill (= bd_head)
 841  *
 842  * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that
 843  * the hardware skips those BDs in the loop.
 844  */
 845
 846 #define AUD_BUF_ADDR(x)         (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH)
 847 #define AUD_BUF_LEN(x)          (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH)
 848
 849 /* Set up a buffer descriptor at the "filled" position */
 850 static void had_prog_bd(struct snd_pcm_substream *substream,
 851                         struct snd_intelhad *intelhaddata)
 852 {
 853         int idx = intelhaddata->bd_head;
 854         int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes;
 855         u32 addr = substream->runtime->dma_addr + ofs;
 856
 857         addr |= AUD_BUF_VALID | AUD_BUF_INTR_EN;
 858         had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr);
 859         had_write_register(intelhaddata, AUD_BUF_LEN(idx),
 860                            intelhaddata->period_bytes);
 861
 862         /* advance the indices to the next */
 863         intelhaddata->bd_head++;
 864         intelhaddata->bd_head %= intelhaddata->num_bds;
 865         intelhaddata->pcmbuf_filled++;
 866         intelhaddata->pcmbuf_filled %= substream->runtime->periods;
 867 }
 868
 869 /* invalidate a buffer descriptor with the given index */
 870 static void had_invalidate_bd(struct snd_intelhad *intelhaddata,
 871                               int idx)
 872 {
 873         had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0);
 874         had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0);
 875 }
 876
 877 /* Initial programming of ring buffer */
 878 static void had_init_ringbuf(struct snd_pcm_substream *substream,
 879                              struct snd_intelhad *intelhaddata)
 880 {
 881         struct snd_pcm_runtime *runtime = substream->runtime;
 882         int i, num_periods;
 883
 884         num_periods = runtime->periods;
 885         intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS);
 886         intelhaddata->period_bytes =
 887                 frames_to_bytes(runtime, runtime->period_size);
 888         WARN_ON(intelhaddata->period_bytes & 0x3f);
 889
 890         intelhaddata->bd_head = 0;
 891         intelhaddata->pcmbuf_head = 0;
 892         intelhaddata->pcmbuf_filled = 0;
 893
 894         for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) {
 895                 if (i < num_periods)
 896                         had_prog_bd(substream, intelhaddata);
 897                 else /* invalidate the rest */
 898                         had_invalidate_bd(intelhaddata, i);
 899         }
 900
 901         intelhaddata->bd_head = 0; /* reset at head again before starting */
 902 }
 903
 904 /* process a bd, advance to the next */
 905 static void had_advance_ringbuf(struct snd_pcm_substream *substream,
 906                                 struct snd_intelhad *intelhaddata)
 907 {
 908         int num_periods = substream->runtime->periods;
 909
 910         /* reprogram the next buffer */
 911         had_prog_bd(substream, intelhaddata);
 912
 913         /* proceed to next */
 914         intelhaddata->pcmbuf_head++;
 915         intelhaddata->pcmbuf_head %= num_periods;
 916 }
 917
 918 /* process the current BD(s);
 919  * returns the current PCM buffer byte position, or -EPIPE for underrun.
 920  */
 921 static int had_process_ringbuf(struct snd_pcm_substream *substream,
 922                                struct snd_intelhad *intelhaddata)
 923 {
 924         int len, processed;
 925         unsigned long flags;
 926
 927         processed = 0;
 928         spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
 929         for (;;) {
 930                 /* get the remaining bytes on the buffer */
 931                 had_read_register(intelhaddata,
 932                                   AUD_BUF_LEN(intelhaddata->bd_head),
 933                                   &len);
 934                 if (len < 0 || len > intelhaddata->period_bytes) {
 935                         dev_dbg(intelhaddata->dev, "Invalid buf length %d\n",
 936                                 len);
 937                         len = -EPIPE;
 938                         goto out;
 939                 }
 940
 941                 if (len > 0) /* OK, this is the current buffer */
 942                         break;
 943
 944                 /* len=0 => already empty, check the next buffer */
 945                 if (++processed >= intelhaddata->num_bds) {
 946                         len = -EPIPE; /* all empty? - report underrun */
 947                         goto out;
 948                 }
 949                 had_advance_ringbuf(substream, intelhaddata);
 950         }
 951
 952         len = intelhaddata->period_bytes - len;
 953         len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head;
 954  out:
 955         spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
 956         return len;
 957 }
 958
 959 /* called from irq handler */
 960 static void had_process_buffer_done(struct snd_intelhad *intelhaddata)
 961 {
 962         struct snd_pcm_substream *substream;
 963
 964         if (!intelhaddata->connected)
 965                 return; /* disconnected? - bail out */
 966
 967         substream = had_substream_get(intelhaddata);
 968         if (!substream)
 969                 return; /* no stream? - bail out */
 970
 971         /* process or stop the stream */
 972         if (had_process_ringbuf(substream, intelhaddata) < 0)
 973                 snd_pcm_stop_xrun(substream);
 974         else
 975                 snd_pcm_period_elapsed(substream);
 976
 977         had_substream_put(intelhaddata);
 978 }
 979
 980 #define MAX_CNT                 0xFF
 981
 982 /*
 983  * The interrupt status 'sticky' bits might not be cleared by
 984  * setting '1' to that bit once...
 985  */
 986 static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata)
 987 {
 988         int i;
 989         u32 val;
 990
 991         for (i = 0; i < MAX_CNT; i++) {
 992                 /* clear bit30, 31 AUD_HDMI_STATUS */
 993                 had_read_register(intelhaddata, AUD_HDMI_STATUS, &val);
 994                 if (!(val & AUD_CONFIG_MASK_UNDERRUN))
 995                         return;
 996                 had_write_register(intelhaddata, AUD_HDMI_STATUS, val);
 997         }
 998         dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n");
 999 }
1000
1001 /* called from irq handler */
1002 static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata)
1003 {
1004         struct snd_pcm_substream *substream;
1005
1006         /* Handle Underrun interrupt within Audio Unit */
1007         had_write_register(intelhaddata, AUD_CONFIG, 0);
1008         /* Reset buffer pointers */
1009         had_reset_audio(intelhaddata);
1010
1011         wait_clear_underrun_bit(intelhaddata);
1012
1013         if (!intelhaddata->connected)
1014                 return; /* disconnected? - bail out */
1015
1016         /* Report UNDERRUN error to above layers */
1017         substream = had_substream_get(intelhaddata);
1018         if (substream) {
1019                 snd_pcm_stop_xrun(substream);
1020                 had_substream_put(intelhaddata);
1021         }
1022 }
1023
1024 /*
1025  * ALSA PCM open callback
1026  */
1027 static int had_pcm_open(struct snd_pcm_substream *substream)
1028 {
1029         struct snd_intelhad *intelhaddata;
1030         struct snd_pcm_runtime *runtime;
1031         int retval;
1032
1033         intelhaddata = snd_pcm_substream_chip(substream);
1034         runtime = substream->runtime;
1035
1036         pm_runtime_get_sync(intelhaddata->dev);
1037
1038         if (!intelhaddata->connected) {
1039                 dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n",
1040                         __func__);
1041                 retval = -ENODEV;
1042                 goto error;
1043         }
1044
1045         /* set the runtime hw parameter with local snd_pcm_hardware struct */
1046         runtime->hw = had_pcm_hardware;
1047
1048         retval = snd_pcm_hw_constraint_integer(runtime,
1049                          SNDRV_PCM_HW_PARAM_PERIODS);
1050         if (retval < 0)
1051                 goto error;
1052
1053         /* Make sure, that the period size is always aligned
1054          * 64byte boundary
1055          */
1056         retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
1057                         SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
1058         if (retval < 0)
1059                 goto error;
1060
1061         /* expose PCM substream */
1062         spin_lock_irq(&intelhaddata->had_spinlock);
1063         intelhaddata->stream_info.substream = substream;
1064         intelhaddata->stream_info.substream_refcount++;
1065         spin_unlock_irq(&intelhaddata->had_spinlock);
1066
1067         return retval;
1068  error:
1069         pm_runtime_put(intelhaddata->dev);
1070         return retval;
1071 }
1072
1073 /*
1074  * ALSA PCM close callback
1075  */
1076 static int had_pcm_close(struct snd_pcm_substream *substream)
1077 {
1078         struct snd_intelhad *intelhaddata;
1079
1080         intelhaddata = snd_pcm_substream_chip(substream);
1081
1082         /* unreference and sync with the pending PCM accesses */
1083         spin_lock_irq(&intelhaddata->had_spinlock);
1084         intelhaddata->stream_info.substream = NULL;
1085         intelhaddata->stream_info.substream_refcount--;
1086         while (intelhaddata->stream_info.substream_refcount > 0) {
1087                 spin_unlock_irq(&intelhaddata->had_spinlock);
1088                 cpu_relax();
1089                 spin_lock_irq(&intelhaddata->had_spinlock);
1090         }
1091         spin_unlock_irq(&intelhaddata->had_spinlock);
1092
1093         pm_runtime_put(intelhaddata->dev);
1094         return 0;
1095 }
1096
1097 /*
1098  * ALSA PCM hw_params callback
1099  */
1100 static int had_pcm_hw_params(struct snd_pcm_substream *substream,
1101                              struct snd_pcm_hw_params *hw_params)
1102 {
1103         struct snd_intelhad *intelhaddata;
1104         unsigned long addr;
1105         int pages, buf_size, retval;
1106
1107         intelhaddata = snd_pcm_substream_chip(substream);
1108         buf_size = params_buffer_bytes(hw_params);
1109         retval = snd_pcm_lib_malloc_pages(substream, buf_size);
1110         if (retval < 0)
1111                 return retval;
1112         dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n",
1113                 __func__, buf_size);
1114         /* mark the pages as uncached region */
1115         addr = (unsigned long) substream->runtime->dma_area;
1116         pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / PAGE_SIZE;
1117         retval = set_memory_uc(addr, pages);
1118         if (retval) {
1119                 dev_err(intelhaddata->dev, "set_memory_uc failed.Error:%d\n",
1120                         retval);
1121                 return retval;
1122         }
1123         memset(substream->runtime->dma_area, 0, buf_size);
1124
1125         return retval;
1126 }
1127
1128 /*
1129  * ALSA PCM hw_free callback
1130  */
1131 static int had_pcm_hw_free(struct snd_pcm_substream *substream)
1132 {
1133         unsigned long addr;
1134         u32 pages;
1135
1136         /* mark back the pages as cached/writeback region before the free */
1137         if (substream->runtime->dma_area != NULL) {
1138                 addr = (unsigned long) substream->runtime->dma_area;
1139                 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) /
1140                                                                 PAGE_SIZE;
1141                 set_memory_wb(addr, pages);
1142                 return snd_pcm_lib_free_pages(substream);
1143         }
1144         return 0;
1145 }
1146
1147 /*
1148  * ALSA PCM trigger callback
1149  */
1150 static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1151 {
1152         int retval = 0;
1153         struct snd_intelhad *intelhaddata;
1154
1155         intelhaddata = snd_pcm_substream_chip(substream);
1156
1157         switch (cmd) {
1158         case SNDRV_PCM_TRIGGER_START:
1159         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1160         case SNDRV_PCM_TRIGGER_RESUME:
1161                 /* Disable local INTRs till register prgmng is done */
1162                 if (!intelhaddata->connected) {
1163                         dev_dbg(intelhaddata->dev,
1164                                 "_START: HDMI cable plugged-out\n");
1165                         retval = -ENODEV;
1166                         break;
1167                 }
1168
1169                 intelhaddata->stream_info.running = true;
1170
1171                 /* Enable Audio */
1172                 had_enable_audio_int(intelhaddata, true);
1173                 had_enable_audio(substream, intelhaddata, true);
1174                 break;
1175
1176         case SNDRV_PCM_TRIGGER_STOP:
1177         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1178         case SNDRV_PCM_TRIGGER_SUSPEND:
1179                 spin_lock(&intelhaddata->had_spinlock);
1180
1181                 /* Stop reporting BUFFER_DONE/UNDERRUN to above layers */
1182
1183                 intelhaddata->stream_info.running = false;
1184                 spin_unlock(&intelhaddata->had_spinlock);
1185                 /* Disable Audio */
1186                 had_enable_audio_int(intelhaddata, false);
1187                 had_enable_audio(substream, intelhaddata, false);
1188                 /* Reset buffer pointers */
1189                 had_reset_audio(intelhaddata);
1190                 had_enable_audio_int(intelhaddata, false);
1191                 break;
1192
1193         default:
1194                 retval = -EINVAL;
1195         }
1196         return retval;
1197 }
1198
1199 /*
1200  * ALSA PCM prepare callback
1201  */
1202 static int had_pcm_prepare(struct snd_pcm_substream *substream)
1203 {
1204         int retval;
1205         u32 disp_samp_freq, n_param;
1206         u32 link_rate = 0;
1207         struct snd_intelhad *intelhaddata;
1208         struct snd_pcm_runtime *runtime;
1209
1210         intelhaddata = snd_pcm_substream_chip(substream);
1211         runtime = substream->runtime;
1212
1213         if (!intelhaddata->connected) {
1214                 dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n",
1215                         __func__);
1216                 retval = -ENODEV;
1217                 goto prep_end;
1218         }
1219
1220         dev_dbg(intelhaddata->dev, "period_size=%d\n",
1221                 (int)frames_to_bytes(runtime, runtime->period_size));
1222         dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods);
1223         dev_dbg(intelhaddata->dev, "buffer_size=%d\n",
1224                 (int)snd_pcm_lib_buffer_bytes(substream));
1225         dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate);
1226         dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels);
1227
1228         /* Get N value in KHz */
1229         disp_samp_freq = intelhaddata->tmds_clock_speed;
1230
1231         retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1232         if (retval) {
1233                 dev_err(intelhaddata->dev,
1234                         "programming N value failed %#x\n", retval);
1235                 goto prep_end;
1236         }
1237
1238         if (intelhaddata->dp_output)
1239                 link_rate = intelhaddata->link_rate;
1240
1241         had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1242                      n_param, intelhaddata);
1243
1244         had_prog_dip(substream, intelhaddata);
1245
1246         retval = had_init_audio_ctrl(substream, intelhaddata);
1247
1248         /* Prog buffer address */
1249         had_init_ringbuf(substream, intelhaddata);
1250
1251         /*
1252          * Program channel mapping in following order:
1253          * FL, FR, C, LFE, RL, RR
1254          */
1255
1256         had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
1257
1258 prep_end:
1259         return retval;
1260 }
1261
1262 /*
1263  * ALSA PCM pointer callback
1264  */
1265 static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream)
1266 {
1267         struct snd_intelhad *intelhaddata;
1268         int len;
1269
1270         intelhaddata = snd_pcm_substream_chip(substream);
1271
1272         if (!intelhaddata->connected)
1273                 return SNDRV_PCM_POS_XRUN;
1274
1275         len = had_process_ringbuf(substream, intelhaddata);
1276         if (len < 0)
1277                 return SNDRV_PCM_POS_XRUN;
1278         return bytes_to_frames(substream->runtime, len);
1279 }
1280
1281 /*
1282  * ALSA PCM mmap callback
1283  */
1284 static int had_pcm_mmap(struct snd_pcm_substream *substream,
1285                         struct vm_area_struct *vma)
1286 {
1287         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1288         return remap_pfn_range(vma, vma->vm_start,
1289                         substream->dma_buffer.addr >> PAGE_SHIFT,
1290                         vma->vm_end - vma->vm_start, vma->vm_page_prot);
1291 }
1292
1293 /*
1294  * ALSA PCM ops
1295  */
1296 static const struct snd_pcm_ops had_pcm_ops = {
1297         .open =         had_pcm_open,
1298         .close =        had_pcm_close,
1299         .ioctl =        snd_pcm_lib_ioctl,
1300         .hw_params =    had_pcm_hw_params,
1301         .hw_free =      had_pcm_hw_free,
1302         .prepare =      had_pcm_prepare,
1303         .trigger =      had_pcm_trigger,
1304         .pointer =      had_pcm_pointer,
1305         .mmap =         had_pcm_mmap,
1306 };
1307
1308 /* process mode change of the running stream; called in mutex */
1309 static int had_process_mode_change(struct snd_intelhad *intelhaddata)
1310 {
1311         struct snd_pcm_substream *substream;
1312         int retval = 0;
1313         u32 disp_samp_freq, n_param;
1314         u32 link_rate = 0;
1315
1316         substream = had_substream_get(intelhaddata);
1317         if (!substream)
1318                 return 0;
1319
1320         /* Disable Audio */
1321         had_enable_audio(substream, intelhaddata, false);
1322
1323         /* Update CTS value */
1324         disp_samp_freq = intelhaddata->tmds_clock_speed;
1325
1326         retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1327         if (retval) {
1328                 dev_err(intelhaddata->dev,
1329                         "programming N value failed %#x\n", retval);
1330                 goto out;
1331         }
1332
1333         if (intelhaddata->dp_output)
1334                 link_rate = intelhaddata->link_rate;
1335
1336         had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1337                      n_param, intelhaddata);
1338
1339         /* Enable Audio */
1340         had_enable_audio(substream, intelhaddata, true);
1341
1342 out:
1343         had_substream_put(intelhaddata);
1344         return retval;
1345 }
1346
1347 /* process hot plug, called from wq with mutex locked */
1348 static void had_process_hot_plug(struct snd_intelhad *intelhaddata)
1349 {
1350         struct snd_pcm_substream *substream;
1351
1352         spin_lock_irq(&intelhaddata->had_spinlock);
1353         if (intelhaddata->connected) {
1354                 dev_dbg(intelhaddata->dev, "Device already connected\n");
1355                 spin_unlock_irq(&intelhaddata->had_spinlock);
1356                 return;
1357         }
1358
1359         intelhaddata->connected = true;
1360         dev_dbg(intelhaddata->dev,
1361                 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
1362                         __func__, __LINE__);
1363         spin_unlock_irq(&intelhaddata->had_spinlock);
1364
1365         /* Safety check */
1366         substream = had_substream_get(intelhaddata);
1367         if (substream) {
1368                 dev_dbg(intelhaddata->dev,
1369                         "Force to stop the active stream by disconnection\n");
1370                 /* Set runtime->state to hw_params done */
1371                 snd_pcm_stop(substream, SNDRV_PCM_STATE_SETUP);
1372                 had_substream_put(intelhaddata);
1373         }
1374
1375         had_build_channel_allocation_map(intelhaddata);
1376 }
1377
1378 /* process hot unplug, called from wq with mutex locked */
1379 static void had_process_hot_unplug(struct snd_intelhad *intelhaddata)
1380 {
1381         struct snd_pcm_substream *substream;
1382
1383         substream = had_substream_get(intelhaddata);
1384
1385         spin_lock_irq(&intelhaddata->had_spinlock);
1386
1387         if (!intelhaddata->connected) {
1388                 dev_dbg(intelhaddata->dev, "Device already disconnected\n");
1389                 spin_unlock_irq(&intelhaddata->had_spinlock);
1390                 goto out;
1391
1392         }
1393
1394         /* Disable Audio */
1395         had_enable_audio_int(intelhaddata, false);
1396         had_enable_audio(substream, intelhaddata, false);
1397
1398         intelhaddata->connected = false;
1399         dev_dbg(intelhaddata->dev,
1400                 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
1401                         __func__, __LINE__);
1402         spin_unlock_irq(&intelhaddata->had_spinlock);
1403
1404         /* Report to above ALSA layer */
1405         if (substream)
1406                 snd_pcm_stop(substream, SNDRV_PCM_STATE_SETUP);
1407
1408  out:
1409         if (substream)
1410                 had_substream_put(intelhaddata);
1411         kfree(intelhaddata->chmap->chmap);
1412         intelhaddata->chmap->chmap = NULL;
1413 }
1414
1415 /*
1416  * ALSA iec958 and ELD controls
1417  */
1418
1419 static int had_iec958_info(struct snd_kcontrol *kcontrol,
1420                                 struct snd_ctl_elem_info *uinfo)
1421 {
1422         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1423         uinfo->count = 1;
1424         return 0;
1425 }
1426
1427 static int had_iec958_get(struct snd_kcontrol *kcontrol,
1428                                 struct snd_ctl_elem_value *ucontrol)
1429 {
1430         struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1431
1432         mutex_lock(&intelhaddata->mutex);
1433         ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
1434         ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
1435         ucontrol->value.iec958.status[2] =
1436                                         (intelhaddata->aes_bits >> 16) & 0xff;
1437         ucontrol->value.iec958.status[3] =
1438                                         (intelhaddata->aes_bits >> 24) & 0xff;
1439         mutex_unlock(&intelhaddata->mutex);
1440         return 0;
1441 }
1442
1443 static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
1444                                 struct snd_ctl_elem_value *ucontrol)
1445 {
1446         ucontrol->value.iec958.status[0] = 0xff;
1447         ucontrol->value.iec958.status[1] = 0xff;
1448         ucontrol->value.iec958.status[2] = 0xff;
1449         ucontrol->value.iec958.status[3] = 0xff;
1450         return 0;
1451 }
1452
1453 static int had_iec958_put(struct snd_kcontrol *kcontrol,
1454                                 struct snd_ctl_elem_value *ucontrol)
1455 {
1456         unsigned int val;
1457         struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1458         int changed = 0;
1459
1460         val = (ucontrol->value.iec958.status[0] << 0) |
1461                 (ucontrol->value.iec958.status[1] << 8) |
1462                 (ucontrol->value.iec958.status[2] << 16) |
1463                 (ucontrol->value.iec958.status[3] << 24);
1464         mutex_lock(&intelhaddata->mutex);
1465         if (intelhaddata->aes_bits != val) {
1466                 intelhaddata->aes_bits = val;
1467                 changed = 1;
1468         }
1469         mutex_unlock(&intelhaddata->mutex);
1470         return changed;
1471 }
1472
1473 static int had_ctl_eld_info(struct snd_kcontrol *kcontrol,
1474                             struct snd_ctl_elem_info *uinfo)
1475 {
1476         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1477         uinfo->count = HDMI_MAX_ELD_BYTES;
1478         return 0;
1479 }
1480
1481 static int had_ctl_eld_get(struct snd_kcontrol *kcontrol,
1482                            struct snd_ctl_elem_value *ucontrol)
1483 {
1484         struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1485
1486         mutex_lock(&intelhaddata->mutex);
1487         memcpy(ucontrol->value.bytes.data, intelhaddata->eld,
1488                HDMI_MAX_ELD_BYTES);
1489         mutex_unlock(&intelhaddata->mutex);
1490         return 0;
1491 }
1492
1493 static const struct snd_kcontrol_new had_controls[] = {
1494         {
1495                 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1496                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1497                 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
1498                 .info = had_iec958_info, /* shared */
1499                 .get = had_iec958_mask_get,
1500         },
1501         {
1502                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1503                 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1504                 .info = had_iec958_info,
1505                 .get = had_iec958_get,
1506                 .put = had_iec958_put,
1507         },
1508         {
1509                 .access = (SNDRV_CTL_ELEM_ACCESS_READ |
1510                            SNDRV_CTL_ELEM_ACCESS_VOLATILE),
1511                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1512                 .name = "ELD",
1513                 .info = had_ctl_eld_info,
1514                 .get = had_ctl_eld_get,
1515         },
1516 };
1517
1518 /*
1519  * audio interrupt handler
1520  */
1521 static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
1522 {
1523         struct snd_intelhad *ctx = dev_id;
1524         u32 audio_stat, audio_reg;
1525
1526         audio_reg = AUD_HDMI_STATUS;
1527         had_read_register(ctx, audio_reg, &audio_stat);
1528
1529         if (audio_stat & HDMI_AUDIO_UNDERRUN) {
1530                 had_write_register(ctx, audio_reg, HDMI_AUDIO_UNDERRUN);
1531                 had_process_buffer_underrun(ctx);
1532         }
1533
1534         if (audio_stat & HDMI_AUDIO_BUFFER_DONE) {
1535                 had_write_register(ctx, audio_reg, HDMI_AUDIO_BUFFER_DONE);
1536                 had_process_buffer_done(ctx);
1537         }
1538
1539         return IRQ_HANDLED;
1540 }
1541
1542 /*
1543  * monitor plug/unplug notification from i915; just kick off the work
1544  */
1545 static void notify_audio_lpe(struct platform_device *pdev)
1546 {
1547         struct snd_intelhad *ctx = platform_get_drvdata(pdev);
1548
1549         schedule_work(&ctx->hdmi_audio_wq);
1550 }
1551
1552 /* the work to handle monitor hot plug/unplug */
1553 static void had_audio_wq(struct work_struct *work)
1554 {
1555         struct snd_intelhad *ctx =
1556                 container_of(work, struct snd_intelhad, hdmi_audio_wq);
1557         struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data;
1558
1559         pm_runtime_get_sync(ctx->dev);
1560         mutex_lock(&ctx->mutex);
1561         if (!pdata->hdmi_connected) {
1562                 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG\n",
1563                         __func__);
1564                 memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */
1565                 had_process_hot_unplug(ctx);
1566         } else {
1567                 struct intel_hdmi_lpe_audio_eld *eld = &pdata->eld;
1568
1569                 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
1570                         __func__, eld->port_id, pdata->tmds_clock_speed);
1571
1572                 switch (eld->pipe_id) {
1573                 case 0:
1574                         ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
1575                         break;
1576                 case 1:
1577                         ctx->had_config_offset = AUDIO_HDMI_CONFIG_B;
1578                         break;
1579                 case 2:
1580                         ctx->had_config_offset = AUDIO_HDMI_CONFIG_C;
1581                         break;
1582                 default:
1583                         dev_dbg(ctx->dev, "Invalid pipe %d\n",
1584                                 eld->pipe_id);
1585                         break;
1586                 }
1587
1588                 memcpy(ctx->eld, eld->eld_data, sizeof(ctx->eld));
1589
1590                 ctx->dp_output = pdata->dp_output;
1591                 ctx->tmds_clock_speed = pdata->tmds_clock_speed;
1592                 ctx->link_rate = pdata->link_rate;
1593
1594                 had_process_hot_plug(ctx);
1595
1596                 /* Process mode change if stream is active */
1597                 had_process_mode_change(ctx);
1598         }
1599         mutex_unlock(&ctx->mutex);
1600         pm_runtime_put(ctx->dev);
1601 }
1602
1603 /*
1604  * PM callbacks
1605  */
1606
1607 static int hdmi_lpe_audio_runtime_suspend(struct device *dev)
1608 {
1609         struct snd_intelhad *ctx = dev_get_drvdata(dev);
1610         struct snd_pcm_substream *substream;
1611
1612         substream = had_substream_get(ctx);
1613         if (substream) {
1614                 snd_pcm_suspend(substream);
1615                 had_substream_put(ctx);
1616         }
1617
1618         return 0;
1619 }
1620
1621 static int hdmi_lpe_audio_suspend(struct device *dev)
1622 {
1623         struct snd_intelhad *ctx = dev_get_drvdata(dev);
1624         int err;
1625
1626         err = hdmi_lpe_audio_runtime_suspend(dev);
1627         if (!err)
1628                 snd_power_change_state(ctx->card, SNDRV_CTL_POWER_D3hot);
1629         return err;
1630 }
1631
1632 static int hdmi_lpe_audio_resume(struct device *dev)
1633 {
1634         struct snd_intelhad *ctx = dev_get_drvdata(dev);
1635
1636         snd_power_change_state(ctx->card, SNDRV_CTL_POWER_D0);
1637         return 0;
1638 }
1639
1640 /* release resources */
1641 static void hdmi_lpe_audio_free(struct snd_card *card)
1642 {
1643         struct snd_intelhad *ctx = card->private_data;
1644
1645         cancel_work_sync(&ctx->hdmi_audio_wq);
1646
1647         if (ctx->mmio_start)
1648                 iounmap(ctx->mmio_start);
1649         if (ctx->irq >= 0)
1650                 free_irq(ctx->irq, ctx);
1651 }
1652
1653 /*
1654  * hdmi_lpe_audio_probe - start bridge with i915
1655  *
1656  * This function is called when the i915 driver creates the
1657  * hdmi-lpe-audio platform device.
1658  */
1659 static int hdmi_lpe_audio_probe(struct platform_device *pdev)
1660 {
1661         struct snd_card *card;
1662         struct snd_intelhad *ctx;
1663         struct snd_pcm *pcm;
1664         struct intel_hdmi_lpe_audio_pdata *pdata;
1665         int irq;
1666         struct resource *res_mmio;
1667         int i, ret;
1668
1669         pdata = pdev->dev.platform_data;
1670         if (!pdata) {
1671                 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
1672                 return -EINVAL;
1673         }
1674
1675         /* get resources */
1676         irq = platform_get_irq(pdev, 0);
1677         if (irq < 0) {
1678                 dev_err(&pdev->dev, "Could not get irq resource\n");
1679                 return -ENODEV;
1680         }
1681
1682         res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1683         if (!res_mmio) {
1684                 dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
1685                 return -ENXIO;
1686         }
1687
1688         /* create a card instance with ALSA framework */
1689         ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
1690                            THIS_MODULE, sizeof(*ctx), &card);
1691         if (ret)
1692                 return ret;
1693
1694         ctx = card->private_data;
1695         spin_lock_init(&ctx->had_spinlock);
1696         mutex_init(&ctx->mutex);
1697         ctx->connected = false;
1698         ctx->dev = &pdev->dev;
1699         ctx->card = card;
1700         ctx->aes_bits = SNDRV_PCM_DEFAULT_CON_SPDIF;
1701         strcpy(card->driver, INTEL_HAD);
1702         strcpy(card->shortname, INTEL_HAD);
1703
1704         ctx->irq = -1;
1705         ctx->tmds_clock_speed = DIS_SAMPLE_RATE_148_5;
1706         INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
1707
1708         card->private_free = hdmi_lpe_audio_free;
1709
1710         /* assume pipe A as default */
1711         ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
1712
1713         platform_set_drvdata(pdev, ctx);
1714
1715         dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
1716                 __func__, (unsigned int)res_mmio->start,
1717                 (unsigned int)res_mmio->end);
1718
1719         ctx->mmio_start = ioremap_nocache(res_mmio->start,
1720                                           (size_t)(resource_size(res_mmio)));
1721         if (!ctx->mmio_start) {
1722                 dev_err(&pdev->dev, "Could not get ioremap\n");
1723                 ret = -EACCES;
1724                 goto err;
1725         }
1726
1727         /* setup interrupt handler */
1728         ret = request_irq(irq, display_pipe_interrupt_handler, 0,
1729                           pdev->name, ctx);
1730         if (ret < 0) {
1731                 dev_err(&pdev->dev, "request_irq failed\n");
1732                 goto err;
1733         }
1734
1735         ctx->irq = irq;
1736
1737         ret = snd_pcm_new(card, INTEL_HAD, PCM_INDEX, MAX_PB_STREAMS,
1738                           MAX_CAP_STREAMS, &pcm);
1739         if (ret)
1740                 goto err;
1741
1742         /* setup private data which can be retrieved when required */
1743         pcm->private_data = ctx;
1744         pcm->info_flags = 0;
1745         strncpy(pcm->name, card->shortname, strlen(card->shortname));
1746         /* setup the ops for playabck */
1747         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops);
1748
1749         /* only 32bit addressable */
1750         dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1751         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1752
1753         /* allocate dma pages;
1754          * try to allocate 600k buffer as default which is large enough
1755          */
1756         snd_pcm_lib_preallocate_pages_for_all(pcm,
1757                         SNDRV_DMA_TYPE_DEV, NULL,
1758                         HAD_DEFAULT_BUFFER, HAD_MAX_BUFFER);
1759
1760         /* create controls */
1761         for (i = 0; i < ARRAY_SIZE(had_controls); i++) {
1762                 ret = snd_ctl_add(card, snd_ctl_new1(&had_controls[i], ctx));
1763                 if (ret < 0)
1764                         goto err;
1765         }
1766
1767         init_channel_allocations();
1768
1769         /* Register channel map controls */
1770         ret = had_register_chmap_ctls(ctx, pcm);
1771         if (ret < 0)
1772                 goto err;
1773
1774         ret = snd_card_register(card);
1775         if (ret)
1776                 goto err;
1777
1778         spin_lock_irq(&pdata->lpe_audio_slock);
1779         pdata->notify_audio_lpe = notify_audio_lpe;
1780         pdata->notify_pending = false;
1781         spin_unlock_irq(&pdata->lpe_audio_slock);
1782
1783         pm_runtime_set_active(&pdev->dev);
1784         pm_runtime_enable(&pdev->dev);
1785
1786         dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
1787         schedule_work(&ctx->hdmi_audio_wq);
1788
1789         return 0;
1790
1791 err:
1792         snd_card_free(card);
1793         return ret;
1794 }
1795
1796 /*
1797  * hdmi_lpe_audio_remove - stop bridge with i915
1798  *
1799  * This function is called when the platform device is destroyed.
1800  */
1801 static int hdmi_lpe_audio_remove(struct platform_device *pdev)
1802 {
1803         struct snd_intelhad *ctx = platform_get_drvdata(pdev);
1804
1805         if (ctx->connected)
1806                 had_enable_audio_int(ctx, false);
1807         snd_card_free(ctx->card);
1808         return 0;
1809 }
1810
1811 static const struct dev_pm_ops hdmi_lpe_audio_pm = {
1812         SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume)
1813         SET_RUNTIME_PM_OPS(hdmi_lpe_audio_runtime_suspend, NULL, NULL)
1814 };
1815
1816 static struct platform_driver hdmi_lpe_audio_driver = {
1817         .driver         = {
1818                 .name  = "hdmi-lpe-audio",
1819                 .pm = &hdmi_lpe_audio_pm,
1820         },
1821         .probe          = hdmi_lpe_audio_probe,
1822         .remove         = hdmi_lpe_audio_remove,
1823 };
1824
1825 module_platform_driver(hdmi_lpe_audio_driver);
1826 MODULE_ALIAS("platform:hdmi_lpe_audio");
1827
1828 MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
1829 MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
1830 MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
1831 MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
1832 MODULE_DESCRIPTION("Intel HDMI Audio driver");
1833 MODULE_LICENSE("GPL v2");
1834 MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}");