sound/x86/intel_hdmi_audio.c

   1 /*
   2  *   intel_hdmi_audio.c - Intel HDMI audio driver
   3  *
   4  *  Copyright (C) 2016 Intel Corp
   5  *  Authors:    Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
   6  *              Ramesh Babu K V <ramesh.babu@intel.com>
   7  *              Vaibhav Agarwal <vaibhav.agarwal@intel.com>
   8  *              Jerome Anand <jerome.anand@intel.com>
   9  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; version 2 of the License.
  14  *
  15  *  This program is distributed in the hope that it will be useful, but
  16  *  WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  *  General Public License for more details.
  19  *
  20  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  21  * ALSA driver for Intel HDMI audio
  22  */
  23
  24 #include <linux/types.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/io.h>
  27 #include <linux/slab.h>
  28 #include <linux/module.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/dma-mapping.h>
  32 #include <asm/cacheflush.h>
  33 #include <sound/core.h>
  34 #include <sound/asoundef.h>
  35 #include <sound/pcm.h>
  36 #include <sound/pcm_params.h>
  37 #include <sound/initval.h>
  38 #include <sound/control.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/intel_lpe_audio.h>
  41 #include "intel_hdmi_audio.h"
  42
  43 /*standard module options for ALSA. This module supports only one card*/
  44 static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
  45 static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
  46
  47 module_param_named(index, hdmi_card_index, int, 0444);
  48 MODULE_PARM_DESC(index,
  49                 "Index value for INTEL Intel HDMI Audio controller.");
  50 module_param_named(id, hdmi_card_id, charp, 0444);
  51 MODULE_PARM_DESC(id,
  52                 "ID string for INTEL Intel HDMI Audio controller.");
  53
  54 /*
  55  * ELD SA bits in the CEA Speaker Allocation data block
  56  */
  57 static const int eld_speaker_allocation_bits[] = {
  58         [0] = FL | FR,
  59         [1] = LFE,
  60         [2] = FC,
  61         [3] = RL | RR,
  62         [4] = RC,
  63         [5] = FLC | FRC,
  64         [6] = RLC | RRC,
  65         /* the following are not defined in ELD yet */
  66         [7] = 0,
  67 };
  68
  69 /*
  70  * This is an ordered list!
  71  *
  72  * The preceding ones have better chances to be selected by
  73  * hdmi_channel_allocation().
  74  */
  75 static struct cea_channel_speaker_allocation channel_allocations[] = {
  76 /*                        channel:   7     6    5    4    3     2    1    0  */
  77 { .ca_index = 0x00,  .speakers = {   0,    0,   0,   0,   0,    0,  FR,  FL } },
  78                                 /* 2.1 */
  79 { .ca_index = 0x01,  .speakers = {   0,    0,   0,   0,   0,  LFE,  FR,  FL } },
  80                                 /* Dolby Surround */
  81 { .ca_index = 0x02,  .speakers = {   0,    0,   0,   0,  FC,    0,  FR,  FL } },
  82                                 /* surround40 */
  83 { .ca_index = 0x08,  .speakers = {   0,    0,  RR,  RL,   0,    0,  FR,  FL } },
  84                                 /* surround41 */
  85 { .ca_index = 0x09,  .speakers = {   0,    0,  RR,  RL,   0,  LFE,  FR,  FL } },
  86                                 /* surround50 */
  87 { .ca_index = 0x0a,  .speakers = {   0,    0,  RR,  RL,  FC,    0,  FR,  FL } },
  88                                 /* surround51 */
  89 { .ca_index = 0x0b,  .speakers = {   0,    0,  RR,  RL,  FC,  LFE,  FR,  FL } },
  90                                 /* 6.1 */
  91 { .ca_index = 0x0f,  .speakers = {   0,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
  92                                 /* surround71 */
  93 { .ca_index = 0x13,  .speakers = { RRC,  RLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
  94
  95 { .ca_index = 0x03,  .speakers = {   0,    0,   0,   0,  FC,  LFE,  FR,  FL } },
  96 { .ca_index = 0x04,  .speakers = {   0,    0,   0,  RC,   0,    0,  FR,  FL } },
  97 { .ca_index = 0x05,  .speakers = {   0,    0,   0,  RC,   0,  LFE,  FR,  FL } },
  98 { .ca_index = 0x06,  .speakers = {   0,    0,   0,  RC,  FC,    0,  FR,  FL } },
  99 { .ca_index = 0x07,  .speakers = {   0,    0,   0,  RC,  FC,  LFE,  FR,  FL } },
 100 { .ca_index = 0x0c,  .speakers = {   0,   RC,  RR,  RL,   0,    0,  FR,  FL } },
 101 { .ca_index = 0x0d,  .speakers = {   0,   RC,  RR,  RL,   0,  LFE,  FR,  FL } },
 102 { .ca_index = 0x0e,  .speakers = {   0,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
 103 { .ca_index = 0x10,  .speakers = { RRC,  RLC,  RR,  RL,   0,    0,  FR,  FL } },
 104 { .ca_index = 0x11,  .speakers = { RRC,  RLC,  RR,  RL,   0,  LFE,  FR,  FL } },
 105 { .ca_index = 0x12,  .speakers = { RRC,  RLC,  RR,  RL,  FC,    0,  FR,  FL } },
 106 { .ca_index = 0x14,  .speakers = { FRC,  FLC,   0,   0,   0,    0,  FR,  FL } },
 107 { .ca_index = 0x15,  .speakers = { FRC,  FLC,   0,   0,   0,  LFE,  FR,  FL } },
 108 { .ca_index = 0x16,  .speakers = { FRC,  FLC,   0,   0,  FC,    0,  FR,  FL } },
 109 { .ca_index = 0x17,  .speakers = { FRC,  FLC,   0,   0,  FC,  LFE,  FR,  FL } },
 110 { .ca_index = 0x18,  .speakers = { FRC,  FLC,   0,  RC,   0,    0,  FR,  FL } },
 111 { .ca_index = 0x19,  .speakers = { FRC,  FLC,   0,  RC,   0,  LFE,  FR,  FL } },
 112 { .ca_index = 0x1a,  .speakers = { FRC,  FLC,   0,  RC,  FC,    0,  FR,  FL } },
 113 { .ca_index = 0x1b,  .speakers = { FRC,  FLC,   0,  RC,  FC,  LFE,  FR,  FL } },
 114 { .ca_index = 0x1c,  .speakers = { FRC,  FLC,  RR,  RL,   0,    0,  FR,  FL } },
 115 { .ca_index = 0x1d,  .speakers = { FRC,  FLC,  RR,  RL,   0,  LFE,  FR,  FL } },
 116 { .ca_index = 0x1e,  .speakers = { FRC,  FLC,  RR,  RL,  FC,    0,  FR,  FL } },
 117 { .ca_index = 0x1f,  .speakers = { FRC,  FLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 118 };
 119
 120 static const struct channel_map_table map_tables[] = {
 121         { SNDRV_CHMAP_FL,       0x00,   FL },
 122         { SNDRV_CHMAP_FR,       0x01,   FR },
 123         { SNDRV_CHMAP_RL,       0x04,   RL },
 124         { SNDRV_CHMAP_RR,       0x05,   RR },
 125         { SNDRV_CHMAP_LFE,      0x02,   LFE },
 126         { SNDRV_CHMAP_FC,       0x03,   FC },
 127         { SNDRV_CHMAP_RLC,      0x06,   RLC },
 128         { SNDRV_CHMAP_RRC,      0x07,   RRC },
 129         {} /* terminator */
 130 };
 131
 132 /* hardware capability structure */
 133 static const struct snd_pcm_hardware had_pcm_hardware = {
 134         .info = (SNDRV_PCM_INFO_INTERLEAVED |
 135                 SNDRV_PCM_INFO_DOUBLE |
 136                 SNDRV_PCM_INFO_MMAP|
 137                 SNDRV_PCM_INFO_MMAP_VALID |
 138                 SNDRV_PCM_INFO_BATCH),
 139         .formats = SNDRV_PCM_FMTBIT_S24,
 140         .rates = SNDRV_PCM_RATE_32000 |
 141                 SNDRV_PCM_RATE_44100 |
 142                 SNDRV_PCM_RATE_48000 |
 143                 SNDRV_PCM_RATE_88200 |
 144                 SNDRV_PCM_RATE_96000 |
 145                 SNDRV_PCM_RATE_176400 |
 146                 SNDRV_PCM_RATE_192000,
 147         .rate_min = HAD_MIN_RATE,
 148         .rate_max = HAD_MAX_RATE,
 149         .channels_min = HAD_MIN_CHANNEL,
 150         .channels_max = HAD_MAX_CHANNEL,
 151         .buffer_bytes_max = HAD_MAX_BUFFER,
 152         .period_bytes_min = HAD_MIN_PERIOD_BYTES,
 153         .period_bytes_max = HAD_MAX_PERIOD_BYTES,
 154         .periods_min = HAD_MIN_PERIODS,
 155         .periods_max = HAD_MAX_PERIODS,
 156         .fifo_size = HAD_FIFO_SIZE,
 157 };
 158
 159 /* Get the active PCM substream;
 160  * Call had_substream_put() for unreferecing.
 161  * Don't call this inside had_spinlock, as it takes by itself
 162  */
 163 static struct snd_pcm_substream *
 164 had_substream_get(struct snd_intelhad *intelhaddata)
 165 {
 166         struct snd_pcm_substream *substream;
 167         unsigned long flags;
 168
 169         spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
 170         substream = intelhaddata->stream_info.substream;
 171         if (substream)
 172                 intelhaddata->stream_info.substream_refcount++;
 173         spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
 174         return substream;
 175 }
 176
 177 /* Unref the active PCM substream;
 178  * Don't call this inside had_spinlock, as it takes by itself
 179  */
 180 static void had_substream_put(struct snd_intelhad *intelhaddata)
 181 {
 182         unsigned long flags;
 183
 184         spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
 185         intelhaddata->stream_info.substream_refcount--;
 186         spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
 187 }
 188
 189 /* Register access functions */
 190 static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val)
 191 {
 192         *val = ioread32(ctx->mmio_start + ctx->had_config_offset + reg);
 193 }
 194
 195 static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val)
 196 {
 197         iowrite32(val, ctx->mmio_start + ctx->had_config_offset + reg);
 198 }
 199
 200 /*
 201  * enable / disable audio configuration
 202  *
 203  * The normal read/modify should not directly be used on VLV2 for
 204  * updating AUD_CONFIG register.
 205  * This is because:
 206  * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2
 207  * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always
 208  * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the
 209  * register. This field should be 1xy binary for configuration with 6 or
 210  * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio)
 211  * causes the "channels" field to be updated as 0xy binary resulting in
 212  * bad audio. The fix is to always write the AUD_CONFIG[6:4] with
 213  * appropriate value when doing read-modify of AUD_CONFIG register.
 214  */
 215 static void had_enable_audio(struct snd_pcm_substream *substream,
 216                              struct snd_intelhad *intelhaddata,
 217                              bool enable)
 218 {
 219         union aud_cfg cfg_val = {.regval = 0};
 220         u8 channels;
 221         u32 mask, val;
 222
 223         /*
 224          * If substream is NULL, there is no active stream.
 225          * In this case just set channels to 2
 226          */
 227         channels = substream ? substream->runtime->channels : 2;
 228         dev_dbg(intelhaddata->dev, "enable %d, ch=%d\n", enable, channels);
 229
 230         cfg_val.regx.num_ch = channels - 2;
 231         if (enable)
 232                 cfg_val.regx.aud_en = 1;
 233         mask = AUD_CONFIG_CH_MASK | 1;
 234
 235         had_read_register(intelhaddata, AUD_CONFIG, &val);
 236         val &= ~mask;
 237         val |= cfg_val.regval;
 238         had_write_register(intelhaddata, AUD_CONFIG, val);
 239 }
 240
 241 /* forcibly ACKs to both BUFFER_DONE and BUFFER_UNDERRUN interrupts */
 242 static void had_ack_irqs(struct snd_intelhad *ctx)
 243 {
 244         u32 status_reg;
 245
 246         had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
 247         status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
 248         had_write_register(ctx, AUD_HDMI_STATUS, status_reg);
 249         had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
 250 }
 251
 252 /* Reset buffer pointers */
 253 static void had_reset_audio(struct snd_intelhad *intelhaddata)
 254 {
 255         had_write_register(intelhaddata, AUD_HDMI_STATUS, 1);
 256         had_write_register(intelhaddata, AUD_HDMI_STATUS, 0);
 257 }
 258
 259 /*
 260  * initialize audio channel status registers
 261  * This function is called in the prepare callback
 262  */
 263 static int had_prog_status_reg(struct snd_pcm_substream *substream,
 264                         struct snd_intelhad *intelhaddata)
 265 {
 266         union aud_cfg cfg_val = {.regval = 0};
 267         union aud_ch_status_0 ch_stat0 = {.regval = 0};
 268         union aud_ch_status_1 ch_stat1 = {.regval = 0};
 269         int format;
 270
 271         ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits &
 272                                           IEC958_AES0_NONAUDIO) >> 1;
 273         ch_stat0.regx.clk_acc = (intelhaddata->aes_bits &
 274                                           IEC958_AES3_CON_CLOCK) >> 4;
 275         cfg_val.regx.val_bit = ch_stat0.regx.lpcm_id;
 276
 277         switch (substream->runtime->rate) {
 278         case AUD_SAMPLE_RATE_32:
 279                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ;
 280                 break;
 281
 282         case AUD_SAMPLE_RATE_44_1:
 283                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ;
 284                 break;
 285         case AUD_SAMPLE_RATE_48:
 286                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ;
 287                 break;
 288         case AUD_SAMPLE_RATE_88_2:
 289                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ;
 290                 break;
 291         case AUD_SAMPLE_RATE_96:
 292                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ;
 293                 break;
 294         case AUD_SAMPLE_RATE_176_4:
 295                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ;
 296                 break;
 297         case AUD_SAMPLE_RATE_192:
 298                 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ;
 299                 break;
 300
 301         default:
 302                 /* control should never come here */
 303                 return -EINVAL;
 304         }
 305
 306         had_write_register(intelhaddata,
 307                            AUD_CH_STATUS_0, ch_stat0.regval);
 308
 309         format = substream->runtime->format;
 310
 311         if (format == SNDRV_PCM_FORMAT_S16_LE) {
 312                 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20;
 313                 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS;
 314         } else if (format == SNDRV_PCM_FORMAT_S24_LE) {
 315                 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24;
 316                 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS;
 317         } else {
 318                 ch_stat1.regx.max_wrd_len = 0;
 319                 ch_stat1.regx.wrd_len = 0;
 320         }
 321
 322         had_write_register(intelhaddata,
 323                            AUD_CH_STATUS_1, ch_stat1.regval);
 324         return 0;
 325 }
 326
 327 /*
 328  * function to initialize audio
 329  * registers and buffer confgiuration registers
 330  * This function is called in the prepare callback
 331  */
 332 static int had_init_audio_ctrl(struct snd_pcm_substream *substream,
 333                                struct snd_intelhad *intelhaddata)
 334 {
 335         union aud_cfg cfg_val = {.regval = 0};
 336         union aud_buf_config buf_cfg = {.regval = 0};
 337         u8 channels;
 338
 339         had_prog_status_reg(substream, intelhaddata);
 340
 341         buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD;
 342         buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
 343         buf_cfg.regx.aud_delay = 0;
 344         had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval);
 345
 346         channels = substream->runtime->channels;
 347         cfg_val.regx.num_ch = channels - 2;
 348         if (channels <= 2)
 349                 cfg_val.regx.layout = LAYOUT0;
 350         else
 351                 cfg_val.regx.layout = LAYOUT1;
 352
 353         cfg_val.regx.val_bit = 1;
 354
 355         /* fix up the DP bits */
 356         if (intelhaddata->dp_output) {
 357                 cfg_val.regx.dp_modei = 1;
 358                 cfg_val.regx.set = 1;
 359         }
 360
 361         had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval);
 362         return 0;
 363 }
 364
 365 /*
 366  * Compute derived values in channel_allocations[].
 367  */
 368 static void init_channel_allocations(void)
 369 {
 370         int i, j;
 371         struct cea_channel_speaker_allocation *p;
 372
 373         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 374                 p = channel_allocations + i;
 375                 p->channels = 0;
 376                 p->spk_mask = 0;
 377                 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
 378                         if (p->speakers[j]) {
 379                                 p->channels++;
 380                                 p->spk_mask |= p->speakers[j];
 381                         }
 382         }
 383 }
 384
 385 /*
 386  * The transformation takes two steps:
 387  *
 388  *      eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
 389  *            spk_mask => (channel_allocations[])         => ai->CA
 390  *
 391  * TODO: it could select the wrong CA from multiple candidates.
 392  */
 393 static int had_channel_allocation(struct snd_intelhad *intelhaddata,
 394                                   int channels)
 395 {
 396         int i;
 397         int ca = 0;
 398         int spk_mask = 0;
 399
 400         /*
 401          * CA defaults to 0 for basic stereo audio
 402          */
 403         if (channels <= 2)
 404                 return 0;
 405
 406         /*
 407          * expand ELD's speaker allocation mask
 408          *
 409          * ELD tells the speaker mask in a compact(paired) form,
 410          * expand ELD's notions to match the ones used by Audio InfoFrame.
 411          */
 412
 413         for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
 414                 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
 415                         spk_mask |= eld_speaker_allocation_bits[i];
 416         }
 417
 418         /* search for the first working match in the CA table */
 419         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 420                 if (channels == channel_allocations[i].channels &&
 421                 (spk_mask & channel_allocations[i].spk_mask) ==
 422                                 channel_allocations[i].spk_mask) {
 423                         ca = channel_allocations[i].ca_index;
 424                         break;
 425                 }
 426         }
 427
 428         dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels);
 429
 430         return ca;
 431 }
 432
 433 /* from speaker bit mask to ALSA API channel position */
 434 static int spk_to_chmap(int spk)
 435 {
 436         const struct channel_map_table *t = map_tables;
 437
 438         for (; t->map; t++) {
 439                 if (t->spk_mask == spk)
 440                         return t->map;
 441         }
 442         return 0;
 443 }
 444
 445 static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
 446 {
 447         int i, c;
 448         int spk_mask = 0;
 449         struct snd_pcm_chmap_elem *chmap;
 450         u8 eld_high, eld_high_mask = 0xF0;
 451         u8 high_msb;
 452
 453         chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
 454         if (!chmap) {
 455                 intelhaddata->chmap->chmap = NULL;
 456                 return;
 457         }
 458
 459         dev_dbg(intelhaddata->dev, "eld speaker = %x\n",
 460                 intelhaddata->eld[DRM_ELD_SPEAKER]);
 461
 462         /* WA: Fix the max channel supported to 8 */
 463
 464         /*
 465          * Sink may support more than 8 channels, if eld_high has more than
 466          * one bit set. SOC supports max 8 channels.
 467          * Refer eld_speaker_allocation_bits, for sink speaker allocation
 468          */
 469
 470         /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */
 471         eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask;
 472         if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
 473                 /* eld_high & (eld_high-1): if more than 1 bit set */
 474                 /* 0x1F: 7 channels */
 475                 for (i = 1; i < 4; i++) {
 476                         high_msb = eld_high & (0x80 >> i);
 477                         if (high_msb) {
 478                                 intelhaddata->eld[DRM_ELD_SPEAKER] &=
 479                                         high_msb | 0xF;
 480                                 break;
 481                         }
 482                 }
 483         }
 484
 485         for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
 486                 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
 487                         spk_mask |= eld_speaker_allocation_bits[i];
 488         }
 489
 490         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 491                 if (spk_mask == channel_allocations[i].spk_mask) {
 492                         for (c = 0; c < channel_allocations[i].channels; c++) {
 493                                 chmap->map[c] = spk_to_chmap(
 494                                         channel_allocations[i].speakers[
 495                                                 (MAX_SPEAKERS - 1) - c]);
 496                         }
 497                         chmap->channels = channel_allocations[i].channels;
 498                         intelhaddata->chmap->chmap = chmap;
 499                         break;
 500                 }
 501         }
 502         if (i >= ARRAY_SIZE(channel_allocations)) {
 503                 intelhaddata->chmap->chmap = NULL;
 504                 kfree(chmap);
 505         }
 506 }
 507
 508 /*
 509  * ALSA API channel-map control callbacks
 510  */
 511 static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
 512                                 struct snd_ctl_elem_info *uinfo)
 513 {
 514         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
 515         struct snd_intelhad *intelhaddata = info->private_data;
 516
 517         if (!intelhaddata->connected)
 518                 return -ENODEV;
 519         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 520         uinfo->count = HAD_MAX_CHANNEL;
 521         uinfo->value.integer.min = 0;
 522         uinfo->value.integer.max = SNDRV_CHMAP_LAST;
 523         return 0;
 524 }
 525
 526 static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
 527                                 struct snd_ctl_elem_value *ucontrol)
 528 {
 529         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
 530         struct snd_intelhad *intelhaddata = info->private_data;
 531         int i;
 532         const struct snd_pcm_chmap_elem *chmap;
 533
 534         if (!intelhaddata->connected)
 535                 return -ENODEV;
 536
 537         mutex_lock(&intelhaddata->mutex);
 538         if (!intelhaddata->chmap->chmap) {
 539                 mutex_unlock(&intelhaddata->mutex);
 540                 return -ENODATA;
 541         }
 542
 543         chmap = intelhaddata->chmap->chmap;
 544         for (i = 0; i < chmap->channels; i++)
 545                 ucontrol->value.integer.value[i] = chmap->map[i];
 546         mutex_unlock(&intelhaddata->mutex);
 547
 548         return 0;
 549 }
 550
 551 static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
 552                                                 struct snd_pcm *pcm)
 553 {
 554         int err;
 555
 556         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
 557                         NULL, 0, (unsigned long)intelhaddata,
 558                         &intelhaddata->chmap);
 559         if (err < 0)
 560                 return err;
 561
 562         intelhaddata->chmap->private_data = intelhaddata;
 563         intelhaddata->chmap->kctl->info = had_chmap_ctl_info;
 564         intelhaddata->chmap->kctl->get = had_chmap_ctl_get;
 565         intelhaddata->chmap->chmap = NULL;
 566         return 0;
 567 }
 568
 569 /*
 570  * Initialize Data Island Packets registers
 571  * This function is called in the prepare callback
 572  */
 573 static void had_prog_dip(struct snd_pcm_substream *substream,
 574                          struct snd_intelhad *intelhaddata)
 575 {
 576         int i;
 577         union aud_ctrl_st ctrl_state = {.regval = 0};
 578         union aud_info_frame2 frame2 = {.regval = 0};
 579         union aud_info_frame3 frame3 = {.regval = 0};
 580         u8 checksum = 0;
 581         u32 info_frame;
 582         int channels;
 583         int ca;
 584
 585         channels = substream->runtime->channels;
 586
 587         had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
 588
 589         ca = had_channel_allocation(intelhaddata, channels);
 590         if (intelhaddata->dp_output) {
 591                 info_frame = DP_INFO_FRAME_WORD1;
 592                 frame2.regval = (substream->runtime->channels - 1) | (ca << 24);
 593         } else {
 594                 info_frame = HDMI_INFO_FRAME_WORD1;
 595                 frame2.regx.chnl_cnt = substream->runtime->channels - 1;
 596                 frame3.regx.chnl_alloc = ca;
 597
 598                 /* Calculte the byte wide checksum for all valid DIP words */
 599                 for (i = 0; i < BYTES_PER_WORD; i++)
 600                         checksum += (info_frame >> (i * 8)) & 0xff;
 601                 for (i = 0; i < BYTES_PER_WORD; i++)
 602                         checksum += (frame2.regval >> (i * 8)) & 0xff;
 603                 for (i = 0; i < BYTES_PER_WORD; i++)
 604                         checksum += (frame3.regval >> (i * 8)) & 0xff;
 605
 606                 frame2.regx.chksum = -(checksum);
 607         }
 608
 609         had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame);
 610         had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval);
 611         had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval);
 612
 613         /* program remaining DIP words with zero */
 614         for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
 615                 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0);
 616
 617         ctrl_state.regx.dip_freq = 1;
 618         ctrl_state.regx.dip_en_sta = 1;
 619         had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
 620 }
 621
 622 static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
 623 {
 624         u32 maud_val;
 625
 626         /* Select maud according to DP 1.2 spec */
 627         if (link_rate == DP_2_7_GHZ) {
 628                 switch (aud_samp_freq) {
 629                 case AUD_SAMPLE_RATE_32:
 630                         maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
 631                         break;
 632
 633                 case AUD_SAMPLE_RATE_44_1:
 634                         maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
 635                         break;
 636
 637                 case AUD_SAMPLE_RATE_48:
 638                         maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
 639                         break;
 640
 641                 case AUD_SAMPLE_RATE_88_2:
 642                         maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
 643                         break;
 644
 645                 case AUD_SAMPLE_RATE_96:
 646                         maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
 647                         break;
 648
 649                 case AUD_SAMPLE_RATE_176_4:
 650                         maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
 651                         break;
 652
 653                 case HAD_MAX_RATE:
 654                         maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
 655                         break;
 656
 657                 default:
 658                         maud_val = -EINVAL;
 659                         break;
 660                 }
 661         } else if (link_rate == DP_1_62_GHZ) {
 662                 switch (aud_samp_freq) {
 663                 case AUD_SAMPLE_RATE_32:
 664                         maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
 665                         break;
 666
 667                 case AUD_SAMPLE_RATE_44_1:
 668                         maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
 669                         break;
 670
 671                 case AUD_SAMPLE_RATE_48:
 672                         maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
 673                         break;
 674
 675                 case AUD_SAMPLE_RATE_88_2:
 676                         maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
 677                         break;
 678
 679                 case AUD_SAMPLE_RATE_96:
 680                         maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
 681                         break;
 682
 683                 case AUD_SAMPLE_RATE_176_4:
 684                         maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
 685                         break;
 686
 687                 case HAD_MAX_RATE:
 688                         maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
 689                         break;
 690
 691                 default:
 692                         maud_val = -EINVAL;
 693                         break;
 694                 }
 695         } else
 696                 maud_val = -EINVAL;
 697
 698         return maud_val;
 699 }
 700
 701 /*
 702  * Program HDMI audio CTS value
 703  *
 704  * @aud_samp_freq: sampling frequency of audio data
 705  * @tmds: sampling frequency of the display data
 706  * @link_rate: DP link rate
 707  * @n_param: N value, depends on aud_samp_freq
 708  * @intelhaddata: substream private data
 709  *
 710  * Program CTS register based on the audio and display sampling frequency
 711  */
 712 static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate,
 713                          u32 n_param, struct snd_intelhad *intelhaddata)
 714 {
 715         u32 cts_val;
 716         u64 dividend, divisor;
 717
 718         if (intelhaddata->dp_output) {
 719                 /* Substitute cts_val with Maud according to DP 1.2 spec*/
 720                 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
 721         } else {
 722                 /* Calculate CTS according to HDMI 1.3a spec*/
 723                 dividend = (u64)tmds * n_param*1000;
 724                 divisor = 128 * aud_samp_freq;
 725                 cts_val = div64_u64(dividend, divisor);
 726         }
 727         dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n",
 728                  tmds, n_param, cts_val);
 729         had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
 730 }
 731
 732 static int had_calculate_n_value(u32 aud_samp_freq)
 733 {
 734         int n_val;
 735
 736         /* Select N according to HDMI 1.3a spec*/
 737         switch (aud_samp_freq) {
 738         case AUD_SAMPLE_RATE_32:
 739                 n_val = 4096;
 740                 break;
 741
 742         case AUD_SAMPLE_RATE_44_1:
 743                 n_val = 6272;
 744                 break;
 745
 746         case AUD_SAMPLE_RATE_48:
 747                 n_val = 6144;
 748                 break;
 749
 750         case AUD_SAMPLE_RATE_88_2:
 751                 n_val = 12544;
 752                 break;
 753
 754         case AUD_SAMPLE_RATE_96:
 755                 n_val = 12288;
 756                 break;
 757
 758         case AUD_SAMPLE_RATE_176_4:
 759                 n_val = 25088;
 760                 break;
 761
 762         case HAD_MAX_RATE:
 763                 n_val = 24576;
 764                 break;
 765
 766         default:
 767                 n_val = -EINVAL;
 768                 break;
 769         }
 770         return n_val;
 771 }
 772
 773 /*
 774  * Program HDMI audio N value
 775  *
 776  * @aud_samp_freq: sampling frequency of audio data
 777  * @n_param: N value, depends on aud_samp_freq
 778  * @intelhaddata: substream private data
 779  *
 780  * This function is called in the prepare callback.
 781  * It programs based on the audio and display sampling frequency
 782  */
 783 static int had_prog_n(u32 aud_samp_freq, u32 *n_param,
 784                       struct snd_intelhad *intelhaddata)
 785 {
 786         int n_val;
 787
 788         if (intelhaddata->dp_output) {
 789                 /*
 790                  * According to DP specs, Maud and Naud values hold
 791                  * a relationship, which is stated as:
 792                  * Maud/Naud = 512 * fs / f_LS_Clk
 793                  * where, fs is the sampling frequency of the audio stream
 794                  * and Naud is 32768 for Async clock.
 795                  */
 796
 797                 n_val = DP_NAUD_VAL;
 798         } else
 799                 n_val = had_calculate_n_value(aud_samp_freq);
 800
 801         if (n_val < 0)
 802                 return n_val;
 803
 804         had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
 805         *n_param = n_val;
 806         return 0;
 807 }
 808
 809 /*
 810  * PCM ring buffer handling
 811  *
 812  * The hardware provides a ring buffer with the fixed 4 buffer descriptors
 813  * (BDs).  The driver maps these 4 BDs onto the PCM ring buffer.  The mapping
 814  * moves at each period elapsed.  The below illustrates how it works:
 815  *
 816  * At time=0
 817  *  PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
 818  *  BD  | 0 | 1 | 2 | 3 |
 819  *
 820  * At time=1 (period elapsed)
 821  *  PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
 822  *  BD      | 1 | 2 | 3 | 0 |
 823  *
 824  * At time=2 (second period elapsed)
 825  *  PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
 826  *  BD          | 2 | 3 | 0 | 1 |
 827  *
 828  * The bd_head field points to the index of the BD to be read.  It's also the
 829  * position to be filled at next.  The pcm_head and the pcm_filled fields
 830  * point to the indices of the current position and of the next position to
 831  * be filled, respectively.  For PCM buffer there are both _head and _filled
 832  * because they may be difference when nperiods > 4.  For example, in the
 833  * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5:
 834  *
 835  * pcm_head (=1) --v               v-- pcm_filled (=5)
 836  *       PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
 837  *       BD      | 1 | 2 | 3 | 0 |
 838  *  bd_head (=1) --^               ^-- next to fill (= bd_head)
 839  *
 840  * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that
 841  * the hardware skips those BDs in the loop.
 842  */
 843
 844 #define AUD_BUF_ADDR(x)         (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH)
 845 #define AUD_BUF_LEN(x)          (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH)
 846
 847 /* Set up a buffer descriptor at the "filled" position */
 848 static void had_prog_bd(struct snd_pcm_substream *substream,
 849                         struct snd_intelhad *intelhaddata)
 850 {
 851         int idx = intelhaddata->bd_head;
 852         int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes;
 853         u32 addr = substream->runtime->dma_addr + ofs;
 854
 855         addr |= AUD_BUF_VALID | AUD_BUF_INTR_EN;
 856         had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr);
 857         had_write_register(intelhaddata, AUD_BUF_LEN(idx),
 858                            intelhaddata->period_bytes);
 859
 860         /* advance the indices to the next */
 861         intelhaddata->bd_head++;
 862         intelhaddata->bd_head %= intelhaddata->num_bds;
 863         intelhaddata->pcmbuf_filled++;
 864         intelhaddata->pcmbuf_filled %= substream->runtime->periods;
 865 }
 866
 867 /* invalidate a buffer descriptor with the given index */
 868 static void had_invalidate_bd(struct snd_intelhad *intelhaddata,
 869                               int idx)
 870 {
 871         had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0);
 872         had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0);
 873 }
 874
 875 /* Initial programming of ring buffer */
 876 static void had_init_ringbuf(struct snd_pcm_substream *substream,
 877                              struct snd_intelhad *intelhaddata)
 878 {
 879         struct snd_pcm_runtime *runtime = substream->runtime;
 880         int i, num_periods;
 881
 882         num_periods = runtime->periods;
 883         intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS);
 884         intelhaddata->period_bytes =
 885                 frames_to_bytes(runtime, runtime->period_size);
 886         WARN_ON(intelhaddata->period_bytes & 0x3f);
 887
 888         intelhaddata->bd_head = 0;
 889         intelhaddata->pcmbuf_head = 0;
 890         intelhaddata->pcmbuf_filled = 0;
 891
 892         for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) {
 893                 if (i < num_periods)
 894                         had_prog_bd(substream, intelhaddata);
 895                 else /* invalidate the rest */
 896                         had_invalidate_bd(intelhaddata, i);
 897         }
 898
 899         intelhaddata->bd_head = 0; /* reset at head again before starting */
 900 }
 901
 902 /* process a bd, advance to the next */
 903 static void had_advance_ringbuf(struct snd_pcm_substream *substream,
 904                                 struct snd_intelhad *intelhaddata)
 905 {
 906         int num_periods = substream->runtime->periods;
 907
 908         /* reprogram the next buffer */
 909         had_prog_bd(substream, intelhaddata);
 910
 911         /* proceed to next */
 912         intelhaddata->pcmbuf_head++;
 913         intelhaddata->pcmbuf_head %= num_periods;
 914 }
 915
 916 /* process the current BD(s);
 917  * returns the current PCM buffer byte position, or -EPIPE for underrun.
 918  */
 919 static int had_process_ringbuf(struct snd_pcm_substream *substream,
 920                                struct snd_intelhad *intelhaddata)
 921 {
 922         int len, processed;
 923         unsigned long flags;
 924
 925         processed = 0;
 926         spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
 927         for (;;) {
 928                 /* get the remaining bytes on the buffer */
 929                 had_read_register(intelhaddata,
 930                                   AUD_BUF_LEN(intelhaddata->bd_head),
 931                                   &len);
 932                 if (len < 0 || len > intelhaddata->period_bytes) {
 933                         dev_dbg(intelhaddata->dev, "Invalid buf length %d\n",
 934                                 len);
 935                         len = -EPIPE;
 936                         goto out;
 937                 }
 938
 939                 if (len > 0) /* OK, this is the current buffer */
 940                         break;
 941
 942                 /* len=0 => already empty, check the next buffer */
 943                 if (++processed >= intelhaddata->num_bds) {
 944                         len = -EPIPE; /* all empty? - report underrun */
 945                         goto out;
 946                 }
 947                 had_advance_ringbuf(substream, intelhaddata);
 948         }
 949
 950         len = intelhaddata->period_bytes - len;
 951         len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head;
 952  out:
 953         spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
 954         return len;
 955 }
 956
 957 /* called from irq handler */
 958 static void had_process_buffer_done(struct snd_intelhad *intelhaddata)
 959 {
 960         struct snd_pcm_substream *substream;
 961
 962         if (!intelhaddata->connected)
 963                 return; /* disconnected? - bail out */
 964
 965         substream = had_substream_get(intelhaddata);
 966         if (!substream)
 967                 return; /* no stream? - bail out */
 968
 969         /* process or stop the stream */
 970         if (had_process_ringbuf(substream, intelhaddata) < 0)
 971                 snd_pcm_stop_xrun(substream);
 972         else
 973                 snd_pcm_period_elapsed(substream);
 974
 975         had_substream_put(intelhaddata);
 976 }
 977
 978 #define MAX_CNT                 0xFF
 979
 980 /*
 981  * The interrupt status 'sticky' bits might not be cleared by
 982  * setting '1' to that bit once...
 983  */
 984 static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata)
 985 {
 986         int i;
 987         u32 val;
 988
 989         for (i = 0; i < MAX_CNT; i++) {
 990                 /* clear bit30, 31 AUD_HDMI_STATUS */
 991                 had_read_register(intelhaddata, AUD_HDMI_STATUS, &val);
 992                 if (!(val & AUD_CONFIG_MASK_UNDERRUN))
 993                         return;
 994                 had_write_register(intelhaddata, AUD_HDMI_STATUS, val);
 995         }
 996         dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n");
 997 }
 998
 999 /* called from irq handler */
1000 static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata)
1001 {
1002         struct snd_pcm_substream *substream;
1003
1004         /* Handle Underrun interrupt within Audio Unit */
1005         had_write_register(intelhaddata, AUD_CONFIG, 0);
1006         /* Reset buffer pointers */
1007         had_reset_audio(intelhaddata);
1008
1009         wait_clear_underrun_bit(intelhaddata);
1010
1011         if (!intelhaddata->connected)
1012                 return; /* disconnected? - bail out */
1013
1014         /* Report UNDERRUN error to above layers */
1015         substream = had_substream_get(intelhaddata);
1016         if (substream) {
1017                 snd_pcm_stop_xrun(substream);
1018                 had_substream_put(intelhaddata);
1019         }
1020 }
1021
1022 /*
1023  * ALSA PCM open callback
1024  */
1025 static int had_pcm_open(struct snd_pcm_substream *substream)
1026 {
1027         struct snd_intelhad *intelhaddata;
1028         struct snd_pcm_runtime *runtime;
1029         int retval;
1030
1031         intelhaddata = snd_pcm_substream_chip(substream);
1032         runtime = substream->runtime;
1033
1034         pm_runtime_get_sync(intelhaddata->dev);
1035
1036         if (!intelhaddata->connected) {
1037                 dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n",
1038                         __func__);
1039                 retval = -ENODEV;
1040                 goto error;
1041         }
1042
1043         /* set the runtime hw parameter with local snd_pcm_hardware struct */
1044         runtime->hw = had_pcm_hardware;
1045
1046         retval = snd_pcm_hw_constraint_integer(runtime,
1047                          SNDRV_PCM_HW_PARAM_PERIODS);
1048         if (retval < 0)
1049                 goto error;
1050
1051         /* Make sure, that the period size is always aligned
1052          * 64byte boundary
1053          */
1054         retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
1055                         SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
1056         if (retval < 0)
1057                 goto error;
1058
1059         /* expose PCM substream */
1060         spin_lock_irq(&intelhaddata->had_spinlock);
1061         intelhaddata->stream_info.substream = substream;
1062         intelhaddata->stream_info.substream_refcount++;
1063         spin_unlock_irq(&intelhaddata->had_spinlock);
1064
1065         return retval;
1066  error:
1067         pm_runtime_put(intelhaddata->dev);
1068         return retval;
1069 }
1070
1071 /*
1072  * ALSA PCM close callback
1073  */
1074 static int had_pcm_close(struct snd_pcm_substream *substream)
1075 {
1076         struct snd_intelhad *intelhaddata;
1077
1078         intelhaddata = snd_pcm_substream_chip(substream);
1079
1080         /* unreference and sync with the pending PCM accesses */
1081         spin_lock_irq(&intelhaddata->had_spinlock);
1082         intelhaddata->stream_info.substream = NULL;
1083         intelhaddata->stream_info.substream_refcount--;
1084         while (intelhaddata->stream_info.substream_refcount > 0) {
1085                 spin_unlock_irq(&intelhaddata->had_spinlock);
1086                 cpu_relax();
1087                 spin_lock_irq(&intelhaddata->had_spinlock);
1088         }
1089         spin_unlock_irq(&intelhaddata->had_spinlock);
1090
1091         pm_runtime_put(intelhaddata->dev);
1092         return 0;
1093 }
1094
1095 /*
1096  * ALSA PCM hw_params callback
1097  */
1098 static int had_pcm_hw_params(struct snd_pcm_substream *substream,
1099                              struct snd_pcm_hw_params *hw_params)
1100 {
1101         struct snd_intelhad *intelhaddata;
1102         unsigned long addr;
1103         int pages, buf_size, retval;
1104
1105         intelhaddata = snd_pcm_substream_chip(substream);
1106         buf_size = params_buffer_bytes(hw_params);
1107         retval = snd_pcm_lib_malloc_pages(substream, buf_size);
1108         if (retval < 0)
1109                 return retval;
1110         dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n",
1111                 __func__, buf_size);
1112         /* mark the pages as uncached region */
1113         addr = (unsigned long) substream->runtime->dma_area;
1114         pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / PAGE_SIZE;
1115         retval = set_memory_uc(addr, pages);
1116         if (retval) {
1117                 dev_err(intelhaddata->dev, "set_memory_uc failed.Error:%d\n",
1118                         retval);
1119                 return retval;
1120         }
1121         memset(substream->runtime->dma_area, 0, buf_size);
1122
1123         return retval;
1124 }
1125
1126 /*
1127  * ALSA PCM hw_free callback
1128  */
1129 static int had_pcm_hw_free(struct snd_pcm_substream *substream)
1130 {
1131         unsigned long addr;
1132         u32 pages;
1133
1134         /* mark back the pages as cached/writeback region before the free */
1135         if (substream->runtime->dma_area != NULL) {
1136                 addr = (unsigned long) substream->runtime->dma_area;
1137                 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) /
1138                                                                 PAGE_SIZE;
1139                 set_memory_wb(addr, pages);
1140                 return snd_pcm_lib_free_pages(substream);
1141         }
1142         return 0;
1143 }
1144
1145 /*
1146  * ALSA PCM trigger callback
1147  */
1148 static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1149 {
1150         int retval = 0;
1151         struct snd_intelhad *intelhaddata;
1152
1153         intelhaddata = snd_pcm_substream_chip(substream);
1154
1155         switch (cmd) {
1156         case SNDRV_PCM_TRIGGER_START:
1157         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1158         case SNDRV_PCM_TRIGGER_RESUME:
1159                 /* Disable local INTRs till register prgmng is done */
1160                 if (!intelhaddata->connected) {
1161                         dev_dbg(intelhaddata->dev,
1162                                 "_START: HDMI cable plugged-out\n");
1163                         retval = -ENODEV;
1164                         break;
1165                 }
1166
1167                 intelhaddata->stream_info.running = true;
1168
1169                 /* Enable Audio */
1170                 had_ack_irqs(intelhaddata); /* FIXME: do we need this? */
1171                 had_enable_audio(substream, intelhaddata, true);
1172                 break;
1173
1174         case SNDRV_PCM_TRIGGER_STOP:
1175         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1176         case SNDRV_PCM_TRIGGER_SUSPEND:
1177                 spin_lock(&intelhaddata->had_spinlock);
1178
1179                 /* Stop reporting BUFFER_DONE/UNDERRUN to above layers */
1180
1181                 intelhaddata->stream_info.running = false;
1182                 spin_unlock(&intelhaddata->had_spinlock);
1183                 /* Disable Audio */
1184                 had_enable_audio(substream, intelhaddata, false);
1185                 /* Reset buffer pointers */
1186                 had_reset_audio(intelhaddata);
1187                 break;
1188
1189         default:
1190                 retval = -EINVAL;
1191         }
1192         return retval;
1193 }
1194
1195 /*
1196  * ALSA PCM prepare callback
1197  */
1198 static int had_pcm_prepare(struct snd_pcm_substream *substream)
1199 {
1200         int retval;
1201         u32 disp_samp_freq, n_param;
1202         u32 link_rate = 0;
1203         struct snd_intelhad *intelhaddata;
1204         struct snd_pcm_runtime *runtime;
1205
1206         intelhaddata = snd_pcm_substream_chip(substream);
1207         runtime = substream->runtime;
1208
1209         if (!intelhaddata->connected) {
1210                 dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n",
1211                         __func__);
1212                 retval = -ENODEV;
1213                 goto prep_end;
1214         }
1215
1216         dev_dbg(intelhaddata->dev, "period_size=%d\n",
1217                 (int)frames_to_bytes(runtime, runtime->period_size));
1218         dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods);
1219         dev_dbg(intelhaddata->dev, "buffer_size=%d\n",
1220                 (int)snd_pcm_lib_buffer_bytes(substream));
1221         dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate);
1222         dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels);
1223
1224         /* Get N value in KHz */
1225         disp_samp_freq = intelhaddata->tmds_clock_speed;
1226
1227         retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1228         if (retval) {
1229                 dev_err(intelhaddata->dev,
1230                         "programming N value failed %#x\n", retval);
1231                 goto prep_end;
1232         }
1233
1234         if (intelhaddata->dp_output)
1235                 link_rate = intelhaddata->link_rate;
1236
1237         had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1238                      n_param, intelhaddata);
1239
1240         had_prog_dip(substream, intelhaddata);
1241
1242         retval = had_init_audio_ctrl(substream, intelhaddata);
1243
1244         /* Prog buffer address */
1245         had_init_ringbuf(substream, intelhaddata);
1246
1247         /*
1248          * Program channel mapping in following order:
1249          * FL, FR, C, LFE, RL, RR
1250          */
1251
1252         had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
1253
1254 prep_end:
1255         return retval;
1256 }
1257
1258 /*
1259  * ALSA PCM pointer callback
1260  */
1261 static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream)
1262 {
1263         struct snd_intelhad *intelhaddata;
1264         int len;
1265
1266         intelhaddata = snd_pcm_substream_chip(substream);
1267
1268         if (!intelhaddata->connected)
1269                 return SNDRV_PCM_POS_XRUN;
1270
1271         len = had_process_ringbuf(substream, intelhaddata);
1272         if (len < 0)
1273                 return SNDRV_PCM_POS_XRUN;
1274         return bytes_to_frames(substream->runtime, len);
1275 }
1276
1277 /*
1278  * ALSA PCM mmap callback
1279  */
1280 static int had_pcm_mmap(struct snd_pcm_substream *substream,
1281                         struct vm_area_struct *vma)
1282 {
1283         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1284         return remap_pfn_range(vma, vma->vm_start,
1285                         substream->dma_buffer.addr >> PAGE_SHIFT,
1286                         vma->vm_end - vma->vm_start, vma->vm_page_prot);
1287 }
1288
1289 /*
1290  * ALSA PCM ops
1291  */
1292 static const struct snd_pcm_ops had_pcm_ops = {
1293         .open =         had_pcm_open,
1294         .close =        had_pcm_close,
1295         .ioctl =        snd_pcm_lib_ioctl,
1296         .hw_params =    had_pcm_hw_params,
1297         .hw_free =      had_pcm_hw_free,
1298         .prepare =      had_pcm_prepare,
1299         .trigger =      had_pcm_trigger,
1300         .pointer =      had_pcm_pointer,
1301         .mmap =         had_pcm_mmap,
1302 };
1303
1304 /* process mode change of the running stream; called in mutex */
1305 static int had_process_mode_change(struct snd_intelhad *intelhaddata)
1306 {
1307         struct snd_pcm_substream *substream;
1308         int retval = 0;
1309         u32 disp_samp_freq, n_param;
1310         u32 link_rate = 0;
1311
1312         substream = had_substream_get(intelhaddata);
1313         if (!substream)
1314                 return 0;
1315
1316         /* Disable Audio */
1317         had_enable_audio(substream, intelhaddata, false);
1318
1319         /* Update CTS value */
1320         disp_samp_freq = intelhaddata->tmds_clock_speed;
1321
1322         retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1323         if (retval) {
1324                 dev_err(intelhaddata->dev,
1325                         "programming N value failed %#x\n", retval);
1326                 goto out;
1327         }
1328
1329         if (intelhaddata->dp_output)
1330                 link_rate = intelhaddata->link_rate;
1331
1332         had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1333                      n_param, intelhaddata);
1334
1335         /* Enable Audio */
1336         had_enable_audio(substream, intelhaddata, true);
1337
1338 out:
1339         had_substream_put(intelhaddata);
1340         return retval;
1341 }
1342
1343 /* process hot plug, called from wq with mutex locked */
1344 static void had_process_hot_plug(struct snd_intelhad *intelhaddata)
1345 {
1346         struct snd_pcm_substream *substream;
1347
1348         spin_lock_irq(&intelhaddata->had_spinlock);
1349         if (intelhaddata->connected) {
1350                 dev_dbg(intelhaddata->dev, "Device already connected\n");
1351                 spin_unlock_irq(&intelhaddata->had_spinlock);
1352                 return;
1353         }
1354
1355         intelhaddata->connected = true;
1356         dev_dbg(intelhaddata->dev,
1357                 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
1358                         __func__, __LINE__);
1359         spin_unlock_irq(&intelhaddata->had_spinlock);
1360
1361         /* Safety check */
1362         substream = had_substream_get(intelhaddata);
1363         if (substream) {
1364                 dev_dbg(intelhaddata->dev,
1365                         "Force to stop the active stream by disconnection\n");
1366                 /* Set runtime->state to hw_params done */
1367                 snd_pcm_stop(substream, SNDRV_PCM_STATE_SETUP);
1368                 had_substream_put(intelhaddata);
1369         }
1370
1371         had_build_channel_allocation_map(intelhaddata);
1372 }
1373
1374 /* process hot unplug, called from wq with mutex locked */
1375 static void had_process_hot_unplug(struct snd_intelhad *intelhaddata)
1376 {
1377         struct snd_pcm_substream *substream;
1378
1379         substream = had_substream_get(intelhaddata);
1380
1381         spin_lock_irq(&intelhaddata->had_spinlock);
1382
1383         if (!intelhaddata->connected) {
1384                 dev_dbg(intelhaddata->dev, "Device already disconnected\n");
1385                 spin_unlock_irq(&intelhaddata->had_spinlock);
1386                 goto out;
1387
1388         }
1389
1390         /* Disable Audio */
1391         had_enable_audio(substream, intelhaddata, false);
1392
1393         intelhaddata->connected = false;
1394         dev_dbg(intelhaddata->dev,
1395                 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
1396                         __func__, __LINE__);
1397         spin_unlock_irq(&intelhaddata->had_spinlock);
1398
1399         /* Report to above ALSA layer */
1400         if (substream)
1401                 snd_pcm_stop(substream, SNDRV_PCM_STATE_SETUP);
1402
1403  out:
1404         if (substream)
1405                 had_substream_put(intelhaddata);
1406         kfree(intelhaddata->chmap->chmap);
1407         intelhaddata->chmap->chmap = NULL;
1408 }
1409
1410 /*
1411  * ALSA iec958 and ELD controls
1412  */
1413
1414 static int had_iec958_info(struct snd_kcontrol *kcontrol,
1415                                 struct snd_ctl_elem_info *uinfo)
1416 {
1417         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1418         uinfo->count = 1;
1419         return 0;
1420 }
1421
1422 static int had_iec958_get(struct snd_kcontrol *kcontrol,
1423                                 struct snd_ctl_elem_value *ucontrol)
1424 {
1425         struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1426
1427         mutex_lock(&intelhaddata->mutex);
1428         ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
1429         ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
1430         ucontrol->value.iec958.status[2] =
1431                                         (intelhaddata->aes_bits >> 16) & 0xff;
1432         ucontrol->value.iec958.status[3] =
1433                                         (intelhaddata->aes_bits >> 24) & 0xff;
1434         mutex_unlock(&intelhaddata->mutex);
1435         return 0;
1436 }
1437
1438 static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
1439                                 struct snd_ctl_elem_value *ucontrol)
1440 {
1441         ucontrol->value.iec958.status[0] = 0xff;
1442         ucontrol->value.iec958.status[1] = 0xff;
1443         ucontrol->value.iec958.status[2] = 0xff;
1444         ucontrol->value.iec958.status[3] = 0xff;
1445         return 0;
1446 }
1447
1448 static int had_iec958_put(struct snd_kcontrol *kcontrol,
1449                                 struct snd_ctl_elem_value *ucontrol)
1450 {
1451         unsigned int val;
1452         struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1453         int changed = 0;
1454
1455         val = (ucontrol->value.iec958.status[0] << 0) |
1456                 (ucontrol->value.iec958.status[1] << 8) |
1457                 (ucontrol->value.iec958.status[2] << 16) |
1458                 (ucontrol->value.iec958.status[3] << 24);
1459         mutex_lock(&intelhaddata->mutex);
1460         if (intelhaddata->aes_bits != val) {
1461                 intelhaddata->aes_bits = val;
1462                 changed = 1;
1463         }
1464         mutex_unlock(&intelhaddata->mutex);
1465         return changed;
1466 }
1467
1468 static int had_ctl_eld_info(struct snd_kcontrol *kcontrol,
1469                             struct snd_ctl_elem_info *uinfo)
1470 {
1471         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1472         uinfo->count = HDMI_MAX_ELD_BYTES;
1473         return 0;
1474 }
1475
1476 static int had_ctl_eld_get(struct snd_kcontrol *kcontrol,
1477                            struct snd_ctl_elem_value *ucontrol)
1478 {
1479         struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1480
1481         mutex_lock(&intelhaddata->mutex);
1482         memcpy(ucontrol->value.bytes.data, intelhaddata->eld,
1483                HDMI_MAX_ELD_BYTES);
1484         mutex_unlock(&intelhaddata->mutex);
1485         return 0;
1486 }
1487
1488 static const struct snd_kcontrol_new had_controls[] = {
1489         {
1490                 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1491                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1492                 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
1493                 .info = had_iec958_info, /* shared */
1494                 .get = had_iec958_mask_get,
1495         },
1496         {
1497                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1498                 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1499                 .info = had_iec958_info,
1500                 .get = had_iec958_get,
1501                 .put = had_iec958_put,
1502         },
1503         {
1504                 .access = (SNDRV_CTL_ELEM_ACCESS_READ |
1505                            SNDRV_CTL_ELEM_ACCESS_VOLATILE),
1506                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1507                 .name = "ELD",
1508                 .info = had_ctl_eld_info,
1509                 .get = had_ctl_eld_get,
1510         },
1511 };
1512
1513 /*
1514  * audio interrupt handler
1515  */
1516 static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
1517 {
1518         struct snd_intelhad *ctx = dev_id;
1519         u32 audio_stat, audio_reg;
1520
1521         audio_reg = AUD_HDMI_STATUS;
1522         had_read_register(ctx, audio_reg, &audio_stat);
1523
1524         if (audio_stat & HDMI_AUDIO_UNDERRUN) {
1525                 had_write_register(ctx, audio_reg, HDMI_AUDIO_UNDERRUN);
1526                 had_process_buffer_underrun(ctx);
1527         }
1528
1529         if (audio_stat & HDMI_AUDIO_BUFFER_DONE) {
1530                 had_write_register(ctx, audio_reg, HDMI_AUDIO_BUFFER_DONE);
1531                 had_process_buffer_done(ctx);
1532         }
1533
1534         return IRQ_HANDLED;
1535 }
1536
1537 /*
1538  * monitor plug/unplug notification from i915; just kick off the work
1539  */
1540 static void notify_audio_lpe(struct platform_device *pdev)
1541 {
1542         struct snd_intelhad *ctx = platform_get_drvdata(pdev);
1543
1544         schedule_work(&ctx->hdmi_audio_wq);
1545 }
1546
1547 /* the work to handle monitor hot plug/unplug */
1548 static void had_audio_wq(struct work_struct *work)
1549 {
1550         struct snd_intelhad *ctx =
1551                 container_of(work, struct snd_intelhad, hdmi_audio_wq);
1552         struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data;
1553
1554         pm_runtime_get_sync(ctx->dev);
1555         mutex_lock(&ctx->mutex);
1556         if (!pdata->hdmi_connected) {
1557                 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG\n",
1558                         __func__);
1559                 memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */
1560                 had_process_hot_unplug(ctx);
1561         } else {
1562                 struct intel_hdmi_lpe_audio_eld *eld = &pdata->eld;
1563
1564                 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
1565                         __func__, eld->port_id, pdata->tmds_clock_speed);
1566
1567                 switch (eld->pipe_id) {
1568                 case 0:
1569                         ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
1570                         break;
1571                 case 1:
1572                         ctx->had_config_offset = AUDIO_HDMI_CONFIG_B;
1573                         break;
1574                 case 2:
1575                         ctx->had_config_offset = AUDIO_HDMI_CONFIG_C;
1576                         break;
1577                 default:
1578                         dev_dbg(ctx->dev, "Invalid pipe %d\n",
1579                                 eld->pipe_id);
1580                         break;
1581                 }
1582
1583                 memcpy(ctx->eld, eld->eld_data, sizeof(ctx->eld));
1584
1585                 ctx->dp_output = pdata->dp_output;
1586                 ctx->tmds_clock_speed = pdata->tmds_clock_speed;
1587                 ctx->link_rate = pdata->link_rate;
1588
1589                 had_process_hot_plug(ctx);
1590
1591                 /* Process mode change if stream is active */
1592                 had_process_mode_change(ctx);
1593         }
1594         mutex_unlock(&ctx->mutex);
1595         pm_runtime_put(ctx->dev);
1596 }
1597
1598 /*
1599  * PM callbacks
1600  */
1601
1602 static int hdmi_lpe_audio_runtime_suspend(struct device *dev)
1603 {
1604         struct snd_intelhad *ctx = dev_get_drvdata(dev);
1605         struct snd_pcm_substream *substream;
1606
1607         substream = had_substream_get(ctx);
1608         if (substream) {
1609                 snd_pcm_suspend(substream);
1610                 had_substream_put(ctx);
1611         }
1612
1613         return 0;
1614 }
1615
1616 static int __maybe_unused hdmi_lpe_audio_suspend(struct device *dev)
1617 {
1618         struct snd_intelhad *ctx = dev_get_drvdata(dev);
1619         int err;
1620
1621         err = hdmi_lpe_audio_runtime_suspend(dev);
1622         if (!err)
1623                 snd_power_change_state(ctx->card, SNDRV_CTL_POWER_D3hot);
1624         return err;
1625 }
1626
1627 static int __maybe_unused hdmi_lpe_audio_resume(struct device *dev)
1628 {
1629         struct snd_intelhad *ctx = dev_get_drvdata(dev);
1630
1631         snd_power_change_state(ctx->card, SNDRV_CTL_POWER_D0);
1632         return 0;
1633 }
1634
1635 /* release resources */
1636 static void hdmi_lpe_audio_free(struct snd_card *card)
1637 {
1638         struct snd_intelhad *ctx = card->private_data;
1639
1640         cancel_work_sync(&ctx->hdmi_audio_wq);
1641
1642         if (ctx->mmio_start)
1643                 iounmap(ctx->mmio_start);
1644         if (ctx->irq >= 0)
1645                 free_irq(ctx->irq, ctx);
1646 }
1647
1648 /*
1649  * hdmi_lpe_audio_probe - start bridge with i915
1650  *
1651  * This function is called when the i915 driver creates the
1652  * hdmi-lpe-audio platform device.
1653  */
1654 static int hdmi_lpe_audio_probe(struct platform_device *pdev)
1655 {
1656         struct snd_card *card;
1657         struct snd_intelhad *ctx;
1658         struct snd_pcm *pcm;
1659         struct intel_hdmi_lpe_audio_pdata *pdata;
1660         int irq;
1661         struct resource *res_mmio;
1662         int i, ret;
1663
1664         pdata = pdev->dev.platform_data;
1665         if (!pdata) {
1666                 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
1667                 return -EINVAL;
1668         }
1669
1670         /* get resources */
1671         irq = platform_get_irq(pdev, 0);
1672         if (irq < 0) {
1673                 dev_err(&pdev->dev, "Could not get irq resource\n");
1674                 return -ENODEV;
1675         }
1676
1677         res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1678         if (!res_mmio) {
1679                 dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
1680                 return -ENXIO;
1681         }
1682
1683         /* create a card instance with ALSA framework */
1684         ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
1685                            THIS_MODULE, sizeof(*ctx), &card);
1686         if (ret)
1687                 return ret;
1688
1689         ctx = card->private_data;
1690         spin_lock_init(&ctx->had_spinlock);
1691         mutex_init(&ctx->mutex);
1692         ctx->connected = false;
1693         ctx->dev = &pdev->dev;
1694         ctx->card = card;
1695         ctx->aes_bits = SNDRV_PCM_DEFAULT_CON_SPDIF;
1696         strcpy(card->driver, INTEL_HAD);
1697         strcpy(card->shortname, "Intel HDMI/DP LPE Audio");
1698         strcpy(card->longname, "Intel HDMI/DP LPE Audio");
1699
1700         ctx->irq = -1;
1701         ctx->tmds_clock_speed = DIS_SAMPLE_RATE_148_5;
1702         INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
1703
1704         card->private_free = hdmi_lpe_audio_free;
1705
1706         /* assume pipe A as default */
1707         ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
1708
1709         platform_set_drvdata(pdev, ctx);
1710
1711         dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
1712                 __func__, (unsigned int)res_mmio->start,
1713                 (unsigned int)res_mmio->end);
1714
1715         ctx->mmio_start = ioremap_nocache(res_mmio->start,
1716                                           (size_t)(resource_size(res_mmio)));
1717         if (!ctx->mmio_start) {
1718                 dev_err(&pdev->dev, "Could not get ioremap\n");
1719                 ret = -EACCES;
1720                 goto err;
1721         }
1722
1723         /* setup interrupt handler */
1724         ret = request_irq(irq, display_pipe_interrupt_handler, 0,
1725                           pdev->name, ctx);
1726         if (ret < 0) {
1727                 dev_err(&pdev->dev, "request_irq failed\n");
1728                 goto err;
1729         }
1730
1731         ctx->irq = irq;
1732
1733         ret = snd_pcm_new(card, INTEL_HAD, PCM_INDEX, MAX_PB_STREAMS,
1734                           MAX_CAP_STREAMS, &pcm);
1735         if (ret)
1736                 goto err;
1737
1738         /* setup private data which can be retrieved when required */
1739         pcm->private_data = ctx;
1740         pcm->info_flags = 0;
1741         strncpy(pcm->name, card->shortname, strlen(card->shortname));
1742         /* setup the ops for playabck */
1743         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops);
1744
1745         /* only 32bit addressable */
1746         dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1747         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1748
1749         /* allocate dma pages;
1750          * try to allocate 600k buffer as default which is large enough
1751          */
1752         snd_pcm_lib_preallocate_pages_for_all(pcm,
1753                         SNDRV_DMA_TYPE_DEV, NULL,
1754                         HAD_DEFAULT_BUFFER, HAD_MAX_BUFFER);
1755
1756         /* create controls */
1757         for (i = 0; i < ARRAY_SIZE(had_controls); i++) {
1758                 ret = snd_ctl_add(card, snd_ctl_new1(&had_controls[i], ctx));
1759                 if (ret < 0)
1760                         goto err;
1761         }
1762
1763         init_channel_allocations();
1764
1765         /* Register channel map controls */
1766         ret = had_register_chmap_ctls(ctx, pcm);
1767         if (ret < 0)
1768                 goto err;
1769
1770         ret = snd_card_register(card);
1771         if (ret)
1772                 goto err;
1773
1774         spin_lock_irq(&pdata->lpe_audio_slock);
1775         pdata->notify_audio_lpe = notify_audio_lpe;
1776         pdata->notify_pending = false;
1777         spin_unlock_irq(&pdata->lpe_audio_slock);
1778
1779         pm_runtime_set_active(&pdev->dev);
1780         pm_runtime_enable(&pdev->dev);
1781
1782         dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
1783         schedule_work(&ctx->hdmi_audio_wq);
1784
1785         return 0;
1786
1787 err:
1788         snd_card_free(card);
1789         return ret;
1790 }
1791
1792 /*
1793  * hdmi_lpe_audio_remove - stop bridge with i915
1794  *
1795  * This function is called when the platform device is destroyed.
1796  */
1797 static int hdmi_lpe_audio_remove(struct platform_device *pdev)
1798 {
1799         struct snd_intelhad *ctx = platform_get_drvdata(pdev);
1800
1801         snd_card_free(ctx->card);
1802         return 0;
1803 }
1804
1805 static const struct dev_pm_ops hdmi_lpe_audio_pm = {
1806         SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume)
1807         SET_RUNTIME_PM_OPS(hdmi_lpe_audio_runtime_suspend, NULL, NULL)
1808 };
1809
1810 static struct platform_driver hdmi_lpe_audio_driver = {
1811         .driver         = {
1812                 .name  = "hdmi-lpe-audio",
1813                 .pm = &hdmi_lpe_audio_pm,
1814         },
1815         .probe          = hdmi_lpe_audio_probe,
1816         .remove         = hdmi_lpe_audio_remove,
1817 };
1818
1819 module_platform_driver(hdmi_lpe_audio_driver);
1820 MODULE_ALIAS("platform:hdmi_lpe_audio");
1821
1822 MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
1823 MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
1824 MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
1825 MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
1826 MODULE_DESCRIPTION("Intel HDMI Audio driver");
1827 MODULE_LICENSE("GPL v2");
1828 MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}");