1 // SPDX-License-Identifier: GPL-2.0-only
3 * Xtfpga I2S controller driver
5 * Copyright (c) 2014 Cadence Design Systems Inc.
10 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14 #include <sound/pcm_params.h>
15 #include <sound/soc.h>
17 #define DRV_NAME "xtfpga-i2s"
19 #define XTFPGA_I2S_VERSION 0x00
20 #define XTFPGA_I2S_CONFIG 0x04
21 #define XTFPGA_I2S_INT_MASK 0x08
22 #define XTFPGA_I2S_INT_STATUS 0x0c
23 #define XTFPGA_I2S_CHAN0_DATA 0x10
24 #define XTFPGA_I2S_CHAN1_DATA 0x14
25 #define XTFPGA_I2S_CHAN2_DATA 0x18
26 #define XTFPGA_I2S_CHAN3_DATA 0x1c
28 #define XTFPGA_I2S_CONFIG_TX_ENABLE 0x1
29 #define XTFPGA_I2S_CONFIG_INT_ENABLE 0x2
30 #define XTFPGA_I2S_CONFIG_LEFT 0x4
31 #define XTFPGA_I2S_CONFIG_RATIO_BASE 8
32 #define XTFPGA_I2S_CONFIG_RATIO_MASK 0x0000ff00
33 #define XTFPGA_I2S_CONFIG_RES_BASE 16
34 #define XTFPGA_I2S_CONFIG_RES_MASK 0x003f0000
35 #define XTFPGA_I2S_CONFIG_LEVEL_BASE 24
36 #define XTFPGA_I2S_CONFIG_LEVEL_MASK 0x0f000000
37 #define XTFPGA_I2S_CONFIG_CHANNEL_BASE 28
39 #define XTFPGA_I2S_INT_UNDERRUN 0x1
40 #define XTFPGA_I2S_INT_LEVEL 0x2
41 #define XTFPGA_I2S_INT_VALID 0x3
43 #define XTFPGA_I2S_FIFO_SIZE 8192
46 * I2S controller operation:
48 * Enabling TX: output 1 period of zeros (starting with left channel)
49 * and then queued data.
51 * Level status and interrupt: whenever FIFO level is below FIFO trigger,
52 * level status is 1 and an IRQ is asserted (if enabled).
54 * Underrun status and interrupt: whenever FIFO is empty, underrun status
55 * is 1 and an IRQ is asserted (if enabled).
60 struct regmap *regmap;
63 /* current playback substream. NULL if not playing.
65 * Access to that field is synchronized between the interrupt handler
66 * and userspace through RCU.
68 * Interrupt handler (threaded part) does PIO on substream data in RCU
69 * read-side critical section. Trigger callback sets and clears the
70 * pointer when the playback is started and stopped with
71 * rcu_assign_pointer. When userspace is about to free the playback
72 * stream in the pcm_close callback it synchronizes with the interrupt
73 * handler by means of synchronize_rcu call.
75 struct snd_pcm_substream __rcu *tx_substream;
76 unsigned (*tx_fn)(struct xtfpga_i2s *i2s,
77 struct snd_pcm_runtime *runtime,
79 unsigned tx_ptr; /* next frame index in the sample buffer */
81 /* current fifo level estimate.
82 * Doesn't have to be perfectly accurate, but must be not less than
83 * the actual FIFO level in order to avoid stall on push attempt.
85 unsigned tx_fifo_level;
87 /* FIFO level at which level interrupt occurs */
90 /* maximal FIFO level */
91 unsigned tx_fifo_high;
94 static bool xtfpga_i2s_wr_reg(struct device *dev, unsigned int reg)
96 return reg >= XTFPGA_I2S_CONFIG;
99 static bool xtfpga_i2s_rd_reg(struct device *dev, unsigned int reg)
101 return reg < XTFPGA_I2S_CHAN0_DATA;
104 static bool xtfpga_i2s_volatile_reg(struct device *dev, unsigned int reg)
106 return reg == XTFPGA_I2S_INT_STATUS;
109 static const struct regmap_config xtfpga_i2s_regmap_config = {
113 .max_register = XTFPGA_I2S_CHAN3_DATA,
114 .writeable_reg = xtfpga_i2s_wr_reg,
115 .readable_reg = xtfpga_i2s_rd_reg,
116 .volatile_reg = xtfpga_i2s_volatile_reg,
117 .cache_type = REGCACHE_FLAT,
120 /* Generate functions that do PIO from TX DMA area to FIFO for all supported
122 * Functions will be called xtfpga_pcm_tx_<channels>x<sample bits>, e.g.
123 * xtfpga_pcm_tx_2x16 for 16-bit stereo.
125 * FIFO consists of 32-bit words, one word per channel, always 2 channels.
126 * If I2S interface is configured with smaller sample resolution, only
127 * the LSB of each word is used.
129 #define xtfpga_pcm_tx_fn(channels, sample_bits) \
130 static unsigned xtfpga_pcm_tx_##channels##x##sample_bits( \
131 struct xtfpga_i2s *i2s, struct snd_pcm_runtime *runtime, \
134 const u##sample_bits (*p)[channels] = \
135 (void *)runtime->dma_area; \
137 for (; i2s->tx_fifo_level < i2s->tx_fifo_high; \
138 i2s->tx_fifo_level += 2) { \
139 iowrite32(p[tx_ptr][0], \
140 i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
141 iowrite32(p[tx_ptr][channels - 1], \
142 i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
143 if (++tx_ptr >= runtime->buffer_size) \
149 xtfpga_pcm_tx_fn(1, 16)
150 xtfpga_pcm_tx_fn(2, 16)
151 xtfpga_pcm_tx_fn(1, 32)
152 xtfpga_pcm_tx_fn(2, 32)
154 #undef xtfpga_pcm_tx_fn
156 static bool xtfpga_pcm_push_tx(struct xtfpga_i2s *i2s)
158 struct snd_pcm_substream *tx_substream;
162 tx_substream = rcu_dereference(i2s->tx_substream);
163 tx_active = tx_substream && snd_pcm_running(tx_substream);
165 unsigned tx_ptr = READ_ONCE(i2s->tx_ptr);
166 unsigned new_tx_ptr = i2s->tx_fn(i2s, tx_substream->runtime,
169 cmpxchg(&i2s->tx_ptr, tx_ptr, new_tx_ptr);
176 static void xtfpga_pcm_refill_fifo(struct xtfpga_i2s *i2s)
181 regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
184 for (i = 0; i < 2; ++i) {
185 bool tx_active = xtfpga_pcm_push_tx(i2s);
187 regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
188 XTFPGA_I2S_INT_VALID);
190 regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
194 !(int_status & XTFPGA_I2S_INT_LEVEL))
197 /* After the push the level IRQ is still asserted,
198 * means FIFO level is below tx_fifo_low. Estimate
201 i2s->tx_fifo_level = i2s->tx_fifo_low;
204 if (!(int_status & XTFPGA_I2S_INT_LEVEL))
205 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
206 XTFPGA_I2S_INT_VALID);
207 else if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
208 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
209 XTFPGA_I2S_INT_UNDERRUN);
211 if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
212 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
213 XTFPGA_I2S_CONFIG_INT_ENABLE |
214 XTFPGA_I2S_CONFIG_TX_ENABLE,
215 XTFPGA_I2S_CONFIG_INT_ENABLE |
216 XTFPGA_I2S_CONFIG_TX_ENABLE);
218 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
219 XTFPGA_I2S_CONFIG_INT_ENABLE |
220 XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
223 static irqreturn_t xtfpga_i2s_threaded_irq_handler(int irq, void *dev_id)
225 struct xtfpga_i2s *i2s = dev_id;
226 struct snd_pcm_substream *tx_substream;
227 unsigned config, int_status, int_mask;
229 regmap_read(i2s->regmap, XTFPGA_I2S_CONFIG, &config);
230 regmap_read(i2s->regmap, XTFPGA_I2S_INT_MASK, &int_mask);
231 regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS, &int_status);
233 if (!(config & XTFPGA_I2S_CONFIG_INT_ENABLE) ||
234 !(int_status & int_mask & XTFPGA_I2S_INT_VALID))
237 /* Update FIFO level estimate in accordance with interrupt status
240 if (int_status & XTFPGA_I2S_INT_UNDERRUN) {
241 i2s->tx_fifo_level = 0;
242 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
243 XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
245 /* The FIFO isn't empty, but is below tx_fifo_low. Estimate
248 i2s->tx_fifo_level = i2s->tx_fifo_low;
252 tx_substream = rcu_dereference(i2s->tx_substream);
254 if (tx_substream && snd_pcm_running(tx_substream)) {
255 snd_pcm_period_elapsed(tx_substream);
256 if (int_status & XTFPGA_I2S_INT_UNDERRUN)
257 dev_dbg_ratelimited(i2s->dev, "%s: underrun\n",
262 /* Refill FIFO, update allowed IRQ reasons, enable IRQ if FIFO is
265 xtfpga_pcm_refill_fifo(i2s);
270 static int xtfpga_i2s_startup(struct snd_pcm_substream *substream,
271 struct snd_soc_dai *dai)
273 struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
275 snd_soc_dai_set_dma_data(dai, substream, i2s);
279 static int xtfpga_i2s_hw_params(struct snd_pcm_substream *substream,
280 struct snd_pcm_hw_params *params,
281 struct snd_soc_dai *dai)
283 struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
284 unsigned srate = params_rate(params);
285 unsigned channels = params_channels(params);
286 unsigned period_size = params_period_size(params);
287 unsigned sample_size = snd_pcm_format_width(params_format(params));
288 unsigned freq, ratio, level;
291 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
292 XTFPGA_I2S_CONFIG_RES_MASK,
293 sample_size << XTFPGA_I2S_CONFIG_RES_BASE);
296 err = clk_set_rate(i2s->clk, freq);
300 /* ratio field of the config register controls MCLK->I2S clock
301 * derivation: I2S clock = MCLK / (2 * (ratio + 2)).
303 * So with MCLK = 256 * sample rate ratio is 0 for 32 bit stereo
304 * and 2 for 16 bit stereo.
306 ratio = (freq - (srate * sample_size * 8)) /
307 (srate * sample_size * 4);
309 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
310 XTFPGA_I2S_CONFIG_RATIO_MASK,
311 ratio << XTFPGA_I2S_CONFIG_RATIO_BASE);
313 i2s->tx_fifo_low = XTFPGA_I2S_FIFO_SIZE / 2;
315 /* period_size * 2: FIFO always gets 2 samples per frame */
317 i2s->tx_fifo_low / 2 >= period_size * 2 &&
318 level < (XTFPGA_I2S_CONFIG_LEVEL_MASK >>
319 XTFPGA_I2S_CONFIG_LEVEL_BASE); ++level)
320 i2s->tx_fifo_low /= 2;
322 i2s->tx_fifo_high = 2 * i2s->tx_fifo_low;
324 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
325 XTFPGA_I2S_CONFIG_LEVEL_MASK,
326 level << XTFPGA_I2S_CONFIG_LEVEL_BASE);
329 "%s srate: %u, channels: %u, sample_size: %u, period_size: %u\n",
330 __func__, srate, channels, sample_size, period_size);
331 dev_dbg(i2s->dev, "%s freq: %u, ratio: %u, level: %u\n",
332 __func__, freq, ratio, level);
337 static int xtfpga_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
340 if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
342 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
344 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_I2S)
352 static const struct snd_pcm_hardware xtfpga_pcm_hardware = {
353 .info = SNDRV_PCM_INFO_INTERLEAVED |
354 SNDRV_PCM_INFO_MMAP_VALID |
355 SNDRV_PCM_INFO_BLOCK_TRANSFER,
356 .formats = SNDRV_PCM_FMTBIT_S16_LE |
357 SNDRV_PCM_FMTBIT_S32_LE,
360 .period_bytes_min = 2,
361 .period_bytes_max = XTFPGA_I2S_FIFO_SIZE / 2 * 8,
363 .periods_max = XTFPGA_I2S_FIFO_SIZE * 8 / 2,
364 .buffer_bytes_max = XTFPGA_I2S_FIFO_SIZE * 8,
368 static int xtfpga_pcm_open(struct snd_soc_component *component,
369 struct snd_pcm_substream *substream)
371 struct snd_pcm_runtime *runtime = substream->runtime;
372 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
375 snd_soc_set_runtime_hwparams(substream, &xtfpga_pcm_hardware);
376 p = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
377 runtime->private_data = p;
382 static int xtfpga_pcm_close(struct snd_soc_component *component,
383 struct snd_pcm_substream *substream)
389 static int xtfpga_pcm_hw_params(struct snd_soc_component *component,
390 struct snd_pcm_substream *substream,
391 struct snd_pcm_hw_params *hw_params)
393 struct snd_pcm_runtime *runtime = substream->runtime;
394 struct xtfpga_i2s *i2s = runtime->private_data;
395 unsigned channels = params_channels(hw_params);
407 switch (params_format(hw_params)) {
408 case SNDRV_PCM_FORMAT_S16_LE:
409 i2s->tx_fn = (channels == 1) ?
414 case SNDRV_PCM_FORMAT_S32_LE:
415 i2s->tx_fn = (channels == 1) ?
427 static int xtfpga_pcm_trigger(struct snd_soc_component *component,
428 struct snd_pcm_substream *substream, int cmd)
431 struct snd_pcm_runtime *runtime = substream->runtime;
432 struct xtfpga_i2s *i2s = runtime->private_data;
435 case SNDRV_PCM_TRIGGER_START:
436 case SNDRV_PCM_TRIGGER_RESUME:
437 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
438 WRITE_ONCE(i2s->tx_ptr, 0);
439 rcu_assign_pointer(i2s->tx_substream, substream);
440 xtfpga_pcm_refill_fifo(i2s);
443 case SNDRV_PCM_TRIGGER_STOP:
444 case SNDRV_PCM_TRIGGER_SUSPEND:
445 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
446 rcu_assign_pointer(i2s->tx_substream, NULL);
456 static snd_pcm_uframes_t xtfpga_pcm_pointer(struct snd_soc_component *component,
457 struct snd_pcm_substream *substream)
459 struct snd_pcm_runtime *runtime = substream->runtime;
460 struct xtfpga_i2s *i2s = runtime->private_data;
461 snd_pcm_uframes_t pos = READ_ONCE(i2s->tx_ptr);
463 return pos < runtime->buffer_size ? pos : 0;
466 static int xtfpga_pcm_new(struct snd_soc_component *component,
467 struct snd_soc_pcm_runtime *rtd)
469 struct snd_card *card = rtd->card->snd_card;
470 size_t size = xtfpga_pcm_hardware.buffer_bytes_max;
472 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
473 card->dev, size, size);
477 static const struct snd_soc_component_driver xtfpga_i2s_component = {
479 .open = xtfpga_pcm_open,
480 .close = xtfpga_pcm_close,
481 .hw_params = xtfpga_pcm_hw_params,
482 .trigger = xtfpga_pcm_trigger,
483 .pointer = xtfpga_pcm_pointer,
484 .pcm_construct = xtfpga_pcm_new,
487 static const struct snd_soc_dai_ops xtfpga_i2s_dai_ops = {
488 .startup = xtfpga_i2s_startup,
489 .hw_params = xtfpga_i2s_hw_params,
490 .set_fmt = xtfpga_i2s_set_fmt,
493 static struct snd_soc_dai_driver xtfpga_i2s_dai[] = {
495 .name = "xtfpga-i2s",
500 .rates = SNDRV_PCM_RATE_8000_96000,
501 .formats = SNDRV_PCM_FMTBIT_S16_LE |
502 SNDRV_PCM_FMTBIT_S32_LE,
504 .ops = &xtfpga_i2s_dai_ops,
508 static int xtfpga_i2s_runtime_suspend(struct device *dev)
510 struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
512 clk_disable_unprepare(i2s->clk);
516 static int xtfpga_i2s_runtime_resume(struct device *dev)
518 struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
521 ret = clk_prepare_enable(i2s->clk);
523 dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
529 static int xtfpga_i2s_probe(struct platform_device *pdev)
531 struct xtfpga_i2s *i2s;
534 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
539 platform_set_drvdata(pdev, i2s);
540 i2s->dev = &pdev->dev;
541 dev_dbg(&pdev->dev, "dev: %p, i2s: %p\n", &pdev->dev, i2s);
543 i2s->regs = devm_platform_ioremap_resource(pdev, 0);
544 if (IS_ERR(i2s->regs)) {
545 err = PTR_ERR(i2s->regs);
549 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs,
550 &xtfpga_i2s_regmap_config);
551 if (IS_ERR(i2s->regmap)) {
552 dev_err(&pdev->dev, "regmap init failed\n");
553 err = PTR_ERR(i2s->regmap);
557 i2s->clk = devm_clk_get(&pdev->dev, NULL);
558 if (IS_ERR(i2s->clk)) {
559 dev_err(&pdev->dev, "couldn't get clock\n");
560 err = PTR_ERR(i2s->clk);
564 regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG,
565 (0x1 << XTFPGA_I2S_CONFIG_CHANNEL_BASE));
566 regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS, XTFPGA_I2S_INT_VALID);
567 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, XTFPGA_I2S_INT_UNDERRUN);
569 irq = platform_get_irq(pdev, 0);
574 err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
575 xtfpga_i2s_threaded_irq_handler,
576 IRQF_SHARED | IRQF_ONESHOT,
579 dev_err(&pdev->dev, "request_irq failed\n");
583 err = devm_snd_soc_register_component(&pdev->dev,
584 &xtfpga_i2s_component,
586 ARRAY_SIZE(xtfpga_i2s_dai));
588 dev_err(&pdev->dev, "couldn't register component\n");
592 pm_runtime_enable(&pdev->dev);
593 if (!pm_runtime_enabled(&pdev->dev)) {
594 err = xtfpga_i2s_runtime_resume(&pdev->dev);
601 pm_runtime_disable(&pdev->dev);
603 dev_err(&pdev->dev, "%s: err = %d\n", __func__, err);
607 static int xtfpga_i2s_remove(struct platform_device *pdev)
609 struct xtfpga_i2s *i2s = dev_get_drvdata(&pdev->dev);
611 if (i2s->regmap && !IS_ERR(i2s->regmap)) {
612 regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG, 0);
613 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, 0);
614 regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
615 XTFPGA_I2S_INT_VALID);
617 pm_runtime_disable(&pdev->dev);
618 if (!pm_runtime_status_suspended(&pdev->dev))
619 xtfpga_i2s_runtime_suspend(&pdev->dev);
624 static const struct of_device_id xtfpga_i2s_of_match[] = {
625 { .compatible = "cdns,xtfpga-i2s", },
628 MODULE_DEVICE_TABLE(of, xtfpga_i2s_of_match);
631 static const struct dev_pm_ops xtfpga_i2s_pm_ops = {
632 SET_RUNTIME_PM_OPS(xtfpga_i2s_runtime_suspend,
633 xtfpga_i2s_runtime_resume, NULL)
636 static struct platform_driver xtfpga_i2s_driver = {
637 .probe = xtfpga_i2s_probe,
638 .remove = xtfpga_i2s_remove,
640 .name = "xtfpga-i2s",
641 .of_match_table = of_match_ptr(xtfpga_i2s_of_match),
642 .pm = &xtfpga_i2s_pm_ops,
646 module_platform_driver(xtfpga_i2s_driver);
648 MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
649 MODULE_DESCRIPTION("xtfpga I2S controller driver");
650 MODULE_LICENSE("GPL v2");