sound/soc/ti/omap-mcbsp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   4  *
   5  * Copyright (C) 2008 Nokia Corporation
   6  *
   7  * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
   8  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/module.h>
  13 #include <linux/device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <sound/core.h>
  18 #include <sound/pcm.h>
  19 #include <sound/pcm_params.h>
  20 #include <sound/initval.h>
  21 #include <sound/soc.h>
  22 #include <sound/dmaengine_pcm.h>
  23
  24 #include "omap-mcbsp-priv.h"
  25 #include "omap-mcbsp.h"
  26 #include "sdma-pcm.h"
  27
  28 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  29
  30 enum {
  31         OMAP_MCBSP_WORD_8 = 0,
  32         OMAP_MCBSP_WORD_12,
  33         OMAP_MCBSP_WORD_16,
  34         OMAP_MCBSP_WORD_20,
  35         OMAP_MCBSP_WORD_24,
  36         OMAP_MCBSP_WORD_32,
  37 };
  38
  39 static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
  40 {
  41         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  42         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n", MCBSP_READ(mcbsp, DRR2));
  43         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n", MCBSP_READ(mcbsp, DRR1));
  44         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n", MCBSP_READ(mcbsp, DXR2));
  45         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n", MCBSP_READ(mcbsp, DXR1));
  46         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", MCBSP_READ(mcbsp, SPCR2));
  47         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", MCBSP_READ(mcbsp, SPCR1));
  48         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n", MCBSP_READ(mcbsp, RCR2));
  49         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n", MCBSP_READ(mcbsp, RCR1));
  50         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n", MCBSP_READ(mcbsp, XCR2));
  51         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n", MCBSP_READ(mcbsp, XCR1));
  52         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", MCBSP_READ(mcbsp, SRGR2));
  53         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", MCBSP_READ(mcbsp, SRGR1));
  54         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n", MCBSP_READ(mcbsp, PCR0));
  55         dev_dbg(mcbsp->dev, "***********************\n");
  56 }
  57
  58 static int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
  59 {
  60         struct clk *fck_src;
  61         const char *src;
  62         int r;
  63
  64         if (fck_src_id == MCBSP_CLKS_PAD_SRC)
  65                 src = "pad_fck";
  66         else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
  67                 src = "prcm_fck";
  68         else
  69                 return -EINVAL;
  70
  71         fck_src = clk_get(mcbsp->dev, src);
  72         if (IS_ERR(fck_src)) {
  73                 dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
  74                 return -EINVAL;
  75         }
  76
  77         pm_runtime_put_sync(mcbsp->dev);
  78
  79         r = clk_set_parent(mcbsp->fclk, fck_src);
  80         if (r)
  81                 dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
  82                         src);
  83
  84         pm_runtime_get_sync(mcbsp->dev);
  85
  86         clk_put(fck_src);
  87
  88         return r;
  89 }
  90
  91 static irqreturn_t omap_mcbsp_irq_handler(int irq, void *data)
  92 {
  93         struct omap_mcbsp *mcbsp = data;
  94         u16 irqst;
  95
  96         irqst = MCBSP_READ(mcbsp, IRQST);
  97         dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
  98
  99         if (irqst & RSYNCERREN)
 100                 dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
 101         if (irqst & RFSREN)
 102                 dev_dbg(mcbsp->dev, "RX Frame Sync\n");
 103         if (irqst & REOFEN)
 104                 dev_dbg(mcbsp->dev, "RX End Of Frame\n");
 105         if (irqst & RRDYEN)
 106                 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
 107         if (irqst & RUNDFLEN)
 108                 dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
 109         if (irqst & ROVFLEN)
 110                 dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
 111
 112         if (irqst & XSYNCERREN)
 113                 dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
 114         if (irqst & XFSXEN)
 115                 dev_dbg(mcbsp->dev, "TX Frame Sync\n");
 116         if (irqst & XEOFEN)
 117                 dev_dbg(mcbsp->dev, "TX End Of Frame\n");
 118         if (irqst & XRDYEN)
 119                 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
 120         if (irqst & XUNDFLEN)
 121                 dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
 122         if (irqst & XOVFLEN)
 123                 dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
 124         if (irqst & XEMPTYEOFEN)
 125                 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
 126
 127         MCBSP_WRITE(mcbsp, IRQST, irqst);
 128
 129         return IRQ_HANDLED;
 130 }
 131
 132 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *data)
 133 {
 134         struct omap_mcbsp *mcbsp = data;
 135         u16 irqst_spcr2;
 136
 137         irqst_spcr2 = MCBSP_READ(mcbsp, SPCR2);
 138         dev_dbg(mcbsp->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
 139
 140         if (irqst_spcr2 & XSYNC_ERR) {
 141                 dev_err(mcbsp->dev, "TX Frame Sync Error! : 0x%x\n",
 142                         irqst_spcr2);
 143                 /* Writing zero to XSYNC_ERR clears the IRQ */
 144                 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
 145         }
 146
 147         return IRQ_HANDLED;
 148 }
 149
 150 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *data)
 151 {
 152         struct omap_mcbsp *mcbsp = data;
 153         u16 irqst_spcr1;
 154
 155         irqst_spcr1 = MCBSP_READ(mcbsp, SPCR1);
 156         dev_dbg(mcbsp->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 157
 158         if (irqst_spcr1 & RSYNC_ERR) {
 159                 dev_err(mcbsp->dev, "RX Frame Sync Error! : 0x%x\n",
 160                         irqst_spcr1);
 161                 /* Writing zero to RSYNC_ERR clears the IRQ */
 162                 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
 163         }
 164
 165         return IRQ_HANDLED;
 166 }
 167
 168 /*
 169  * omap_mcbsp_config simply write a config to the
 170  * appropriate McBSP.
 171  * You either call this function or set the McBSP registers
 172  * by yourself before calling omap_mcbsp_start().
 173  */
 174 static void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
 175                               const struct omap_mcbsp_reg_cfg *config)
 176 {
 177         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 178                 mcbsp->id, mcbsp->phys_base);
 179
 180         /* We write the given config */
 181         MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
 182         MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
 183         MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
 184         MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
 185         MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
 186         MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
 187         MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
 188         MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
 189         MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
 190         MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
 191         MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
 192         if (mcbsp->pdata->has_ccr) {
 193                 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
 194                 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
 195         }
 196         /* Enable wakeup behavior */
 197         if (mcbsp->pdata->has_wakeup)
 198                 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
 199
 200         /* Enable TX/RX sync error interrupts by default */
 201         if (mcbsp->irq)
 202                 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN |
 203                             RUNDFLEN | ROVFLEN | XUNDFLEN | XOVFLEN);
 204 }
 205
 206 /**
 207  * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
 208  * @mcbsp: omap_mcbsp struct for the McBSP instance
 209  * @stream: Stream direction (playback/capture)
 210  *
 211  * Returns the address of mcbsp data transmit register or data receive register
 212  * to be used by DMA for transferring/receiving data
 213  */
 214 static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
 215                                      unsigned int stream)
 216 {
 217         int data_reg;
 218
 219         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 220                 if (mcbsp->pdata->reg_size == 2)
 221                         data_reg = OMAP_MCBSP_REG_DXR1;
 222                 else
 223                         data_reg = OMAP_MCBSP_REG_DXR;
 224         } else {
 225                 if (mcbsp->pdata->reg_size == 2)
 226                         data_reg = OMAP_MCBSP_REG_DRR1;
 227                 else
 228                         data_reg = OMAP_MCBSP_REG_DRR;
 229         }
 230
 231         return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
 232 }
 233
 234 /*
 235  * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
 236  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 237  * for the THRSH2 register.
 238  */
 239 static void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
 240 {
 241         if (threshold && threshold <= mcbsp->max_tx_thres)
 242                 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
 243 }
 244
 245 /*
 246  * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
 247  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 248  * for the THRSH1 register.
 249  */
 250 static void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
 251 {
 252         if (threshold && threshold <= mcbsp->max_rx_thres)
 253                 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
 254 }
 255
 256 /*
 257  * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
 258  */
 259 static u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
 260 {
 261         u16 buffstat;
 262
 263         /* Returns the number of free locations in the buffer */
 264         buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
 265
 266         /* Number of slots are different in McBSP ports */
 267         return mcbsp->pdata->buffer_size - buffstat;
 268 }
 269
 270 /*
 271  * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
 272  * to reach the threshold value (when the DMA will be triggered to read it)
 273  */
 274 static u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
 275 {
 276         u16 buffstat, threshold;
 277
 278         /* Returns the number of used locations in the buffer */
 279         buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
 280         /* RX threshold */
 281         threshold = MCBSP_READ(mcbsp, THRSH1);
 282
 283         /* Return the number of location till we reach the threshold limit */
 284         if (threshold <= buffstat)
 285                 return 0;
 286         else
 287                 return threshold - buffstat;
 288 }
 289
 290 static int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
 291 {
 292         void *reg_cache;
 293         int err;
 294
 295         reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
 296         if (!reg_cache)
 297                 return -ENOMEM;
 298
 299         spin_lock(&mcbsp->lock);
 300         if (!mcbsp->free) {
 301                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id);
 302                 err = -EBUSY;
 303                 goto err_kfree;
 304         }
 305
 306         mcbsp->free = false;
 307         mcbsp->reg_cache = reg_cache;
 308         spin_unlock(&mcbsp->lock);
 309
 310         if(mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 311                 mcbsp->pdata->ops->request(mcbsp->id - 1);
 312
 313         /*
 314          * Make sure that transmitter, receiver and sample-rate generator are
 315          * not running before activating IRQs.
 316          */
 317         MCBSP_WRITE(mcbsp, SPCR1, 0);
 318         MCBSP_WRITE(mcbsp, SPCR2, 0);
 319
 320         if (mcbsp->irq) {
 321                 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
 322                                   "McBSP", (void *)mcbsp);
 323                 if (err != 0) {
 324                         dev_err(mcbsp->dev, "Unable to request IRQ\n");
 325                         goto err_clk_disable;
 326                 }
 327         } else {
 328                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
 329                                   "McBSP TX", (void *)mcbsp);
 330                 if (err != 0) {
 331                         dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
 332                         goto err_clk_disable;
 333                 }
 334
 335                 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
 336                                   "McBSP RX", (void *)mcbsp);
 337                 if (err != 0) {
 338                         dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
 339                         goto err_free_irq;
 340                 }
 341         }
 342
 343         return 0;
 344 err_free_irq:
 345         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 346 err_clk_disable:
 347         if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 348                 mcbsp->pdata->ops->free(mcbsp->id - 1);
 349
 350         /* Disable wakeup behavior */
 351         if (mcbsp->pdata->has_wakeup)
 352                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 353
 354         spin_lock(&mcbsp->lock);
 355         mcbsp->free = true;
 356         mcbsp->reg_cache = NULL;
 357 err_kfree:
 358         spin_unlock(&mcbsp->lock);
 359         kfree(reg_cache);
 360
 361         return err;
 362 }
 363
 364 static void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
 365 {
 366         void *reg_cache;
 367
 368         if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 369                 mcbsp->pdata->ops->free(mcbsp->id - 1);
 370
 371         /* Disable wakeup behavior */
 372         if (mcbsp->pdata->has_wakeup)
 373                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 374
 375         /* Disable interrupt requests */
 376         if (mcbsp->irq) {
 377                 MCBSP_WRITE(mcbsp, IRQEN, 0);
 378
 379                 free_irq(mcbsp->irq, (void *)mcbsp);
 380         } else {
 381                 free_irq(mcbsp->rx_irq, (void *)mcbsp);
 382                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 383         }
 384
 385         reg_cache = mcbsp->reg_cache;
 386
 387         /*
 388          * Select CLKS source from internal source unconditionally before
 389          * marking the McBSP port as free.
 390          * If the external clock source via MCBSP_CLKS pin has been selected the
 391          * system will refuse to enter idle if the CLKS pin source is not reset
 392          * back to internal source.
 393          */
 394         if (!mcbsp_omap1())
 395                 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
 396
 397         spin_lock(&mcbsp->lock);
 398         if (mcbsp->free)
 399                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
 400         else
 401                 mcbsp->free = true;
 402         mcbsp->reg_cache = NULL;
 403         spin_unlock(&mcbsp->lock);
 404
 405         kfree(reg_cache);
 406 }
 407
 408 /*
 409  * Here we start the McBSP, by enabling transmitter, receiver or both.
 410  * If no transmitter or receiver is active prior calling, then sample-rate
 411  * generator and frame sync are started.
 412  */
 413 static void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int stream)
 414 {
 415         int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
 416         int rx = !tx;
 417         int enable_srg = 0;
 418         u16 w;
 419
 420         if (mcbsp->st_data)
 421                 omap_mcbsp_st_start(mcbsp);
 422
 423         /* Only enable SRG, if McBSP is master */
 424         w = MCBSP_READ_CACHE(mcbsp, PCR0);
 425         if (w & (FSXM | FSRM | CLKXM | CLKRM))
 426                 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 427                                 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 428
 429         if (enable_srg) {
 430                 /* Start the sample generator */
 431                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 432                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
 433         }
 434
 435         /* Enable transmitter and receiver */
 436         tx &= 1;
 437         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 438         MCBSP_WRITE(mcbsp, SPCR2, w | tx);
 439
 440         rx &= 1;
 441         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 442         MCBSP_WRITE(mcbsp, SPCR1, w | rx);
 443
 444         /*
 445          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 446          * REVISIT: 100us may give enough time for two CLKSRG, however
 447          * due to some unknown PM related, clock gating etc. reason it
 448          * is now at 500us.
 449          */
 450         udelay(500);
 451
 452         if (enable_srg) {
 453                 /* Start frame sync */
 454                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 455                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
 456         }
 457
 458         if (mcbsp->pdata->has_ccr) {
 459                 /* Release the transmitter and receiver */
 460                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 461                 w &= ~(tx ? XDISABLE : 0);
 462                 MCBSP_WRITE(mcbsp, XCCR, w);
 463                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 464                 w &= ~(rx ? RDISABLE : 0);
 465                 MCBSP_WRITE(mcbsp, RCCR, w);
 466         }
 467
 468         /* Dump McBSP Regs */
 469         omap_mcbsp_dump_reg(mcbsp);
 470 }
 471
 472 static void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int stream)
 473 {
 474         int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
 475         int rx = !tx;
 476         int idle;
 477         u16 w;
 478
 479         /* Reset transmitter */
 480         tx &= 1;
 481         if (mcbsp->pdata->has_ccr) {
 482                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 483                 w |= (tx ? XDISABLE : 0);
 484                 MCBSP_WRITE(mcbsp, XCCR, w);
 485         }
 486         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 487         MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
 488
 489         /* Reset receiver */
 490         rx &= 1;
 491         if (mcbsp->pdata->has_ccr) {
 492                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 493                 w |= (rx ? RDISABLE : 0);
 494                 MCBSP_WRITE(mcbsp, RCCR, w);
 495         }
 496         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 497         MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
 498
 499         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 500                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 501
 502         if (idle) {
 503                 /* Reset the sample rate generator */
 504                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 505                 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
 506         }
 507
 508         if (mcbsp->st_data)
 509                 omap_mcbsp_st_stop(mcbsp);
 510 }
 511
 512 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
 513 #define valid_threshold(m, val)         ((val) <= max_thres(m))
 514 #define THRESHOLD_PROP_BUILDER(prop)                                    \
 515 static ssize_t prop##_show(struct device *dev,                          \
 516                         struct device_attribute *attr, char *buf)       \
 517 {                                                                       \
 518         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
 519                                                                         \
 520         return sprintf(buf, "%u\n", mcbsp->prop);                       \
 521 }                                                                       \
 522                                                                         \
 523 static ssize_t prop##_store(struct device *dev,                         \
 524                                 struct device_attribute *attr,          \
 525                                 const char *buf, size_t size)           \
 526 {                                                                       \
 527         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
 528         unsigned long val;                                              \
 529         int status;                                                     \
 530                                                                         \
 531         status = kstrtoul(buf, 0, &val);                                \
 532         if (status)                                                     \
 533                 return status;                                          \
 534                                                                         \
 535         if (!valid_threshold(mcbsp, val))                               \
 536                 return -EDOM;                                           \
 537                                                                         \
 538         mcbsp->prop = val;                                              \
 539         return size;                                                    \
 540 }                                                                       \
 541                                                                         \
 542 static DEVICE_ATTR_RW(prop)
 543
 544 THRESHOLD_PROP_BUILDER(max_tx_thres);
 545 THRESHOLD_PROP_BUILDER(max_rx_thres);
 546
 547 static const char * const dma_op_modes[] = {
 548         "element", "threshold",
 549 };
 550
 551 static ssize_t dma_op_mode_show(struct device *dev,
 552                                 struct device_attribute *attr, char *buf)
 553 {
 554         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 555         int dma_op_mode, i = 0;
 556         ssize_t len = 0;
 557         const char * const *s;
 558
 559         dma_op_mode = mcbsp->dma_op_mode;
 560
 561         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
 562                 if (dma_op_mode == i)
 563                         len += sprintf(buf + len, "[%s] ", *s);
 564                 else
 565                         len += sprintf(buf + len, "%s ", *s);
 566         }
 567         len += sprintf(buf + len, "\n");
 568
 569         return len;
 570 }
 571
 572 static ssize_t dma_op_mode_store(struct device *dev,
 573                                  struct device_attribute *attr, const char *buf,
 574                                  size_t size)
 575 {
 576         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 577         int i;
 578
 579         i = sysfs_match_string(dma_op_modes, buf);
 580         if (i < 0)
 581                 return i;
 582
 583         spin_lock_irq(&mcbsp->lock);
 584         if (!mcbsp->free) {
 585                 size = -EBUSY;
 586                 goto unlock;
 587         }
 588         mcbsp->dma_op_mode = i;
 589
 590 unlock:
 591         spin_unlock_irq(&mcbsp->lock);
 592
 593         return size;
 594 }
 595
 596 static DEVICE_ATTR_RW(dma_op_mode);
 597
 598 static const struct attribute *additional_attrs[] = {
 599         &dev_attr_max_tx_thres.attr,
 600         &dev_attr_max_rx_thres.attr,
 601         &dev_attr_dma_op_mode.attr,
 602         NULL,
 603 };
 604
 605 static const struct attribute_group additional_attr_group = {
 606         .attrs = (struct attribute **)additional_attrs,
 607 };
 608
 609 /*
 610  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
 611  * 730 has only 2 McBSP, and both of them are MPU peripherals.
 612  */
 613 static int omap_mcbsp_init(struct platform_device *pdev)
 614 {
 615         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
 616         struct resource *res;
 617         int ret = 0;
 618
 619         spin_lock_init(&mcbsp->lock);
 620         mcbsp->free = true;
 621
 622         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
 623         if (!res)
 624                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 625
 626         mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res);
 627         if (IS_ERR(mcbsp->io_base))
 628                 return PTR_ERR(mcbsp->io_base);
 629
 630         mcbsp->phys_base = res->start;
 631         mcbsp->reg_cache_size = resource_size(res);
 632
 633         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
 634         if (!res)
 635                 mcbsp->phys_dma_base = mcbsp->phys_base;
 636         else
 637                 mcbsp->phys_dma_base = res->start;
 638
 639         /*
 640          * OMAP1, 2 uses two interrupt lines: TX, RX
 641          * OMAP2430, OMAP3 SoC have combined IRQ line as well.
 642          * OMAP4 and newer SoC only have the combined IRQ line.
 643          * Use the combined IRQ if available since it gives better debugging
 644          * possibilities.
 645          */
 646         mcbsp->irq = platform_get_irq_byname(pdev, "common");
 647         if (mcbsp->irq == -ENXIO) {
 648                 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
 649
 650                 if (mcbsp->tx_irq == -ENXIO) {
 651                         mcbsp->irq = platform_get_irq(pdev, 0);
 652                         mcbsp->tx_irq = 0;
 653                 } else {
 654                         mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
 655                         mcbsp->irq = 0;
 656                 }
 657         }
 658
 659         if (!pdev->dev.of_node) {
 660                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
 661                 if (!res) {
 662                         dev_err(&pdev->dev, "invalid tx DMA channel\n");
 663                         return -ENODEV;
 664                 }
 665                 mcbsp->dma_req[0] = res->start;
 666                 mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0];
 667
 668                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
 669                 if (!res) {
 670                         dev_err(&pdev->dev, "invalid rx DMA channel\n");
 671                         return -ENODEV;
 672                 }
 673                 mcbsp->dma_req[1] = res->start;
 674                 mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1];
 675         } else {
 676                 mcbsp->dma_data[0].filter_data = "tx";
 677                 mcbsp->dma_data[1].filter_data = "rx";
 678         }
 679
 680         mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp,
 681                                                 SNDRV_PCM_STREAM_PLAYBACK);
 682         mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp,
 683                                                 SNDRV_PCM_STREAM_CAPTURE);
 684
 685         mcbsp->fclk = devm_clk_get(&pdev->dev, "fck");
 686         if (IS_ERR(mcbsp->fclk)) {
 687                 ret = PTR_ERR(mcbsp->fclk);
 688                 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
 689                 return ret;
 690         }
 691
 692         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
 693         if (mcbsp->pdata->buffer_size) {
 694                 /*
 695                  * Initially configure the maximum thresholds to a safe value.
 696                  * The McBSP FIFO usage with these values should not go under
 697                  * 16 locations.
 698                  * If the whole FIFO without safety buffer is used, than there
 699                  * is a possibility that the DMA will be not able to push the
 700                  * new data on time, causing channel shifts in runtime.
 701                  */
 702                 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
 703                 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
 704
 705                 ret = devm_device_add_group(mcbsp->dev, &additional_attr_group);
 706                 if (ret) {
 707                         dev_err(mcbsp->dev,
 708                                 "Unable to create additional controls\n");
 709                         return ret;
 710                 }
 711         }
 712
 713         return omap_mcbsp_st_init(pdev);
 714 }
 715
 716 /*
 717  * Stream DMA parameters. DMA request line and port address are set runtime
 718  * since they are different between OMAP1 and later OMAPs
 719  */
 720 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream,
 721                 unsigned int packet_size)
 722 {
 723         struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
 724         struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
 725         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 726         int words;
 727
 728         /* No need to proceed further if McBSP does not have FIFO */
 729         if (mcbsp->pdata->buffer_size == 0)
 730                 return;
 731
 732         /*
 733          * Configure McBSP threshold based on either:
 734          * packet_size, when the sDMA is in packet mode, or based on the
 735          * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
 736          * for mono streams.
 737          */
 738         if (packet_size)
 739                 words = packet_size;
 740         else
 741                 words = 1;
 742
 743         /* Configure McBSP internal buffer usage */
 744         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 745                 omap_mcbsp_set_tx_threshold(mcbsp, words);
 746         else
 747                 omap_mcbsp_set_rx_threshold(mcbsp, words);
 748 }
 749
 750 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
 751                                     struct snd_pcm_hw_rule *rule)
 752 {
 753         struct snd_interval *buffer_size = hw_param_interval(params,
 754                                         SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
 755         struct snd_interval *channels = hw_param_interval(params,
 756                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 757         struct omap_mcbsp *mcbsp = rule->private;
 758         struct snd_interval frames;
 759         int size;
 760
 761         snd_interval_any(&frames);
 762         size = mcbsp->pdata->buffer_size;
 763
 764         frames.min = size / channels->min;
 765         frames.integer = 1;
 766         return snd_interval_refine(buffer_size, &frames);
 767 }
 768
 769 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 770                                   struct snd_soc_dai *cpu_dai)
 771 {
 772         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 773         int err = 0;
 774
 775         if (!snd_soc_dai_active(cpu_dai))
 776                 err = omap_mcbsp_request(mcbsp);
 777
 778         /*
 779          * OMAP3 McBSP FIFO is word structured.
 780          * McBSP2 has 1024 + 256 = 1280 word long buffer,
 781          * McBSP1,3,4,5 has 128 word long buffer
 782          * This means that the size of the FIFO depends on the sample format.
 783          * For example on McBSP3:
 784          * 16bit samples: size is 128 * 2 = 256 bytes
 785          * 32bit samples: size is 128 * 4 = 512 bytes
 786          * It is simpler to place constraint for buffer and period based on
 787          * channels.
 788          * McBSP3 as example again (16 or 32 bit samples):
 789          * 1 channel (mono): size is 128 frames (128 words)
 790          * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
 791          * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
 792          */
 793         if (mcbsp->pdata->buffer_size) {
 794                 /*
 795                 * Rule for the buffer size. We should not allow
 796                 * smaller buffer than the FIFO size to avoid underruns.
 797                 * This applies only for the playback stream.
 798                 */
 799                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 800                         snd_pcm_hw_rule_add(substream->runtime, 0,
 801                                             SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 802                                             omap_mcbsp_hwrule_min_buffersize,
 803                                             mcbsp,
 804                                             SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 805
 806                 /* Make sure, that the period size is always even */
 807                 snd_pcm_hw_constraint_step(substream->runtime, 0,
 808                                            SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
 809         }
 810
 811         return err;
 812 }
 813
 814 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 815                                     struct snd_soc_dai *cpu_dai)
 816 {
 817         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 818         int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 819         int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
 820         int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
 821
 822         if (mcbsp->latency[stream2])
 823                 cpu_latency_qos_update_request(&mcbsp->pm_qos_req,
 824                                                mcbsp->latency[stream2]);
 825         else if (mcbsp->latency[stream1])
 826                 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
 827
 828         mcbsp->latency[stream1] = 0;
 829
 830         if (!snd_soc_dai_active(cpu_dai)) {
 831                 omap_mcbsp_free(mcbsp);
 832                 mcbsp->configured = 0;
 833         }
 834 }
 835
 836 static int omap_mcbsp_dai_prepare(struct snd_pcm_substream *substream,
 837                                   struct snd_soc_dai *cpu_dai)
 838 {
 839         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 840         struct pm_qos_request *pm_qos_req = &mcbsp->pm_qos_req;
 841         int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 842         int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
 843         int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
 844         int latency = mcbsp->latency[stream2];
 845
 846         /* Prevent omap hardware from hitting off between FIFO fills */
 847         if (!latency || mcbsp->latency[stream1] < latency)
 848                 latency = mcbsp->latency[stream1];
 849
 850         if (cpu_latency_qos_request_active(pm_qos_req))
 851                 cpu_latency_qos_update_request(pm_qos_req, latency);
 852         else if (latency)
 853                 cpu_latency_qos_add_request(pm_qos_req, latency);
 854
 855         return 0;
 856 }
 857
 858 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 859                                   struct snd_soc_dai *cpu_dai)
 860 {
 861         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 862
 863         switch (cmd) {
 864         case SNDRV_PCM_TRIGGER_START:
 865         case SNDRV_PCM_TRIGGER_RESUME:
 866         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 867                 mcbsp->active++;
 868                 omap_mcbsp_start(mcbsp, substream->stream);
 869                 break;
 870
 871         case SNDRV_PCM_TRIGGER_STOP:
 872         case SNDRV_PCM_TRIGGER_SUSPEND:
 873         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 874                 omap_mcbsp_stop(mcbsp, substream->stream);
 875                 mcbsp->active--;
 876                 break;
 877         default:
 878                 return -EINVAL;
 879         }
 880
 881         return 0;
 882 }
 883
 884 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
 885                         struct snd_pcm_substream *substream,
 886                         struct snd_soc_dai *dai)
 887 {
 888         struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
 889         struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
 890         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 891         u16 fifo_use;
 892         snd_pcm_sframes_t delay;
 893
 894         /* No need to proceed further if McBSP does not have FIFO */
 895         if (mcbsp->pdata->buffer_size == 0)
 896                 return 0;
 897
 898         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 899                 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
 900         else
 901                 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
 902
 903         /*
 904          * Divide the used locations with the channel count to get the
 905          * FIFO usage in samples (don't care about partial samples in the
 906          * buffer).
 907          */
 908         delay = fifo_use / substream->runtime->channels;
 909
 910         return delay;
 911 }
 912
 913 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 914                                     struct snd_pcm_hw_params *params,
 915                                     struct snd_soc_dai *cpu_dai)
 916 {
 917         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 918         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 919         struct snd_dmaengine_dai_dma_data *dma_data;
 920         int wlen, channels, wpf;
 921         int pkt_size = 0;
 922         unsigned int format, div, framesize, master;
 923         unsigned int buffer_size = mcbsp->pdata->buffer_size;
 924
 925         dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
 926         channels = params_channels(params);
 927
 928         switch (params_format(params)) {
 929         case SNDRV_PCM_FORMAT_S16_LE:
 930                 wlen = 16;
 931                 break;
 932         case SNDRV_PCM_FORMAT_S32_LE:
 933                 wlen = 32;
 934                 break;
 935         default:
 936                 return -EINVAL;
 937         }
 938         if (buffer_size) {
 939                 int latency;
 940
 941                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 942                         int period_words, max_thrsh;
 943                         int divider = 0;
 944
 945                         period_words = params_period_bytes(params) / (wlen / 8);
 946                         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 947                                 max_thrsh = mcbsp->max_tx_thres;
 948                         else
 949                                 max_thrsh = mcbsp->max_rx_thres;
 950                         /*
 951                          * Use sDMA packet mode if McBSP is in threshold mode:
 952                          * If period words less than the FIFO size the packet
 953                          * size is set to the number of period words, otherwise
 954                          * Look for the biggest threshold value which divides
 955                          * the period size evenly.
 956                          */
 957                         divider = period_words / max_thrsh;
 958                         if (period_words % max_thrsh)
 959                                 divider++;
 960                         while (period_words % divider &&
 961                                 divider < period_words)
 962                                 divider++;
 963                         if (divider == period_words)
 964                                 return -EINVAL;
 965
 966                         pkt_size = period_words / divider;
 967                 } else if (channels > 1) {
 968                         /* Use packet mode for non mono streams */
 969                         pkt_size = channels;
 970                 }
 971
 972                 latency = (buffer_size - pkt_size) / channels;
 973                 latency = latency * USEC_PER_SEC /
 974                           (params->rate_num / params->rate_den);
 975                 mcbsp->latency[substream->stream] = latency;
 976
 977                 omap_mcbsp_set_threshold(substream, pkt_size);
 978         }
 979
 980         dma_data->maxburst = pkt_size;
 981
 982         if (mcbsp->configured) {
 983                 /* McBSP already configured by another stream */
 984                 return 0;
 985         }
 986
 987         regs->rcr2      &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
 988         regs->xcr2      &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
 989         regs->rcr1      &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
 990         regs->xcr1      &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
 991         format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 992         wpf = channels;
 993         if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
 994                               format == SND_SOC_DAIFMT_LEFT_J)) {
 995                 /* Use dual-phase frames */
 996                 regs->rcr2      |= RPHASE;
 997                 regs->xcr2      |= XPHASE;
 998                 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
 999                 wpf--;
1000                 regs->rcr2      |= RFRLEN2(wpf - 1);
1001                 regs->xcr2      |= XFRLEN2(wpf - 1);
1002         }
1003
1004         regs->rcr1      |= RFRLEN1(wpf - 1);
1005         regs->xcr1      |= XFRLEN1(wpf - 1);
1006
1007         switch (params_format(params)) {
1008         case SNDRV_PCM_FORMAT_S16_LE:
1009                 /* Set word lengths */
1010                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
1011                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
1012                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
1013                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
1014                 break;
1015         case SNDRV_PCM_FORMAT_S32_LE:
1016                 /* Set word lengths */
1017                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_32);
1018                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_32);
1019                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_32);
1020                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_32);
1021                 break;
1022         default:
1023                 /* Unsupported PCM format */
1024                 return -EINVAL;
1025         }
1026
1027         /* In McBSP master modes, FRAME (i.e. sample rate) is generated
1028          * by _counting_ BCLKs. Calculate frame size in BCLKs */
1029         master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
1030         if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
1031                 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
1032                 framesize = (mcbsp->in_freq / div) / params_rate(params);
1033
1034                 if (framesize < wlen * channels) {
1035                         printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
1036                                         "channels\n", __func__);
1037                         return -EINVAL;
1038                 }
1039         } else
1040                 framesize = wlen * channels;
1041
1042         /* Set FS period and length in terms of bit clock periods */
1043         regs->srgr2     &= ~FPER(0xfff);
1044         regs->srgr1     &= ~FWID(0xff);
1045         switch (format) {
1046         case SND_SOC_DAIFMT_I2S:
1047         case SND_SOC_DAIFMT_LEFT_J:
1048                 regs->srgr2     |= FPER(framesize - 1);
1049                 regs->srgr1     |= FWID((framesize >> 1) - 1);
1050                 break;
1051         case SND_SOC_DAIFMT_DSP_A:
1052         case SND_SOC_DAIFMT_DSP_B:
1053                 regs->srgr2     |= FPER(framesize - 1);
1054                 regs->srgr1     |= FWID(0);
1055                 break;
1056         }
1057
1058         omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
1059         mcbsp->wlen = wlen;
1060         mcbsp->configured = 1;
1061
1062         return 0;
1063 }
1064
1065 /*
1066  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
1067  * cache is initialized here
1068  */
1069 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
1070                                       unsigned int fmt)
1071 {
1072         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1073         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1074         bool inv_fs = false;
1075
1076         if (mcbsp->configured)
1077                 return 0;
1078
1079         mcbsp->fmt = fmt;
1080         memset(regs, 0, sizeof(*regs));
1081         /* Generic McBSP register settings */
1082         regs->spcr2     |= XINTM(3) | FREE;
1083         regs->spcr1     |= RINTM(3);
1084         /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
1085         if (!mcbsp->pdata->has_ccr) {
1086                 regs->rcr2      |= RFIG;
1087                 regs->xcr2      |= XFIG;
1088         }
1089
1090         /* Configure XCCR/RCCR only for revisions which have ccr registers */
1091         if (mcbsp->pdata->has_ccr) {
1092                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
1093                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
1094         }
1095
1096         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1097         case SND_SOC_DAIFMT_I2S:
1098                 /* 1-bit data delay */
1099                 regs->rcr2      |= RDATDLY(1);
1100                 regs->xcr2      |= XDATDLY(1);
1101                 break;
1102         case SND_SOC_DAIFMT_LEFT_J:
1103                 /* 0-bit data delay */
1104                 regs->rcr2      |= RDATDLY(0);
1105                 regs->xcr2      |= XDATDLY(0);
1106                 regs->spcr1     |= RJUST(2);
1107                 /* Invert FS polarity configuration */
1108                 inv_fs = true;
1109                 break;
1110         case SND_SOC_DAIFMT_DSP_A:
1111                 /* 1-bit data delay */
1112                 regs->rcr2      |= RDATDLY(1);
1113                 regs->xcr2      |= XDATDLY(1);
1114                 /* Invert FS polarity configuration */
1115                 inv_fs = true;
1116                 break;
1117         case SND_SOC_DAIFMT_DSP_B:
1118                 /* 0-bit data delay */
1119                 regs->rcr2      |= RDATDLY(0);
1120                 regs->xcr2      |= XDATDLY(0);
1121                 /* Invert FS polarity configuration */
1122                 inv_fs = true;
1123                 break;
1124         default:
1125                 /* Unsupported data format */
1126                 return -EINVAL;
1127         }
1128
1129         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1130         case SND_SOC_DAIFMT_CBS_CFS:
1131                 /* McBSP master. Set FS and bit clocks as outputs */
1132                 regs->pcr0      |= FSXM | FSRM |
1133                                    CLKXM | CLKRM;
1134                 /* Sample rate generator drives the FS */
1135                 regs->srgr2     |= FSGM;
1136                 break;
1137         case SND_SOC_DAIFMT_CBM_CFS:
1138                 /* McBSP slave. FS clock as output */
1139                 regs->srgr2     |= FSGM;
1140                 regs->pcr0      |= FSXM | FSRM;
1141                 break;
1142         case SND_SOC_DAIFMT_CBM_CFM:
1143                 /* McBSP slave */
1144                 break;
1145         default:
1146                 /* Unsupported master/slave configuration */
1147                 return -EINVAL;
1148         }
1149
1150         /* Set bit clock (CLKX/CLKR) and FS polarities */
1151         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1152         case SND_SOC_DAIFMT_NB_NF:
1153                 /*
1154                  * Normal BCLK + FS.
1155                  * FS active low. TX data driven on falling edge of bit clock
1156                  * and RX data sampled on rising edge of bit clock.
1157                  */
1158                 regs->pcr0      |= FSXP | FSRP |
1159                                    CLKXP | CLKRP;
1160                 break;
1161         case SND_SOC_DAIFMT_NB_IF:
1162                 regs->pcr0      |= CLKXP | CLKRP;
1163                 break;
1164         case SND_SOC_DAIFMT_IB_NF:
1165                 regs->pcr0      |= FSXP | FSRP;
1166                 break;
1167         case SND_SOC_DAIFMT_IB_IF:
1168                 break;
1169         default:
1170                 return -EINVAL;
1171         }
1172         if (inv_fs)
1173                 regs->pcr0 ^= FSXP | FSRP;
1174
1175         return 0;
1176 }
1177
1178 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
1179                                      int div_id, int div)
1180 {
1181         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1182         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1183
1184         if (div_id != OMAP_MCBSP_CLKGDV)
1185                 return -ENODEV;
1186
1187         mcbsp->clk_div = div;
1188         regs->srgr1     &= ~CLKGDV(0xff);
1189         regs->srgr1     |= CLKGDV(div - 1);
1190
1191         return 0;
1192 }
1193
1194 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
1195                                          int clk_id, unsigned int freq,
1196                                          int dir)
1197 {
1198         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1199         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1200         int err = 0;
1201
1202         if (mcbsp->active) {
1203                 if (freq == mcbsp->in_freq)
1204                         return 0;
1205                 else
1206                         return -EBUSY;
1207         }
1208
1209         mcbsp->in_freq = freq;
1210         regs->srgr2 &= ~CLKSM;
1211         regs->pcr0 &= ~SCLKME;
1212
1213         switch (clk_id) {
1214         case OMAP_MCBSP_SYSCLK_CLK:
1215                 regs->srgr2     |= CLKSM;
1216                 break;
1217         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
1218                 if (mcbsp_omap1()) {
1219                         err = -EINVAL;
1220                         break;
1221                 }
1222                 err = omap2_mcbsp_set_clks_src(mcbsp,
1223                                                MCBSP_CLKS_PRCM_SRC);
1224                 break;
1225         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
1226                 if (mcbsp_omap1()) {
1227                         err = 0;
1228                         break;
1229                 }
1230                 err = omap2_mcbsp_set_clks_src(mcbsp,
1231                                                MCBSP_CLKS_PAD_SRC);
1232                 break;
1233
1234         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
1235                 regs->srgr2     |= CLKSM;
1236                 regs->pcr0      |= SCLKME;
1237                 /*
1238                  * If McBSP is master but yet the CLKX/CLKR pin drives the SRG,
1239                  * disable output on those pins. This enables to inject the
1240                  * reference clock through CLKX/CLKR. For this to work
1241                  * set_dai_sysclk() _needs_ to be called after set_dai_fmt().
1242                  */
1243                 regs->pcr0      &= ~CLKXM;
1244                 break;
1245         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
1246                 regs->pcr0      |= SCLKME;
1247                 /* Disable ouput on CLKR pin in master mode */
1248                 regs->pcr0      &= ~CLKRM;
1249                 break;
1250         default:
1251                 err = -ENODEV;
1252         }
1253
1254         return err;
1255 }
1256
1257 static const struct snd_soc_dai_ops mcbsp_dai_ops = {
1258         .startup        = omap_mcbsp_dai_startup,
1259         .shutdown       = omap_mcbsp_dai_shutdown,
1260         .prepare        = omap_mcbsp_dai_prepare,
1261         .trigger        = omap_mcbsp_dai_trigger,
1262         .delay          = omap_mcbsp_dai_delay,
1263         .hw_params      = omap_mcbsp_dai_hw_params,
1264         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
1265         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
1266         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
1267 };
1268
1269 static int omap_mcbsp_probe(struct snd_soc_dai *dai)
1270 {
1271         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1272
1273         pm_runtime_enable(mcbsp->dev);
1274
1275         snd_soc_dai_init_dma_data(dai,
1276                                   &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
1277                                   &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
1278
1279         return 0;
1280 }
1281
1282 static int omap_mcbsp_remove(struct snd_soc_dai *dai)
1283 {
1284         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1285
1286         pm_runtime_disable(mcbsp->dev);
1287
1288         return 0;
1289 }
1290
1291 static struct snd_soc_dai_driver omap_mcbsp_dai = {
1292         .probe = omap_mcbsp_probe,
1293         .remove = omap_mcbsp_remove,
1294         .playback = {
1295                 .channels_min = 1,
1296                 .channels_max = 16,
1297                 .rates = OMAP_MCBSP_RATES,
1298                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1299         },
1300         .capture = {
1301                 .channels_min = 1,
1302                 .channels_max = 16,
1303                 .rates = OMAP_MCBSP_RATES,
1304                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1305         },
1306         .ops = &mcbsp_dai_ops,
1307 };
1308
1309 static const struct snd_soc_component_driver omap_mcbsp_component = {
1310         .name           = "omap-mcbsp",
1311 };
1312
1313 static struct omap_mcbsp_platform_data omap2420_pdata = {
1314         .reg_step = 4,
1315         .reg_size = 2,
1316 };
1317
1318 static struct omap_mcbsp_platform_data omap2430_pdata = {
1319         .reg_step = 4,
1320         .reg_size = 4,
1321         .has_ccr = true,
1322 };
1323
1324 static struct omap_mcbsp_platform_data omap3_pdata = {
1325         .reg_step = 4,
1326         .reg_size = 4,
1327         .has_ccr = true,
1328         .has_wakeup = true,
1329 };
1330
1331 static struct omap_mcbsp_platform_data omap4_pdata = {
1332         .reg_step = 4,
1333         .reg_size = 4,
1334         .has_ccr = true,
1335         .has_wakeup = true,
1336 };
1337
1338 static const struct of_device_id omap_mcbsp_of_match[] = {
1339         {
1340                 .compatible = "ti,omap2420-mcbsp",
1341                 .data = &omap2420_pdata,
1342         },
1343         {
1344                 .compatible = "ti,omap2430-mcbsp",
1345                 .data = &omap2430_pdata,
1346         },
1347         {
1348                 .compatible = "ti,omap3-mcbsp",
1349                 .data = &omap3_pdata,
1350         },
1351         {
1352                 .compatible = "ti,omap4-mcbsp",
1353                 .data = &omap4_pdata,
1354         },
1355         { },
1356 };
1357 MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
1358
1359 static int asoc_mcbsp_probe(struct platform_device *pdev)
1360 {
1361         struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
1362         struct omap_mcbsp *mcbsp;
1363         const struct of_device_id *match;
1364         int ret;
1365
1366         match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
1367         if (match) {
1368                 struct device_node *node = pdev->dev.of_node;
1369                 struct omap_mcbsp_platform_data *pdata_quirk = pdata;
1370                 int buffer_size;
1371
1372                 pdata = devm_kzalloc(&pdev->dev,
1373                                      sizeof(struct omap_mcbsp_platform_data),
1374                                      GFP_KERNEL);
1375                 if (!pdata)
1376                         return -ENOMEM;
1377
1378                 memcpy(pdata, match->data, sizeof(*pdata));
1379                 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
1380                         pdata->buffer_size = buffer_size;
1381                 if (pdata_quirk)
1382                         pdata->force_ick_on = pdata_quirk->force_ick_on;
1383         } else if (!pdata) {
1384                 dev_err(&pdev->dev, "missing platform data.\n");
1385                 return -EINVAL;
1386         }
1387         mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
1388         if (!mcbsp)
1389                 return -ENOMEM;
1390
1391         mcbsp->id = pdev->id;
1392         mcbsp->pdata = pdata;
1393         mcbsp->dev = &pdev->dev;
1394         platform_set_drvdata(pdev, mcbsp);
1395
1396         ret = omap_mcbsp_init(pdev);
1397         if (ret)
1398                 return ret;
1399
1400         if (mcbsp->pdata->reg_size == 2) {
1401                 omap_mcbsp_dai.playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
1402                 omap_mcbsp_dai.capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
1403         }
1404
1405         ret = devm_snd_soc_register_component(&pdev->dev,
1406                                               &omap_mcbsp_component,
1407                                               &omap_mcbsp_dai, 1);
1408         if (ret)
1409                 return ret;
1410
1411         return sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
1412 }
1413
1414 static int asoc_mcbsp_remove(struct platform_device *pdev)
1415 {
1416         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1417
1418         if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
1419                 mcbsp->pdata->ops->free(mcbsp->id);
1420
1421         if (cpu_latency_qos_request_active(&mcbsp->pm_qos_req))
1422                 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
1423
1424         return 0;
1425 }
1426
1427 static struct platform_driver asoc_mcbsp_driver = {
1428         .driver = {
1429                         .name = "omap-mcbsp",
1430                         .of_match_table = omap_mcbsp_of_match,
1431         },
1432
1433         .probe = asoc_mcbsp_probe,
1434         .remove = asoc_mcbsp_remove,
1435 };
1436
1437 module_platform_driver(asoc_mcbsp_driver);
1438
1439 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
1440 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
1441 MODULE_LICENSE("GPL");
1442 MODULE_ALIAS("platform:omap-mcbsp");