1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap-dmic.c -- OMAP ASoC DMIC DAI driver
5 * Copyright (C) 2010 - 2011 Texas Instruments
7 * Author: David Lambert <dlambert@ti.com>
8 * Misael Lopez Cruz <misael.lopez@ti.com>
9 * Liam Girdwood <lrg@ti.com>
10 * Peter Ujfalusi <peter.ujfalusi@ti.com>
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
19 #include <linux/slab.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/of_device.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/initval.h>
27 #include <sound/soc.h>
28 #include <sound/dmaengine_pcm.h>
30 #include "omap-dmic.h"
35 void __iomem *io_base;
37 struct pm_qos_request pm_qos_req;
48 struct snd_dmaengine_dai_dma_data dma_data;
51 static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
53 writel_relaxed(val, dmic->io_base + reg);
56 static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
58 return readl_relaxed(dmic->io_base + reg);
61 static inline void omap_dmic_start(struct omap_dmic *dmic)
63 u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
65 /* Configure DMA controller */
66 omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG,
67 OMAP_DMIC_DMA_ENABLE);
69 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled);
72 static inline void omap_dmic_stop(struct omap_dmic *dmic)
74 u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
75 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
76 ctrl & ~OMAP_DMIC_UP_ENABLE_MASK);
78 /* Disable DMA request generation */
79 omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG,
80 OMAP_DMIC_DMA_ENABLE);
84 static inline int dmic_is_enabled(struct omap_dmic *dmic)
86 return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) &
87 OMAP_DMIC_UP_ENABLE_MASK;
90 static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
91 struct snd_soc_dai *dai)
93 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
96 mutex_lock(&dmic->mutex);
103 mutex_unlock(&dmic->mutex);
108 static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream,
109 struct snd_soc_dai *dai)
111 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
113 mutex_lock(&dmic->mutex);
115 pm_qos_remove_request(&dmic->pm_qos_req);
120 mutex_unlock(&dmic->mutex);
123 static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate)
125 int divider = -EINVAL;
128 * 192KHz rate is only supported with 19.2MHz/3.84MHz clock
131 if (sample_rate == 192000) {
132 if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000)
133 divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
136 "invalid clock configuration for 192KHz\n");
141 switch (dmic->out_freq) {
143 if (dmic->fclk_freq != 24576000)
145 divider = 0x4; /* Divider: 16 */
148 switch (dmic->fclk_freq) {
150 divider = 0x5; /* Divider: 5 */
153 divider = 0x0; /* Divider: 8 */
156 divider = 0x2; /* Divider: 10 */
163 if (dmic->fclk_freq != 24576000)
165 divider = 0x3; /* Divider: 8 */
168 if (dmic->fclk_freq != 19200000)
170 divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
173 dev_err(dmic->dev, "invalid out frequency: %dHz\n",
181 dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n",
182 dmic->out_freq, dmic->fclk_freq);
186 static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream,
187 struct snd_pcm_hw_params *params,
188 struct snd_soc_dai *dai)
190 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
191 struct snd_dmaengine_dai_dma_data *dma_data;
194 dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params));
195 if (dmic->clk_div < 0) {
196 dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n",
197 dmic->out_freq, dmic->fclk_freq);
201 dmic->ch_enabled = 0;
202 channels = params_channels(params);
205 dmic->ch_enabled |= OMAP_DMIC_UP3_ENABLE;
208 dmic->ch_enabled |= OMAP_DMIC_UP2_ENABLE;
211 dmic->ch_enabled |= OMAP_DMIC_UP1_ENABLE;
214 dev_err(dmic->dev, "invalid number of legacy channels\n");
218 /* packet size is threshold * channels */
219 dma_data = snd_soc_dai_get_dma_data(dai, substream);
220 dma_data->maxburst = dmic->threshold * channels;
221 dmic->latency = (OMAP_DMIC_THRES_MAX - dmic->threshold) * USEC_PER_SEC /
227 static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream,
228 struct snd_soc_dai *dai)
230 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
233 if (pm_qos_request_active(&dmic->pm_qos_req))
234 pm_qos_update_request(&dmic->pm_qos_req, dmic->latency);
236 /* Configure uplink threshold */
237 omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold);
239 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
241 /* Set dmic out format */
242 ctrl &= ~(OMAP_DMIC_FORMAT | OMAP_DMIC_POLAR_MASK);
243 ctrl |= (OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
244 OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
246 /* Configure dmic clock divider */
247 ctrl &= ~OMAP_DMIC_CLK_DIV_MASK;
248 ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div);
250 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl);
252 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
253 ctrl | OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
254 OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
259 static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream,
260 int cmd, struct snd_soc_dai *dai)
262 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
265 case SNDRV_PCM_TRIGGER_START:
266 omap_dmic_start(dmic);
268 case SNDRV_PCM_TRIGGER_STOP:
269 omap_dmic_stop(dmic);
278 static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id,
281 struct clk *parent_clk, *mux;
282 char *parent_clk_name;
292 dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq);
297 if (dmic->sysclk == clk_id) {
298 dmic->fclk_freq = freq;
302 /* re-parent not allowed if a stream is ongoing */
303 if (dmic->active && dmic_is_enabled(dmic)) {
304 dev_err(dmic->dev, "can't re-parent when DMIC active\n");
309 case OMAP_DMIC_SYSCLK_PAD_CLKS:
310 parent_clk_name = "pad_clks_ck";
312 case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS:
313 parent_clk_name = "slimbus_clk";
315 case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS:
316 parent_clk_name = "dmic_sync_mux_ck";
319 dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
323 parent_clk = clk_get(dmic->dev, parent_clk_name);
324 if (IS_ERR(parent_clk)) {
325 dev_err(dmic->dev, "can't get %s\n", parent_clk_name);
329 mux = clk_get_parent(dmic->fclk);
331 dev_err(dmic->dev, "can't get fck mux parent\n");
336 mutex_lock(&dmic->mutex);
338 /* disable clock while reparenting */
339 pm_runtime_put_sync(dmic->dev);
340 ret = clk_set_parent(mux, parent_clk);
341 pm_runtime_get_sync(dmic->dev);
343 ret = clk_set_parent(mux, parent_clk);
345 mutex_unlock(&dmic->mutex);
348 dev_err(dmic->dev, "re-parent failed\n");
352 dmic->sysclk = clk_id;
353 dmic->fclk_freq = freq;
362 static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id,
367 if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) {
368 dev_err(dmic->dev, "output clk_id (%d) not supported\n",
378 dmic->out_freq = freq;
381 dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq);
389 static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
390 unsigned int freq, int dir)
392 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
394 if (dir == SND_SOC_CLOCK_IN)
395 return omap_dmic_select_fclk(dmic, clk_id, freq);
396 else if (dir == SND_SOC_CLOCK_OUT)
397 return omap_dmic_select_outclk(dmic, clk_id, freq);
399 dev_err(dmic->dev, "invalid clock direction (%d)\n", dir);
403 static const struct snd_soc_dai_ops omap_dmic_dai_ops = {
404 .startup = omap_dmic_dai_startup,
405 .shutdown = omap_dmic_dai_shutdown,
406 .hw_params = omap_dmic_dai_hw_params,
407 .prepare = omap_dmic_dai_prepare,
408 .trigger = omap_dmic_dai_trigger,
409 .set_sysclk = omap_dmic_set_dai_sysclk,
412 static int omap_dmic_probe(struct snd_soc_dai *dai)
414 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
416 pm_runtime_enable(dmic->dev);
418 /* Disable lines while request is ongoing */
419 pm_runtime_get_sync(dmic->dev);
420 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00);
421 pm_runtime_put_sync(dmic->dev);
423 /* Configure DMIC threshold value */
424 dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
426 snd_soc_dai_init_dma_data(dai, NULL, &dmic->dma_data);
431 static int omap_dmic_remove(struct snd_soc_dai *dai)
433 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
435 pm_runtime_disable(dmic->dev);
440 static struct snd_soc_dai_driver omap_dmic_dai = {
442 .probe = omap_dmic_probe,
443 .remove = omap_dmic_remove,
447 .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
448 .formats = SNDRV_PCM_FMTBIT_S32_LE,
451 .ops = &omap_dmic_dai_ops,
454 static const struct snd_soc_component_driver omap_dmic_component = {
458 static int asoc_dmic_probe(struct platform_device *pdev)
460 struct omap_dmic *dmic;
461 struct resource *res;
464 dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
468 platform_set_drvdata(pdev, dmic);
469 dmic->dev = &pdev->dev;
470 dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS;
472 mutex_init(&dmic->mutex);
474 dmic->fclk = devm_clk_get(dmic->dev, "fck");
475 if (IS_ERR(dmic->fclk)) {
476 dev_err(dmic->dev, "cant get fck\n");
480 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
482 dev_err(dmic->dev, "invalid dma memory resource\n");
485 dmic->dma_data.addr = res->start + OMAP_DMIC_DATA_REG;
487 dmic->dma_data.filter_data = "up_link";
489 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
490 dmic->io_base = devm_ioremap_resource(&pdev->dev, res);
491 if (IS_ERR(dmic->io_base))
492 return PTR_ERR(dmic->io_base);
495 ret = devm_snd_soc_register_component(&pdev->dev,
496 &omap_dmic_component,
501 ret = sdma_pcm_platform_register(&pdev->dev, NULL, "up_link");
508 static const struct of_device_id omap_dmic_of_match[] = {
509 { .compatible = "ti,omap4-dmic", },
512 MODULE_DEVICE_TABLE(of, omap_dmic_of_match);
514 static struct platform_driver asoc_dmic_driver = {
517 .of_match_table = omap_dmic_of_match,
519 .probe = asoc_dmic_probe,
522 module_platform_driver(asoc_dmic_driver);
524 MODULE_ALIAS("platform:omap-dmic");
525 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
526 MODULE_DESCRIPTION("OMAP DMIC ASoC Interface");
527 MODULE_LICENSE("GPL");