2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 * Multi-channel Audio Serial Port Driver
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
29 #include <linux/platform_data/davinci_asp.h>
30 #include <linux/math64.h>
31 #include <linux/bitmap.h>
33 #include <sound/asoundef.h>
34 #include <sound/core.h>
35 #include <sound/pcm.h>
36 #include <sound/pcm_params.h>
37 #include <sound/initval.h>
38 #include <sound/soc.h>
39 #include <sound/dmaengine_pcm.h>
43 #include "davinci-mcasp.h"
45 #define MCASP_MAX_AFIFO_DEPTH 64
47 static u32 context_regs[] = {
48 DAVINCI_MCASP_TXFMCTL_REG,
49 DAVINCI_MCASP_RXFMCTL_REG,
50 DAVINCI_MCASP_TXFMT_REG,
51 DAVINCI_MCASP_RXFMT_REG,
52 DAVINCI_MCASP_ACLKXCTL_REG,
53 DAVINCI_MCASP_ACLKRCTL_REG,
54 DAVINCI_MCASP_AHCLKXCTL_REG,
55 DAVINCI_MCASP_AHCLKRCTL_REG,
56 DAVINCI_MCASP_PDIR_REG,
57 DAVINCI_MCASP_RXMASK_REG,
58 DAVINCI_MCASP_TXMASK_REG,
59 DAVINCI_MCASP_RXTDM_REG,
60 DAVINCI_MCASP_TXTDM_REG,
63 struct davinci_mcasp_context {
64 u32 config_regs[ARRAY_SIZE(context_regs)];
65 u32 afifo_regs[2]; /* for read/write fifo control registers */
66 u32 *xrsr_regs; /* for serializer configuration */
70 struct davinci_mcasp_ruledata {
71 struct davinci_mcasp *mcasp;
75 struct davinci_mcasp {
76 struct snd_dmaengine_dai_dma_data dma_data[2];
80 struct snd_pcm_substream *substreams[2];
83 /* McASP specific data */
100 unsigned long pdir; /* Pin direction bitfield */
102 /* McASP FIFO related */
108 /* Used for comstraint setting on the second stream */
112 struct davinci_mcasp_context context;
115 struct davinci_mcasp_ruledata ruledata[2];
116 struct snd_pcm_hw_constraint_list chconstr[2];
119 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
122 void __iomem *reg = mcasp->base + offset;
123 __raw_writel(__raw_readl(reg) | val, reg);
126 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
129 void __iomem *reg = mcasp->base + offset;
130 __raw_writel((__raw_readl(reg) & ~(val)), reg);
133 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
136 void __iomem *reg = mcasp->base + offset;
137 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
140 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
143 __raw_writel(val, mcasp->base + offset);
146 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
148 return (u32)__raw_readl(mcasp->base + offset);
151 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
155 mcasp_set_bits(mcasp, ctl_reg, val);
157 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
158 /* loop count is to avoid the lock-up */
159 for (i = 0; i < 1000; i++) {
160 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
164 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
165 printk(KERN_ERR "GBLCTL write error\n");
168 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
170 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
171 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
173 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
176 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
178 u32 bit = PIN_BIT_AMUTE;
180 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
182 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
184 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
188 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
192 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AFSR) {
194 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
196 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
200 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
202 if (mcasp->rxnumevt) { /* enable FIFO */
203 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
205 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
206 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
210 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
211 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
213 * When ASYNC == 0 the transmit and receive sections operate
214 * synchronously from the transmit clock and frame sync. We need to make
215 * sure that the TX signlas are enabled when starting reception.
217 if (mcasp_is_synchronous(mcasp)) {
218 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
219 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
222 /* Activate serializer(s) */
223 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
224 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
225 /* Release RX state machine */
226 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
227 /* Release Frame Sync generator */
228 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
229 if (mcasp_is_synchronous(mcasp))
230 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
232 /* enable receive IRQs */
233 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
234 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
237 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
241 if (mcasp->txnumevt) { /* enable FIFO */
242 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
244 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
245 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
249 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
250 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
251 mcasp_set_clk_pdir(mcasp, true);
253 /* Activate serializer(s) */
254 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
255 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
257 /* wait for XDATA to be cleared */
259 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
263 mcasp_set_axr_pdir(mcasp, true);
265 /* Release TX state machine */
266 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
267 /* Release Frame Sync generator */
268 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
270 /* enable transmit IRQs */
271 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
272 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
275 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
279 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
280 mcasp_start_tx(mcasp);
282 mcasp_start_rx(mcasp);
285 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
287 /* disable IRQ sources */
288 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
289 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
292 * In synchronous mode stop the TX clocks if no other stream is
295 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
296 mcasp_set_clk_pdir(mcasp, false);
297 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
300 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
301 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
303 if (mcasp->rxnumevt) { /* disable FIFO */
304 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
306 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
310 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
314 /* disable IRQ sources */
315 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
316 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
319 * In synchronous mode keep TX clocks running if the capture stream is
322 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
323 val = TXHCLKRST | TXCLKRST | TXFSRST;
325 mcasp_set_clk_pdir(mcasp, false);
328 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
329 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
331 if (mcasp->txnumevt) { /* disable FIFO */
332 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
334 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
337 mcasp_set_axr_pdir(mcasp, false);
340 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
344 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
345 mcasp_stop_tx(mcasp);
347 mcasp_stop_rx(mcasp);
350 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
352 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
353 struct snd_pcm_substream *substream;
354 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
355 u32 handled_mask = 0;
358 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
359 if (stat & XUNDRN & irq_mask) {
360 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
361 handled_mask |= XUNDRN;
363 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
365 snd_pcm_stop_xrun(substream);
369 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
373 handled_mask |= XRERR;
375 /* Ack the handled event only */
376 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
378 return IRQ_RETVAL(handled_mask);
381 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
383 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
384 struct snd_pcm_substream *substream;
385 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
386 u32 handled_mask = 0;
389 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
390 if (stat & ROVRN & irq_mask) {
391 dev_warn(mcasp->dev, "Receive buffer overflow\n");
392 handled_mask |= ROVRN;
394 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
396 snd_pcm_stop_xrun(substream);
400 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
404 handled_mask |= XRERR;
406 /* Ack the handled event only */
407 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
409 return IRQ_RETVAL(handled_mask);
412 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
414 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
415 irqreturn_t ret = IRQ_NONE;
417 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
418 ret = davinci_mcasp_tx_irq_handler(irq, data);
420 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
421 ret |= davinci_mcasp_rx_irq_handler(irq, data);
426 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
429 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
438 pm_runtime_get_sync(mcasp->dev);
439 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
440 case SND_SOC_DAIFMT_DSP_A:
441 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
442 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
443 /* 1st data bit occur one ACLK cycle after the frame sync */
446 case SND_SOC_DAIFMT_DSP_B:
447 case SND_SOC_DAIFMT_AC97:
448 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
449 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
450 /* No delay after FS */
453 case SND_SOC_DAIFMT_I2S:
454 /* configure a full-word SYNC pulse (LRCLK) */
455 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
456 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
457 /* 1st data bit occur one ACLK cycle after the frame sync */
459 /* FS need to be inverted */
462 case SND_SOC_DAIFMT_LEFT_J:
463 /* configure a full-word SYNC pulse (LRCLK) */
464 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
465 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
466 /* No delay after FS */
474 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
476 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
479 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
480 case SND_SOC_DAIFMT_CBS_CFS:
481 /* codec is clock and frame slave */
482 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
483 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
485 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
486 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
489 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
490 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
492 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
493 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
495 mcasp->bclk_master = 1;
497 case SND_SOC_DAIFMT_CBS_CFM:
498 /* codec is clock slave and frame master */
499 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
500 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
502 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
503 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
506 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
507 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
509 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
510 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
512 mcasp->bclk_master = 1;
514 case SND_SOC_DAIFMT_CBM_CFS:
515 /* codec is clock master and frame slave */
516 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
517 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
519 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
520 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
523 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
524 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
526 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
527 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
529 mcasp->bclk_master = 0;
531 case SND_SOC_DAIFMT_CBM_CFM:
532 /* codec is clock and frame master */
533 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
534 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
536 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
537 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
540 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
541 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
543 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
544 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
546 mcasp->bclk_master = 0;
553 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
554 case SND_SOC_DAIFMT_IB_NF:
555 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
556 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
557 fs_pol_rising = true;
559 case SND_SOC_DAIFMT_NB_IF:
560 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
561 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
562 fs_pol_rising = false;
564 case SND_SOC_DAIFMT_IB_IF:
565 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
566 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
567 fs_pol_rising = false;
569 case SND_SOC_DAIFMT_NB_NF:
570 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
571 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
572 fs_pol_rising = true;
580 fs_pol_rising = !fs_pol_rising;
583 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
584 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
586 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
587 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
590 mcasp->dai_fmt = fmt;
592 pm_runtime_put(mcasp->dev);
596 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
597 int div, bool explicit)
599 pm_runtime_get_sync(mcasp->dev);
601 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
602 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
603 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
604 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
605 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
608 case MCASP_CLKDIV_BCLK: /* BCLK divider */
609 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
610 ACLKXDIV(div - 1), ACLKXDIV_MASK);
611 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
612 ACLKRDIV(div - 1), ACLKRDIV_MASK);
614 mcasp->bclk_div = div;
617 case MCASP_CLKDIV_BCLK_FS_RATIO:
619 * BCLK/LRCLK ratio descries how many bit-clock cycles
620 * fit into one frame. The clock ratio is given for a
621 * full period of data (for I2S format both left and
622 * right channels), so it has to be divided by number
623 * of tdm-slots (for I2S - divided by 2).
624 * Instead of storing this ratio, we calculate a new
625 * tdm_slot width by dividing the the ratio by the
626 * number of configured tdm slots.
628 mcasp->slot_width = div / mcasp->tdm_slots;
629 if (div % mcasp->tdm_slots)
631 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
632 __func__, div, mcasp->tdm_slots);
639 pm_runtime_put(mcasp->dev);
643 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
646 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
648 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
651 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
652 unsigned int freq, int dir)
654 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
656 pm_runtime_get_sync(mcasp->dev);
657 if (dir == SND_SOC_CLOCK_OUT) {
658 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
659 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
660 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
662 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
663 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
664 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
667 mcasp->sysclk_freq = freq;
669 pm_runtime_put(mcasp->dev);
673 /* All serializers must have equal number of channels */
674 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
677 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
678 unsigned int *list = (unsigned int *) cl->list;
679 int slots = mcasp->tdm_slots;
682 if (mcasp->tdm_mask[stream])
683 slots = hweight32(mcasp->tdm_mask[stream]);
685 for (i = 1; i <= slots; i++)
688 for (i = 2; i <= serializers; i++)
689 list[count++] = i*slots;
696 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
698 int rx_serializers = 0, tx_serializers = 0, ret, i;
700 for (i = 0; i < mcasp->num_serializer; i++)
701 if (mcasp->serial_dir[i] == TX_MODE)
703 else if (mcasp->serial_dir[i] == RX_MODE)
706 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
711 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
718 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
719 unsigned int tx_mask,
720 unsigned int rx_mask,
721 int slots, int slot_width)
723 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
726 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
727 __func__, tx_mask, rx_mask, slots, slot_width);
729 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
731 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
732 tx_mask, rx_mask, slots);
737 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
738 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
739 __func__, slot_width);
743 mcasp->tdm_slots = slots;
744 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
745 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
746 mcasp->slot_width = slot_width;
748 return davinci_mcasp_set_ch_constraints(mcasp);
751 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
755 u32 tx_rotate = (sample_width / 4) & 0x7;
756 u32 mask = (1ULL << sample_width) - 1;
757 u32 slot_width = sample_width;
760 * For captured data we should not rotate, inversion and masking is
761 * enoguh to get the data to the right position:
762 * Format data from bus after reverse (XRBUF)
763 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
764 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
765 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
766 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
771 * Setting the tdm slot width either with set_clkdiv() or
772 * set_tdm_slot() allows us to for example send 32 bits per
773 * channel to the codec, while only 16 of them carry audio
776 if (mcasp->slot_width) {
778 * When we have more bclk then it is needed for the
779 * data, we need to use the rotation to move the
780 * received samples to have correct alignment.
782 slot_width = mcasp->slot_width;
783 rx_rotate = (slot_width - sample_width) / 4;
786 /* mapping of the XSSZ bit-field as described in the datasheet */
787 fmt = (slot_width >> 1) - 1;
789 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
790 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
792 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
794 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
796 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
798 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
801 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
806 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
807 int period_words, int channels)
809 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
813 u8 slots = mcasp->tdm_slots;
814 u8 max_active_serializers = (channels + slots - 1) / slots;
815 int active_serializers, numevt;
817 /* Default configuration */
818 if (mcasp->version < MCASP_VERSION_3)
819 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
821 /* All PINS as McASP */
822 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
824 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
825 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
826 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
828 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
829 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
832 for (i = 0; i < mcasp->num_serializer; i++) {
833 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
834 mcasp->serial_dir[i]);
835 if (mcasp->serial_dir[i] == TX_MODE &&
836 tx_ser < max_active_serializers) {
837 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
838 mcasp->dismod, DISMOD_MASK);
839 set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
841 } else if (mcasp->serial_dir[i] == RX_MODE &&
842 rx_ser < max_active_serializers) {
843 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
845 } else if (mcasp->serial_dir[i] == INACTIVE_MODE) {
846 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
847 SRMOD_INACTIVE, SRMOD_MASK);
848 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
849 } else if (mcasp->serial_dir[i] == TX_MODE) {
850 /* Unused TX pins, clear PDIR */
851 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
852 mcasp->dismod, DISMOD_MASK);
853 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
857 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
858 active_serializers = tx_ser;
859 numevt = mcasp->txnumevt;
860 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
862 active_serializers = rx_ser;
863 numevt = mcasp->rxnumevt;
864 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
867 if (active_serializers < max_active_serializers) {
868 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
869 "enabled in mcasp (%d)\n", channels,
870 active_serializers * slots);
874 /* AFIFO is not in use */
876 /* Configure the burst size for platform drivers */
877 if (active_serializers > 1) {
879 * If more than one serializers are in use we have one
880 * DMA request to provide data for all serializers.
881 * For example if three serializers are enabled the DMA
882 * need to transfer three words per DMA request.
884 dma_data->maxburst = active_serializers;
886 dma_data->maxburst = 0;
891 if (period_words % active_serializers) {
892 dev_err(mcasp->dev, "Invalid combination of period words and "
893 "active serializers: %d, %d\n", period_words,
899 * Calculate the optimal AFIFO depth for platform side:
900 * The number of words for numevt need to be in steps of active
903 numevt = (numevt / active_serializers) * active_serializers;
905 while (period_words % numevt && numevt > 0)
906 numevt -= active_serializers;
908 numevt = active_serializers;
910 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
911 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
913 /* Configure the burst size for platform drivers */
916 dma_data->maxburst = numevt;
921 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
926 int active_serializers;
930 total_slots = mcasp->tdm_slots;
933 * If more than one serializer is needed, then use them with
934 * all the specified tdm_slots. Otherwise, one serializer can
935 * cope with the transaction using just as many slots as there
936 * are channels in the stream.
938 if (mcasp->tdm_mask[stream]) {
939 active_slots = hweight32(mcasp->tdm_mask[stream]);
940 active_serializers = (channels + active_slots - 1) /
942 if (active_serializers == 1) {
943 active_slots = channels;
944 for (i = 0; i < total_slots; i++) {
945 if ((1 << i) & mcasp->tdm_mask[stream]) {
947 if (--active_slots <= 0)
953 active_serializers = (channels + total_slots - 1) / total_slots;
954 if (active_serializers == 1)
955 active_slots = channels;
957 active_slots = total_slots;
959 for (i = 0; i < active_slots; i++)
962 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
964 if (!mcasp->dat_port)
967 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
968 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
969 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
970 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
971 FSXMOD(total_slots), FSXMOD(0x1FF));
972 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
973 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
974 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
975 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
976 FSRMOD(total_slots), FSRMOD(0x1FF));
978 * If McASP is set to be TX/RX synchronous and the playback is
979 * not running already we need to configure the TX slots in
980 * order to have correct FSX on the bus
982 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
983 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
984 FSXMOD(total_slots), FSXMOD(0x1FF));
991 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
995 u8 *cs_bytes = (u8*) &cs_value;
997 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
999 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
1001 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
1002 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
1004 /* Set the TX tdm : for all the slots */
1005 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
1007 /* Set the TX clock controls : div = 1 and internal */
1008 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
1010 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
1012 /* Only 44100 and 48000 are valid, both have the same setting */
1013 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
1015 /* Enable the DIT */
1016 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
1018 /* Set S/PDIF channel status bits */
1019 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
1020 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
1024 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
1027 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
1030 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
1033 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
1036 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
1039 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
1042 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
1045 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
1048 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
1051 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
1055 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
1056 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
1061 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1062 unsigned int bclk_freq, bool set)
1065 unsigned int sysclk_freq = mcasp->sysclk_freq;
1066 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1067 int div = sysclk_freq / bclk_freq;
1068 int rem = sysclk_freq % bclk_freq;
1071 if (div > (ACLKXDIV_MASK + 1)) {
1072 if (reg & AHCLKXE) {
1073 aux_div = div / (ACLKXDIV_MASK + 1);
1074 if (div % (ACLKXDIV_MASK + 1))
1077 sysclk_freq /= aux_div;
1078 div = sysclk_freq / bclk_freq;
1079 rem = sysclk_freq % bclk_freq;
1081 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1088 ((sysclk_freq / div) - bclk_freq) >
1089 (bclk_freq - (sysclk_freq / (div+1)))) {
1091 rem = rem - bclk_freq;
1094 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1095 (int)bclk_freq)) / div - 1000000;
1099 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1102 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1104 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1111 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
1113 if (!mcasp->txnumevt)
1116 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
1119 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
1121 if (!mcasp->rxnumevt)
1124 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
1127 static snd_pcm_sframes_t davinci_mcasp_delay(
1128 struct snd_pcm_substream *substream,
1129 struct snd_soc_dai *cpu_dai)
1131 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1134 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1135 fifo_use = davinci_mcasp_tx_delay(mcasp);
1137 fifo_use = davinci_mcasp_rx_delay(mcasp);
1140 * Divide the used locations with the channel count to get the
1141 * FIFO usage in samples (don't care about partial samples in the
1144 return fifo_use / substream->runtime->channels;
1147 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1148 struct snd_pcm_hw_params *params,
1149 struct snd_soc_dai *cpu_dai)
1151 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1153 int channels = params_channels(params);
1154 int period_size = params_period_size(params);
1157 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1162 * If mcasp is BCLK master, and a BCLK divider was not provided by
1163 * the machine driver, we need to calculate the ratio.
1165 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1166 int slots = mcasp->tdm_slots;
1167 int rate = params_rate(params);
1168 int sbits = params_width(params);
1170 if (mcasp->slot_width)
1171 sbits = mcasp->slot_width;
1173 davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true);
1176 ret = mcasp_common_hw_param(mcasp, substream->stream,
1177 period_size * channels, channels);
1181 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1182 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1184 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1190 switch (params_format(params)) {
1191 case SNDRV_PCM_FORMAT_U8:
1192 case SNDRV_PCM_FORMAT_S8:
1196 case SNDRV_PCM_FORMAT_U16_LE:
1197 case SNDRV_PCM_FORMAT_S16_LE:
1201 case SNDRV_PCM_FORMAT_U24_3LE:
1202 case SNDRV_PCM_FORMAT_S24_3LE:
1206 case SNDRV_PCM_FORMAT_U24_LE:
1207 case SNDRV_PCM_FORMAT_S24_LE:
1211 case SNDRV_PCM_FORMAT_U32_LE:
1212 case SNDRV_PCM_FORMAT_S32_LE:
1217 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1221 davinci_config_channel_size(mcasp, word_length);
1223 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1224 mcasp->channels = channels;
1229 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1230 int cmd, struct snd_soc_dai *cpu_dai)
1232 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1236 case SNDRV_PCM_TRIGGER_RESUME:
1237 case SNDRV_PCM_TRIGGER_START:
1238 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1239 davinci_mcasp_start(mcasp, substream->stream);
1241 case SNDRV_PCM_TRIGGER_SUSPEND:
1242 case SNDRV_PCM_TRIGGER_STOP:
1243 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1244 davinci_mcasp_stop(mcasp, substream->stream);
1254 static const unsigned int davinci_mcasp_dai_rates[] = {
1255 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1256 88200, 96000, 176400, 192000,
1259 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1261 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1262 struct snd_pcm_hw_rule *rule)
1264 struct davinci_mcasp_ruledata *rd = rule->private;
1265 struct snd_interval *ri =
1266 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1267 int sbits = params_width(params);
1268 int slots = rd->mcasp->tdm_slots;
1269 struct snd_interval range;
1272 if (rd->mcasp->slot_width)
1273 sbits = rd->mcasp->slot_width;
1275 snd_interval_any(&range);
1278 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1279 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1280 uint bclk_freq = sbits*slots*
1281 davinci_mcasp_dai_rates[i];
1284 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq,
1286 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1288 range.min = davinci_mcasp_dai_rates[i];
1291 range.max = davinci_mcasp_dai_rates[i];
1296 dev_dbg(rd->mcasp->dev,
1297 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1298 ri->min, ri->max, range.min, range.max, sbits, slots);
1300 return snd_interval_refine(hw_param_interval(params, rule->var),
1304 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1305 struct snd_pcm_hw_rule *rule)
1307 struct davinci_mcasp_ruledata *rd = rule->private;
1308 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1309 struct snd_mask nfmt;
1310 int rate = params_rate(params);
1311 int slots = rd->mcasp->tdm_slots;
1314 snd_mask_none(&nfmt);
1316 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1317 if (snd_mask_test(fmt, i)) {
1318 uint sbits = snd_pcm_format_width(i);
1321 if (rd->mcasp->slot_width)
1322 sbits = rd->mcasp->slot_width;
1324 ppm = davinci_mcasp_calc_clk_div(rd->mcasp,
1325 sbits * slots * rate,
1327 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1328 snd_mask_set(&nfmt, i);
1333 dev_dbg(rd->mcasp->dev,
1334 "%d possible sample format for %d Hz and %d tdm slots\n",
1335 count, rate, slots);
1337 return snd_mask_refine(fmt, &nfmt);
1340 static int davinci_mcasp_hw_rule_min_periodsize(
1341 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1343 struct snd_interval *period_size = hw_param_interval(params,
1344 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1345 struct snd_interval frames;
1347 snd_interval_any(&frames);
1351 return snd_interval_refine(period_size, &frames);
1354 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1355 struct snd_soc_dai *cpu_dai)
1357 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1358 struct davinci_mcasp_ruledata *ruledata =
1359 &mcasp->ruledata[substream->stream];
1360 u32 max_channels = 0;
1362 int tdm_slots = mcasp->tdm_slots;
1364 /* Do not allow more then one stream per direction */
1365 if (mcasp->substreams[substream->stream])
1368 mcasp->substreams[substream->stream] = substream;
1370 if (mcasp->tdm_mask[substream->stream])
1371 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1373 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1377 * Limit the maximum allowed channels for the first stream:
1378 * number of serializers for the direction * tdm slots per serializer
1380 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1385 for (i = 0; i < mcasp->num_serializer; i++) {
1386 if (mcasp->serial_dir[i] == dir)
1389 ruledata->serializers = max_channels;
1390 max_channels *= tdm_slots;
1392 * If the already active stream has less channels than the calculated
1393 * limnit based on the seirializers * tdm_slots, we need to use that as
1394 * a constraint for the second stream.
1395 * Otherwise (first stream or less allowed channels) we use the
1396 * calculated constraint.
1398 if (mcasp->channels && mcasp->channels < max_channels)
1399 max_channels = mcasp->channels;
1401 * But we can always allow channels upto the amount of
1402 * the available tdm_slots.
1404 if (max_channels < tdm_slots)
1405 max_channels = tdm_slots;
1407 snd_pcm_hw_constraint_minmax(substream->runtime,
1408 SNDRV_PCM_HW_PARAM_CHANNELS,
1411 snd_pcm_hw_constraint_list(substream->runtime,
1412 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1413 &mcasp->chconstr[substream->stream]);
1415 if (mcasp->slot_width)
1416 snd_pcm_hw_constraint_minmax(substream->runtime,
1417 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1418 8, mcasp->slot_width);
1421 * If we rely on implicit BCLK divider setting we should
1422 * set constraints based on what we can provide.
1424 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1427 ruledata->mcasp = mcasp;
1429 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1430 SNDRV_PCM_HW_PARAM_RATE,
1431 davinci_mcasp_hw_rule_rate,
1433 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1436 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1437 SNDRV_PCM_HW_PARAM_FORMAT,
1438 davinci_mcasp_hw_rule_format,
1440 SNDRV_PCM_HW_PARAM_RATE, -1);
1445 snd_pcm_hw_rule_add(substream->runtime, 0,
1446 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1447 davinci_mcasp_hw_rule_min_periodsize, NULL,
1448 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1453 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1454 struct snd_soc_dai *cpu_dai)
1456 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1458 mcasp->substreams[substream->stream] = NULL;
1460 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1463 if (!cpu_dai->active)
1464 mcasp->channels = 0;
1467 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1468 .startup = davinci_mcasp_startup,
1469 .shutdown = davinci_mcasp_shutdown,
1470 .trigger = davinci_mcasp_trigger,
1471 .delay = davinci_mcasp_delay,
1472 .hw_params = davinci_mcasp_hw_params,
1473 .set_fmt = davinci_mcasp_set_dai_fmt,
1474 .set_clkdiv = davinci_mcasp_set_clkdiv,
1475 .set_sysclk = davinci_mcasp_set_sysclk,
1476 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1479 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1481 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1483 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1484 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1489 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1491 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1492 SNDRV_PCM_FMTBIT_U8 | \
1493 SNDRV_PCM_FMTBIT_S16_LE | \
1494 SNDRV_PCM_FMTBIT_U16_LE | \
1495 SNDRV_PCM_FMTBIT_S24_LE | \
1496 SNDRV_PCM_FMTBIT_U24_LE | \
1497 SNDRV_PCM_FMTBIT_S24_3LE | \
1498 SNDRV_PCM_FMTBIT_U24_3LE | \
1499 SNDRV_PCM_FMTBIT_S32_LE | \
1500 SNDRV_PCM_FMTBIT_U32_LE)
1502 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1504 .name = "davinci-mcasp.0",
1505 .probe = davinci_mcasp_dai_probe,
1508 .channels_max = 32 * 16,
1509 .rates = DAVINCI_MCASP_RATES,
1510 .formats = DAVINCI_MCASP_PCM_FMTS,
1514 .channels_max = 32 * 16,
1515 .rates = DAVINCI_MCASP_RATES,
1516 .formats = DAVINCI_MCASP_PCM_FMTS,
1518 .ops = &davinci_mcasp_dai_ops,
1520 .symmetric_samplebits = 1,
1521 .symmetric_rates = 1,
1524 .name = "davinci-mcasp.1",
1525 .probe = davinci_mcasp_dai_probe,
1528 .channels_max = 384,
1529 .rates = DAVINCI_MCASP_RATES,
1530 .formats = DAVINCI_MCASP_PCM_FMTS,
1532 .ops = &davinci_mcasp_dai_ops,
1537 static const struct snd_soc_component_driver davinci_mcasp_component = {
1538 .name = "davinci-mcasp",
1541 /* Some HW specific values and defaults. The rest is filled in from DT. */
1542 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1543 .tx_dma_offset = 0x400,
1544 .rx_dma_offset = 0x400,
1545 .version = MCASP_VERSION_1,
1548 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1549 .tx_dma_offset = 0x2000,
1550 .rx_dma_offset = 0x2000,
1551 .version = MCASP_VERSION_2,
1554 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1557 .version = MCASP_VERSION_3,
1560 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1561 /* The CFG port offset will be calculated if it is needed */
1564 .version = MCASP_VERSION_4,
1567 static const struct of_device_id mcasp_dt_ids[] = {
1569 .compatible = "ti,dm646x-mcasp-audio",
1570 .data = &dm646x_mcasp_pdata,
1573 .compatible = "ti,da830-mcasp-audio",
1574 .data = &da830_mcasp_pdata,
1577 .compatible = "ti,am33xx-mcasp-audio",
1578 .data = &am33xx_mcasp_pdata,
1581 .compatible = "ti,dra7-mcasp-audio",
1582 .data = &dra7_mcasp_pdata,
1586 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1588 static int mcasp_reparent_fck(struct platform_device *pdev)
1590 struct device_node *node = pdev->dev.of_node;
1591 struct clk *gfclk, *parent_clk;
1592 const char *parent_name;
1598 parent_name = of_get_property(node, "fck_parent", NULL);
1602 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1604 gfclk = clk_get(&pdev->dev, "fck");
1605 if (IS_ERR(gfclk)) {
1606 dev_err(&pdev->dev, "failed to get fck\n");
1607 return PTR_ERR(gfclk);
1610 parent_clk = clk_get(NULL, parent_name);
1611 if (IS_ERR(parent_clk)) {
1612 dev_err(&pdev->dev, "failed to get parent clock\n");
1613 ret = PTR_ERR(parent_clk);
1617 ret = clk_set_parent(gfclk, parent_clk);
1619 dev_err(&pdev->dev, "failed to reparent fck\n");
1624 clk_put(parent_clk);
1630 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1631 struct platform_device *pdev)
1633 struct device_node *np = pdev->dev.of_node;
1634 struct davinci_mcasp_pdata *pdata = NULL;
1635 const struct of_device_id *match =
1636 of_match_device(mcasp_dt_ids, &pdev->dev);
1637 struct of_phandle_args dma_spec;
1639 const u32 *of_serial_dir32;
1643 if (pdev->dev.platform_data) {
1644 pdata = pdev->dev.platform_data;
1645 pdata->dismod = DISMOD_LOW;
1648 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1655 /* control shouldn't reach here. something is wrong */
1660 ret = of_property_read_u32(np, "op-mode", &val);
1662 pdata->op_mode = val;
1664 ret = of_property_read_u32(np, "tdm-slots", &val);
1666 if (val < 2 || val > 32) {
1668 "tdm-slots must be in rage [2-32]\n");
1673 pdata->tdm_slots = val;
1676 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1678 if (of_serial_dir32) {
1679 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1680 (sizeof(*of_serial_dir) * val),
1682 if (!of_serial_dir) {
1687 for (i = 0; i < val; i++)
1688 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1690 pdata->num_serializer = val;
1691 pdata->serial_dir = of_serial_dir;
1694 ret = of_property_match_string(np, "dma-names", "tx");
1698 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1703 pdata->tx_dma_channel = dma_spec.args[0];
1705 /* RX is not valid in DIT mode */
1706 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1707 ret = of_property_match_string(np, "dma-names", "rx");
1711 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1716 pdata->rx_dma_channel = dma_spec.args[0];
1719 ret = of_property_read_u32(np, "tx-num-evt", &val);
1721 pdata->txnumevt = val;
1723 ret = of_property_read_u32(np, "rx-num-evt", &val);
1725 pdata->rxnumevt = val;
1727 ret = of_property_read_u32(np, "sram-size-playback", &val);
1729 pdata->sram_size_playback = val;
1731 ret = of_property_read_u32(np, "sram-size-capture", &val);
1733 pdata->sram_size_capture = val;
1735 ret = of_property_read_u32(np, "dismod", &val);
1737 if (val == 0 || val == 2 || val == 3) {
1738 pdata->dismod = DISMOD_VAL(val);
1740 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val);
1741 pdata->dismod = DISMOD_LOW;
1744 pdata->dismod = DISMOD_LOW;
1751 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1762 static const char *sdma_prefix = "ti,omap";
1764 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1766 struct dma_chan *chan;
1770 if (!mcasp->dev->of_node)
1773 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1774 chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1776 if (PTR_ERR(chan) != -EPROBE_DEFER)
1778 "Can't verify DMA configuration (%ld)\n",
1780 return PTR_ERR(chan);
1782 if (WARN_ON(!chan->device || !chan->device->dev))
1785 if (chan->device->dev->of_node)
1786 ret = of_property_read_string(chan->device->dev->of_node,
1787 "compatible", &tmp);
1789 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1791 dma_release_channel(chan);
1795 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1796 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1802 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1807 if (pdata->version != MCASP_VERSION_4)
1808 return pdata->tx_dma_offset;
1810 for (i = 0; i < pdata->num_serializer; i++) {
1811 if (pdata->serial_dir[i] == TX_MODE) {
1813 offset = DAVINCI_MCASP_TXBUF_REG(i);
1815 pr_err("%s: Only one serializer allowed!\n",
1825 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1830 if (pdata->version != MCASP_VERSION_4)
1831 return pdata->rx_dma_offset;
1833 for (i = 0; i < pdata->num_serializer; i++) {
1834 if (pdata->serial_dir[i] == RX_MODE) {
1836 offset = DAVINCI_MCASP_RXBUF_REG(i);
1838 pr_err("%s: Only one serializer allowed!\n",
1848 static int davinci_mcasp_probe(struct platform_device *pdev)
1850 struct snd_dmaengine_dai_dma_data *dma_data;
1851 struct resource *mem, *res, *dat;
1852 struct davinci_mcasp_pdata *pdata;
1853 struct davinci_mcasp *mcasp;
1859 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1860 dev_err(&pdev->dev, "No platform data supplied\n");
1864 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1869 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1871 dev_err(&pdev->dev, "no platform data\n");
1875 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1877 dev_warn(mcasp->dev,
1878 "\"mpu\" mem resource not found, using index 0\n");
1879 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1881 dev_err(&pdev->dev, "no mem resource?\n");
1886 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
1887 if (IS_ERR(mcasp->base))
1888 return PTR_ERR(mcasp->base);
1890 pm_runtime_enable(&pdev->dev);
1892 mcasp->op_mode = pdata->op_mode;
1893 /* sanity check for tdm slots parameter */
1894 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1895 if (pdata->tdm_slots < 2) {
1896 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1898 mcasp->tdm_slots = 2;
1899 } else if (pdata->tdm_slots > 32) {
1900 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1902 mcasp->tdm_slots = 32;
1904 mcasp->tdm_slots = pdata->tdm_slots;
1908 mcasp->num_serializer = pdata->num_serializer;
1910 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
1911 mcasp->num_serializer, sizeof(u32),
1913 if (!mcasp->context.xrsr_regs) {
1918 mcasp->serial_dir = pdata->serial_dir;
1919 mcasp->version = pdata->version;
1920 mcasp->txnumevt = pdata->txnumevt;
1921 mcasp->rxnumevt = pdata->rxnumevt;
1922 mcasp->dismod = pdata->dismod;
1924 mcasp->dev = &pdev->dev;
1926 irq = platform_get_irq_byname(pdev, "common");
1928 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
1929 dev_name(&pdev->dev));
1934 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1935 davinci_mcasp_common_irq_handler,
1936 IRQF_ONESHOT | IRQF_SHARED,
1939 dev_err(&pdev->dev, "common IRQ request failed\n");
1943 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1944 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1947 irq = platform_get_irq_byname(pdev, "rx");
1949 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
1950 dev_name(&pdev->dev));
1955 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1956 davinci_mcasp_rx_irq_handler,
1957 IRQF_ONESHOT, irq_name, mcasp);
1959 dev_err(&pdev->dev, "RX IRQ request failed\n");
1963 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1966 irq = platform_get_irq_byname(pdev, "tx");
1968 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
1969 dev_name(&pdev->dev));
1974 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1975 davinci_mcasp_tx_irq_handler,
1976 IRQF_ONESHOT, irq_name, mcasp);
1978 dev_err(&pdev->dev, "TX IRQ request failed\n");
1982 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1985 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1987 mcasp->dat_port = true;
1989 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1991 dma_data->addr = dat->start;
1993 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
1995 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
1996 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
2000 *dma = pdata->tx_dma_channel;
2002 /* dmaengine filter data for DT and non-DT boot */
2003 if (pdev->dev.of_node)
2004 dma_data->filter_data = "tx";
2006 dma_data->filter_data = dma;
2008 /* RX is not valid in DIT mode */
2009 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
2010 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
2012 dma_data->addr = dat->start;
2015 mem->start + davinci_mcasp_rxdma_offset(pdata);
2017 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
2018 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
2022 *dma = pdata->rx_dma_channel;
2024 /* dmaengine filter data for DT and non-DT boot */
2025 if (pdev->dev.of_node)
2026 dma_data->filter_data = "rx";
2028 dma_data->filter_data = dma;
2031 if (mcasp->version < MCASP_VERSION_3) {
2032 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
2033 /* dma_params->dma_addr is pointing to the data port address */
2034 mcasp->dat_port = true;
2036 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2039 /* Allocate memory for long enough list for all possible
2040 * scenarios. Maximum number tdm slots is 32 and there cannot
2041 * be more serializers than given in the configuration. The
2042 * serializer directions could be taken into account, but it
2043 * would make code much more complex and save only couple of
2046 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2047 devm_kcalloc(mcasp->dev,
2048 32 + mcasp->num_serializer - 1,
2049 sizeof(unsigned int),
2052 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2053 devm_kcalloc(mcasp->dev,
2054 32 + mcasp->num_serializer - 1,
2055 sizeof(unsigned int),
2058 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2059 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2064 ret = davinci_mcasp_set_ch_constraints(mcasp);
2068 dev_set_drvdata(&pdev->dev, mcasp);
2070 mcasp_reparent_fck(pdev);
2072 ret = devm_snd_soc_register_component(&pdev->dev,
2073 &davinci_mcasp_component,
2074 &davinci_mcasp_dai[pdata->op_mode], 1);
2079 ret = davinci_mcasp_get_dma_type(mcasp);
2082 #if IS_BUILTIN(CONFIG_SND_SOC_TI_EDMA_PCM) || \
2083 (IS_MODULE(CONFIG_SND_SOC_DAVINCI_MCASP) && \
2084 IS_MODULE(CONFIG_SND_SOC_TI_EDMA_PCM))
2085 ret = edma_pcm_platform_register(&pdev->dev);
2087 dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n");
2093 #if IS_BUILTIN(CONFIG_SND_SOC_TI_SDMA_PCM) || \
2094 (IS_MODULE(CONFIG_SND_SOC_DAVINCI_MCASP) && \
2095 IS_MODULE(CONFIG_SND_SOC_TI_SDMA_PCM))
2096 ret = sdma_pcm_platform_register(&pdev->dev, NULL, NULL);
2098 dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n");
2104 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2111 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2118 pm_runtime_disable(&pdev->dev);
2122 static int davinci_mcasp_remove(struct platform_device *pdev)
2124 pm_runtime_disable(&pdev->dev);
2130 static int davinci_mcasp_runtime_suspend(struct device *dev)
2132 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2133 struct davinci_mcasp_context *context = &mcasp->context;
2137 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2138 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
2140 if (mcasp->txnumevt) {
2141 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2142 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
2144 if (mcasp->rxnumevt) {
2145 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2146 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
2149 for (i = 0; i < mcasp->num_serializer; i++)
2150 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
2151 DAVINCI_MCASP_XRSRCTL_REG(i));
2156 static int davinci_mcasp_runtime_resume(struct device *dev)
2158 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2159 struct davinci_mcasp_context *context = &mcasp->context;
2163 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2164 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
2166 if (mcasp->txnumevt) {
2167 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2168 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
2170 if (mcasp->rxnumevt) {
2171 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2172 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
2175 for (i = 0; i < mcasp->num_serializer; i++)
2176 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
2177 context->xrsr_regs[i]);
2184 static const struct dev_pm_ops davinci_mcasp_pm_ops = {
2185 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend,
2186 davinci_mcasp_runtime_resume,
2190 static struct platform_driver davinci_mcasp_driver = {
2191 .probe = davinci_mcasp_probe,
2192 .remove = davinci_mcasp_remove,
2194 .name = "davinci-mcasp",
2195 .pm = &davinci_mcasp_pm_ops,
2196 .of_match_table = mcasp_dt_ids,
2200 module_platform_driver(davinci_mcasp_driver);
2202 MODULE_AUTHOR("Steve Chen");
2203 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2204 MODULE_LICENSE("GPL");