1 // SPDX-License-Identifier: GPL-2.0-only
3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
5 * Multi-channel Audio Serial Port Driver
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
8 * Suresh Rajashekara <suresh.r@ti.com>
9 * Steve Chen <schen@.mvista.com>
11 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
12 * Copyright: (C) 2009 Texas Instruments, India
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/device.h>
18 #include <linux/slab.h>
19 #include <linux/delay.h>
21 #include <linux/clk.h>
22 #include <linux/pm_runtime.h>
24 #include <linux/of_platform.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_data/davinci_asp.h>
27 #include <linux/math64.h>
28 #include <linux/bitmap.h>
29 #include <linux/gpio/driver.h>
31 #include <sound/asoundef.h>
32 #include <sound/core.h>
33 #include <sound/pcm.h>
34 #include <sound/pcm_params.h>
35 #include <sound/initval.h>
36 #include <sound/soc.h>
37 #include <sound/dmaengine_pcm.h>
41 #include "davinci-mcasp.h"
43 #define MCASP_MAX_AFIFO_DEPTH 64
46 static u32 context_regs[] = {
47 DAVINCI_MCASP_TXFMCTL_REG,
48 DAVINCI_MCASP_RXFMCTL_REG,
49 DAVINCI_MCASP_TXFMT_REG,
50 DAVINCI_MCASP_RXFMT_REG,
51 DAVINCI_MCASP_ACLKXCTL_REG,
52 DAVINCI_MCASP_ACLKRCTL_REG,
53 DAVINCI_MCASP_AHCLKXCTL_REG,
54 DAVINCI_MCASP_AHCLKRCTL_REG,
55 DAVINCI_MCASP_PDIR_REG,
56 DAVINCI_MCASP_PFUNC_REG,
57 DAVINCI_MCASP_RXMASK_REG,
58 DAVINCI_MCASP_TXMASK_REG,
59 DAVINCI_MCASP_RXTDM_REG,
60 DAVINCI_MCASP_TXTDM_REG,
63 struct davinci_mcasp_context {
64 u32 config_regs[ARRAY_SIZE(context_regs)];
65 u32 afifo_regs[2]; /* for read/write fifo control registers */
66 u32 *xrsr_regs; /* for serializer configuration */
71 struct davinci_mcasp_ruledata {
72 struct davinci_mcasp *mcasp;
76 struct davinci_mcasp {
77 struct snd_dmaengine_dai_dma_data dma_data[2];
81 struct snd_pcm_substream *substreams[2];
84 /* McASP specific data */
101 unsigned long pdir; /* Pin direction bitfield */
103 /* McASP FIFO related */
109 /* Used for comstraint setting on the second stream */
112 #ifdef CONFIG_GPIOLIB
113 struct gpio_chip gpio_chip;
117 struct davinci_mcasp_context context;
120 struct davinci_mcasp_ruledata ruledata[2];
121 struct snd_pcm_hw_constraint_list chconstr[2];
124 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
127 void __iomem *reg = mcasp->base + offset;
128 __raw_writel(__raw_readl(reg) | val, reg);
131 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
134 void __iomem *reg = mcasp->base + offset;
135 __raw_writel((__raw_readl(reg) & ~(val)), reg);
138 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
141 void __iomem *reg = mcasp->base + offset;
142 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
145 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
148 __raw_writel(val, mcasp->base + offset);
151 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
153 return (u32)__raw_readl(mcasp->base + offset);
156 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
160 mcasp_set_bits(mcasp, ctl_reg, val);
162 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
163 /* loop count is to avoid the lock-up */
164 for (i = 0; i < 1000; i++) {
165 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
169 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
170 printk(KERN_ERR "GBLCTL write error\n");
173 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
175 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
176 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
178 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
181 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
183 u32 bit = PIN_BIT_AMUTE;
185 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
187 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
189 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
193 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
197 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AFSR) {
199 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
201 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
205 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
207 if (mcasp->rxnumevt) { /* enable FIFO */
208 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
210 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
211 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
215 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
216 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
218 * When ASYNC == 0 the transmit and receive sections operate
219 * synchronously from the transmit clock and frame sync. We need to make
220 * sure that the TX signlas are enabled when starting reception.
222 if (mcasp_is_synchronous(mcasp)) {
223 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
224 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
227 /* Activate serializer(s) */
228 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
229 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
230 /* Release RX state machine */
231 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
232 /* Release Frame Sync generator */
233 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
234 if (mcasp_is_synchronous(mcasp))
235 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
237 /* enable receive IRQs */
238 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
239 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
242 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
246 if (mcasp->txnumevt) { /* enable FIFO */
247 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
249 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
250 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
254 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
255 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
256 mcasp_set_clk_pdir(mcasp, true);
258 /* Activate serializer(s) */
259 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
260 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
262 /* wait for XDATA to be cleared */
264 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
268 mcasp_set_axr_pdir(mcasp, true);
270 /* Release TX state machine */
271 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
272 /* Release Frame Sync generator */
273 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
275 /* enable transmit IRQs */
276 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
277 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
280 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
284 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
285 mcasp_start_tx(mcasp);
287 mcasp_start_rx(mcasp);
290 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
292 /* disable IRQ sources */
293 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
294 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
297 * In synchronous mode stop the TX clocks if no other stream is
300 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
301 mcasp_set_clk_pdir(mcasp, false);
302 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
305 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
306 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
308 if (mcasp->rxnumevt) { /* disable FIFO */
309 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
311 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
315 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
319 /* disable IRQ sources */
320 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
321 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
324 * In synchronous mode keep TX clocks running if the capture stream is
327 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
328 val = TXHCLKRST | TXCLKRST | TXFSRST;
330 mcasp_set_clk_pdir(mcasp, false);
333 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
334 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
336 if (mcasp->txnumevt) { /* disable FIFO */
337 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
339 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
342 mcasp_set_axr_pdir(mcasp, false);
345 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
349 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
350 mcasp_stop_tx(mcasp);
352 mcasp_stop_rx(mcasp);
355 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
357 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
358 struct snd_pcm_substream *substream;
359 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
360 u32 handled_mask = 0;
363 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
364 if (stat & XUNDRN & irq_mask) {
365 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
366 handled_mask |= XUNDRN;
368 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
370 snd_pcm_stop_xrun(substream);
374 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
378 handled_mask |= XRERR;
380 /* Ack the handled event only */
381 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
383 return IRQ_RETVAL(handled_mask);
386 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
388 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
389 struct snd_pcm_substream *substream;
390 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
391 u32 handled_mask = 0;
394 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
395 if (stat & ROVRN & irq_mask) {
396 dev_warn(mcasp->dev, "Receive buffer overflow\n");
397 handled_mask |= ROVRN;
399 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
401 snd_pcm_stop_xrun(substream);
405 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
409 handled_mask |= XRERR;
411 /* Ack the handled event only */
412 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
414 return IRQ_RETVAL(handled_mask);
417 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
419 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
420 irqreturn_t ret = IRQ_NONE;
422 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
423 ret = davinci_mcasp_tx_irq_handler(irq, data);
425 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
426 ret |= davinci_mcasp_rx_irq_handler(irq, data);
431 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
434 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
443 pm_runtime_get_sync(mcasp->dev);
444 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
445 case SND_SOC_DAIFMT_DSP_A:
446 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
447 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
448 /* 1st data bit occur one ACLK cycle after the frame sync */
451 case SND_SOC_DAIFMT_DSP_B:
452 case SND_SOC_DAIFMT_AC97:
453 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
454 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
455 /* No delay after FS */
458 case SND_SOC_DAIFMT_I2S:
459 /* configure a full-word SYNC pulse (LRCLK) */
460 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
461 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
462 /* 1st data bit occur one ACLK cycle after the frame sync */
464 /* FS need to be inverted */
467 case SND_SOC_DAIFMT_LEFT_J:
468 /* configure a full-word SYNC pulse (LRCLK) */
469 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
470 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
471 /* No delay after FS */
479 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
481 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
484 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
485 case SND_SOC_DAIFMT_CBS_CFS:
486 /* codec is clock and frame slave */
487 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
488 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
490 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
491 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
494 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
495 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
497 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
498 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
500 mcasp->bclk_master = 1;
502 case SND_SOC_DAIFMT_CBS_CFM:
503 /* codec is clock slave and frame master */
504 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
505 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
507 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
508 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
511 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
512 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
514 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
515 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
517 mcasp->bclk_master = 1;
519 case SND_SOC_DAIFMT_CBM_CFS:
520 /* codec is clock master and frame slave */
521 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
522 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
524 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
525 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
528 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
529 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
531 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
532 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
534 mcasp->bclk_master = 0;
536 case SND_SOC_DAIFMT_CBM_CFM:
537 /* codec is clock and frame master */
538 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
539 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
541 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
542 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
545 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
546 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
548 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
549 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
551 mcasp->bclk_master = 0;
558 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
559 case SND_SOC_DAIFMT_IB_NF:
560 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
561 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
562 fs_pol_rising = true;
564 case SND_SOC_DAIFMT_NB_IF:
565 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
566 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
567 fs_pol_rising = false;
569 case SND_SOC_DAIFMT_IB_IF:
570 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
571 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
572 fs_pol_rising = false;
574 case SND_SOC_DAIFMT_NB_NF:
575 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
576 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
577 fs_pol_rising = true;
585 fs_pol_rising = !fs_pol_rising;
588 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
589 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
591 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
592 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
595 mcasp->dai_fmt = fmt;
597 pm_runtime_put(mcasp->dev);
601 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
602 int div, bool explicit)
604 pm_runtime_get_sync(mcasp->dev);
606 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
607 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
608 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
609 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
610 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
613 case MCASP_CLKDIV_BCLK: /* BCLK divider */
614 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
615 ACLKXDIV(div - 1), ACLKXDIV_MASK);
616 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
617 ACLKRDIV(div - 1), ACLKRDIV_MASK);
619 mcasp->bclk_div = div;
622 case MCASP_CLKDIV_BCLK_FS_RATIO:
624 * BCLK/LRCLK ratio descries how many bit-clock cycles
625 * fit into one frame. The clock ratio is given for a
626 * full period of data (for I2S format both left and
627 * right channels), so it has to be divided by number
628 * of tdm-slots (for I2S - divided by 2).
629 * Instead of storing this ratio, we calculate a new
630 * tdm_slot width by dividing the the ratio by the
631 * number of configured tdm slots.
633 mcasp->slot_width = div / mcasp->tdm_slots;
634 if (div % mcasp->tdm_slots)
636 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
637 __func__, div, mcasp->tdm_slots);
644 pm_runtime_put(mcasp->dev);
648 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
651 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
653 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
656 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
657 unsigned int freq, int dir)
659 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
661 pm_runtime_get_sync(mcasp->dev);
662 if (dir == SND_SOC_CLOCK_OUT) {
663 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
664 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
665 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
667 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
668 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
669 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
672 mcasp->sysclk_freq = freq;
674 pm_runtime_put(mcasp->dev);
678 /* All serializers must have equal number of channels */
679 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
682 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
683 unsigned int *list = (unsigned int *) cl->list;
684 int slots = mcasp->tdm_slots;
687 if (mcasp->tdm_mask[stream])
688 slots = hweight32(mcasp->tdm_mask[stream]);
690 for (i = 1; i <= slots; i++)
693 for (i = 2; i <= serializers; i++)
694 list[count++] = i*slots;
701 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
703 int rx_serializers = 0, tx_serializers = 0, ret, i;
705 for (i = 0; i < mcasp->num_serializer; i++)
706 if (mcasp->serial_dir[i] == TX_MODE)
708 else if (mcasp->serial_dir[i] == RX_MODE)
711 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
716 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
723 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
724 unsigned int tx_mask,
725 unsigned int rx_mask,
726 int slots, int slot_width)
728 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
731 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
732 __func__, tx_mask, rx_mask, slots, slot_width);
734 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
736 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
737 tx_mask, rx_mask, slots);
742 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
743 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
744 __func__, slot_width);
748 mcasp->tdm_slots = slots;
749 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
750 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
751 mcasp->slot_width = slot_width;
753 return davinci_mcasp_set_ch_constraints(mcasp);
756 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
760 u32 tx_rotate = (sample_width / 4) & 0x7;
761 u32 mask = (1ULL << sample_width) - 1;
762 u32 slot_width = sample_width;
765 * For captured data we should not rotate, inversion and masking is
766 * enoguh to get the data to the right position:
767 * Format data from bus after reverse (XRBUF)
768 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
769 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
770 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
771 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
776 * Setting the tdm slot width either with set_clkdiv() or
777 * set_tdm_slot() allows us to for example send 32 bits per
778 * channel to the codec, while only 16 of them carry audio
781 if (mcasp->slot_width) {
783 * When we have more bclk then it is needed for the
784 * data, we need to use the rotation to move the
785 * received samples to have correct alignment.
787 slot_width = mcasp->slot_width;
788 rx_rotate = (slot_width - sample_width) / 4;
791 /* mapping of the XSSZ bit-field as described in the datasheet */
792 fmt = (slot_width >> 1) - 1;
794 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
795 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
797 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
799 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
801 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
803 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
806 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
811 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
812 int period_words, int channels)
814 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
818 u8 slots = mcasp->tdm_slots;
819 u8 max_active_serializers = (channels + slots - 1) / slots;
820 int active_serializers, numevt;
822 /* Default configuration */
823 if (mcasp->version < MCASP_VERSION_3)
824 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
826 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
827 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
828 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
830 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
831 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
834 for (i = 0; i < mcasp->num_serializer; i++) {
835 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
836 mcasp->serial_dir[i]);
837 if (mcasp->serial_dir[i] == TX_MODE &&
838 tx_ser < max_active_serializers) {
839 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
840 mcasp->dismod, DISMOD_MASK);
841 set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
843 } else if (mcasp->serial_dir[i] == RX_MODE &&
844 rx_ser < max_active_serializers) {
845 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
847 } else if (mcasp->serial_dir[i] == INACTIVE_MODE) {
848 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
849 SRMOD_INACTIVE, SRMOD_MASK);
850 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
851 } else if (mcasp->serial_dir[i] == TX_MODE) {
852 /* Unused TX pins, clear PDIR */
853 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
854 mcasp->dismod, DISMOD_MASK);
855 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
859 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
860 active_serializers = tx_ser;
861 numevt = mcasp->txnumevt;
862 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
864 active_serializers = rx_ser;
865 numevt = mcasp->rxnumevt;
866 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
869 if (active_serializers < max_active_serializers) {
870 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
871 "enabled in mcasp (%d)\n", channels,
872 active_serializers * slots);
876 /* AFIFO is not in use */
878 /* Configure the burst size for platform drivers */
879 if (active_serializers > 1) {
881 * If more than one serializers are in use we have one
882 * DMA request to provide data for all serializers.
883 * For example if three serializers are enabled the DMA
884 * need to transfer three words per DMA request.
886 dma_data->maxburst = active_serializers;
888 dma_data->maxburst = 0;
893 if (period_words % active_serializers) {
894 dev_err(mcasp->dev, "Invalid combination of period words and "
895 "active serializers: %d, %d\n", period_words,
901 * Calculate the optimal AFIFO depth for platform side:
902 * The number of words for numevt need to be in steps of active
905 numevt = (numevt / active_serializers) * active_serializers;
907 while (period_words % numevt && numevt > 0)
908 numevt -= active_serializers;
910 numevt = active_serializers;
912 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
913 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
915 /* Configure the burst size for platform drivers */
918 dma_data->maxburst = numevt;
923 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
928 int active_serializers;
932 total_slots = mcasp->tdm_slots;
935 * If more than one serializer is needed, then use them with
936 * all the specified tdm_slots. Otherwise, one serializer can
937 * cope with the transaction using just as many slots as there
938 * are channels in the stream.
940 if (mcasp->tdm_mask[stream]) {
941 active_slots = hweight32(mcasp->tdm_mask[stream]);
942 active_serializers = (channels + active_slots - 1) /
944 if (active_serializers == 1) {
945 active_slots = channels;
946 for (i = 0; i < total_slots; i++) {
947 if ((1 << i) & mcasp->tdm_mask[stream]) {
949 if (--active_slots <= 0)
955 active_serializers = (channels + total_slots - 1) / total_slots;
956 if (active_serializers == 1)
957 active_slots = channels;
959 active_slots = total_slots;
961 for (i = 0; i < active_slots; i++)
964 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
966 if (!mcasp->dat_port)
969 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
970 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
971 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
972 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
973 FSXMOD(total_slots), FSXMOD(0x1FF));
974 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
975 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
976 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
977 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
978 FSRMOD(total_slots), FSRMOD(0x1FF));
980 * If McASP is set to be TX/RX synchronous and the playback is
981 * not running already we need to configure the TX slots in
982 * order to have correct FSX on the bus
984 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
985 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
986 FSXMOD(total_slots), FSXMOD(0x1FF));
993 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
997 u8 *cs_bytes = (u8*) &cs_value;
999 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
1001 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
1003 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
1004 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
1006 /* Set the TX tdm : for all the slots */
1007 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
1009 /* Set the TX clock controls : div = 1 and internal */
1010 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
1012 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
1014 /* Only 44100 and 48000 are valid, both have the same setting */
1015 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
1017 /* Enable the DIT */
1018 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
1020 /* Set S/PDIF channel status bits */
1021 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
1022 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
1026 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
1029 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
1032 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
1035 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
1038 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
1041 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
1044 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
1047 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
1050 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
1053 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
1057 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
1058 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
1063 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1064 unsigned int bclk_freq, bool set)
1067 unsigned int sysclk_freq = mcasp->sysclk_freq;
1068 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1069 int div = sysclk_freq / bclk_freq;
1070 int rem = sysclk_freq % bclk_freq;
1073 if (div > (ACLKXDIV_MASK + 1)) {
1074 if (reg & AHCLKXE) {
1075 aux_div = div / (ACLKXDIV_MASK + 1);
1076 if (div % (ACLKXDIV_MASK + 1))
1079 sysclk_freq /= aux_div;
1080 div = sysclk_freq / bclk_freq;
1081 rem = sysclk_freq % bclk_freq;
1083 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1090 ((sysclk_freq / div) - bclk_freq) >
1091 (bclk_freq - (sysclk_freq / (div+1)))) {
1093 rem = rem - bclk_freq;
1096 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1097 (int)bclk_freq)) / div - 1000000;
1101 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1104 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1106 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1113 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
1115 if (!mcasp->txnumevt)
1118 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
1121 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
1123 if (!mcasp->rxnumevt)
1126 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
1129 static snd_pcm_sframes_t davinci_mcasp_delay(
1130 struct snd_pcm_substream *substream,
1131 struct snd_soc_dai *cpu_dai)
1133 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1136 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1137 fifo_use = davinci_mcasp_tx_delay(mcasp);
1139 fifo_use = davinci_mcasp_rx_delay(mcasp);
1142 * Divide the used locations with the channel count to get the
1143 * FIFO usage in samples (don't care about partial samples in the
1146 return fifo_use / substream->runtime->channels;
1149 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1150 struct snd_pcm_hw_params *params,
1151 struct snd_soc_dai *cpu_dai)
1153 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1155 int channels = params_channels(params);
1156 int period_size = params_period_size(params);
1159 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1164 * If mcasp is BCLK master, and a BCLK divider was not provided by
1165 * the machine driver, we need to calculate the ratio.
1167 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1168 int slots = mcasp->tdm_slots;
1169 int rate = params_rate(params);
1170 int sbits = params_width(params);
1172 if (mcasp->slot_width)
1173 sbits = mcasp->slot_width;
1175 davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true);
1178 ret = mcasp_common_hw_param(mcasp, substream->stream,
1179 period_size * channels, channels);
1183 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1184 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1186 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1192 switch (params_format(params)) {
1193 case SNDRV_PCM_FORMAT_U8:
1194 case SNDRV_PCM_FORMAT_S8:
1198 case SNDRV_PCM_FORMAT_U16_LE:
1199 case SNDRV_PCM_FORMAT_S16_LE:
1203 case SNDRV_PCM_FORMAT_U24_3LE:
1204 case SNDRV_PCM_FORMAT_S24_3LE:
1208 case SNDRV_PCM_FORMAT_U24_LE:
1209 case SNDRV_PCM_FORMAT_S24_LE:
1213 case SNDRV_PCM_FORMAT_U32_LE:
1214 case SNDRV_PCM_FORMAT_S32_LE:
1219 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1223 davinci_config_channel_size(mcasp, word_length);
1225 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1226 mcasp->channels = channels;
1231 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1232 int cmd, struct snd_soc_dai *cpu_dai)
1234 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1238 case SNDRV_PCM_TRIGGER_RESUME:
1239 case SNDRV_PCM_TRIGGER_START:
1240 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1241 davinci_mcasp_start(mcasp, substream->stream);
1243 case SNDRV_PCM_TRIGGER_SUSPEND:
1244 case SNDRV_PCM_TRIGGER_STOP:
1245 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1246 davinci_mcasp_stop(mcasp, substream->stream);
1256 static const unsigned int davinci_mcasp_dai_rates[] = {
1257 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1258 88200, 96000, 176400, 192000,
1261 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1263 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1264 struct snd_pcm_hw_rule *rule)
1266 struct davinci_mcasp_ruledata *rd = rule->private;
1267 struct snd_interval *ri =
1268 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1269 int sbits = params_width(params);
1270 int slots = rd->mcasp->tdm_slots;
1271 struct snd_interval range;
1274 if (rd->mcasp->slot_width)
1275 sbits = rd->mcasp->slot_width;
1277 snd_interval_any(&range);
1280 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1281 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1282 uint bclk_freq = sbits*slots*
1283 davinci_mcasp_dai_rates[i];
1286 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq,
1288 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1290 range.min = davinci_mcasp_dai_rates[i];
1293 range.max = davinci_mcasp_dai_rates[i];
1298 dev_dbg(rd->mcasp->dev,
1299 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1300 ri->min, ri->max, range.min, range.max, sbits, slots);
1302 return snd_interval_refine(hw_param_interval(params, rule->var),
1306 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1307 struct snd_pcm_hw_rule *rule)
1309 struct davinci_mcasp_ruledata *rd = rule->private;
1310 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1311 struct snd_mask nfmt;
1312 int rate = params_rate(params);
1313 int slots = rd->mcasp->tdm_slots;
1316 snd_mask_none(&nfmt);
1318 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1319 if (snd_mask_test(fmt, i)) {
1320 uint sbits = snd_pcm_format_width(i);
1323 if (rd->mcasp->slot_width)
1324 sbits = rd->mcasp->slot_width;
1326 ppm = davinci_mcasp_calc_clk_div(rd->mcasp,
1327 sbits * slots * rate,
1329 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1330 snd_mask_set(&nfmt, i);
1335 dev_dbg(rd->mcasp->dev,
1336 "%d possible sample format for %d Hz and %d tdm slots\n",
1337 count, rate, slots);
1339 return snd_mask_refine(fmt, &nfmt);
1342 static int davinci_mcasp_hw_rule_min_periodsize(
1343 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1345 struct snd_interval *period_size = hw_param_interval(params,
1346 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1347 struct snd_interval frames;
1349 snd_interval_any(&frames);
1353 return snd_interval_refine(period_size, &frames);
1356 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1357 struct snd_soc_dai *cpu_dai)
1359 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1360 struct davinci_mcasp_ruledata *ruledata =
1361 &mcasp->ruledata[substream->stream];
1362 u32 max_channels = 0;
1364 int tdm_slots = mcasp->tdm_slots;
1366 /* Do not allow more then one stream per direction */
1367 if (mcasp->substreams[substream->stream])
1370 mcasp->substreams[substream->stream] = substream;
1372 if (mcasp->tdm_mask[substream->stream])
1373 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1375 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1379 * Limit the maximum allowed channels for the first stream:
1380 * number of serializers for the direction * tdm slots per serializer
1382 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1387 for (i = 0; i < mcasp->num_serializer; i++) {
1388 if (mcasp->serial_dir[i] == dir)
1391 ruledata->serializers = max_channels;
1392 max_channels *= tdm_slots;
1394 * If the already active stream has less channels than the calculated
1395 * limnit based on the seirializers * tdm_slots, we need to use that as
1396 * a constraint for the second stream.
1397 * Otherwise (first stream or less allowed channels) we use the
1398 * calculated constraint.
1400 if (mcasp->channels && mcasp->channels < max_channels)
1401 max_channels = mcasp->channels;
1403 * But we can always allow channels upto the amount of
1404 * the available tdm_slots.
1406 if (max_channels < tdm_slots)
1407 max_channels = tdm_slots;
1409 snd_pcm_hw_constraint_minmax(substream->runtime,
1410 SNDRV_PCM_HW_PARAM_CHANNELS,
1413 snd_pcm_hw_constraint_list(substream->runtime,
1414 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1415 &mcasp->chconstr[substream->stream]);
1417 if (mcasp->slot_width)
1418 snd_pcm_hw_constraint_minmax(substream->runtime,
1419 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1420 8, mcasp->slot_width);
1423 * If we rely on implicit BCLK divider setting we should
1424 * set constraints based on what we can provide.
1426 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1429 ruledata->mcasp = mcasp;
1431 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1432 SNDRV_PCM_HW_PARAM_RATE,
1433 davinci_mcasp_hw_rule_rate,
1435 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1438 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1439 SNDRV_PCM_HW_PARAM_FORMAT,
1440 davinci_mcasp_hw_rule_format,
1442 SNDRV_PCM_HW_PARAM_RATE, -1);
1447 snd_pcm_hw_rule_add(substream->runtime, 0,
1448 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1449 davinci_mcasp_hw_rule_min_periodsize, NULL,
1450 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1455 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1456 struct snd_soc_dai *cpu_dai)
1458 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1460 mcasp->substreams[substream->stream] = NULL;
1462 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1465 if (!cpu_dai->active)
1466 mcasp->channels = 0;
1469 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1470 .startup = davinci_mcasp_startup,
1471 .shutdown = davinci_mcasp_shutdown,
1472 .trigger = davinci_mcasp_trigger,
1473 .delay = davinci_mcasp_delay,
1474 .hw_params = davinci_mcasp_hw_params,
1475 .set_fmt = davinci_mcasp_set_dai_fmt,
1476 .set_clkdiv = davinci_mcasp_set_clkdiv,
1477 .set_sysclk = davinci_mcasp_set_sysclk,
1478 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1481 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1483 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1485 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1486 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1491 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1493 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1494 SNDRV_PCM_FMTBIT_U8 | \
1495 SNDRV_PCM_FMTBIT_S16_LE | \
1496 SNDRV_PCM_FMTBIT_U16_LE | \
1497 SNDRV_PCM_FMTBIT_S24_LE | \
1498 SNDRV_PCM_FMTBIT_U24_LE | \
1499 SNDRV_PCM_FMTBIT_S24_3LE | \
1500 SNDRV_PCM_FMTBIT_U24_3LE | \
1501 SNDRV_PCM_FMTBIT_S32_LE | \
1502 SNDRV_PCM_FMTBIT_U32_LE)
1504 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1506 .name = "davinci-mcasp.0",
1507 .probe = davinci_mcasp_dai_probe,
1510 .channels_max = 32 * 16,
1511 .rates = DAVINCI_MCASP_RATES,
1512 .formats = DAVINCI_MCASP_PCM_FMTS,
1516 .channels_max = 32 * 16,
1517 .rates = DAVINCI_MCASP_RATES,
1518 .formats = DAVINCI_MCASP_PCM_FMTS,
1520 .ops = &davinci_mcasp_dai_ops,
1522 .symmetric_samplebits = 1,
1523 .symmetric_rates = 1,
1526 .name = "davinci-mcasp.1",
1527 .probe = davinci_mcasp_dai_probe,
1530 .channels_max = 384,
1531 .rates = DAVINCI_MCASP_RATES,
1532 .formats = DAVINCI_MCASP_PCM_FMTS,
1534 .ops = &davinci_mcasp_dai_ops,
1539 static const struct snd_soc_component_driver davinci_mcasp_component = {
1540 .name = "davinci-mcasp",
1543 /* Some HW specific values and defaults. The rest is filled in from DT. */
1544 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1545 .tx_dma_offset = 0x400,
1546 .rx_dma_offset = 0x400,
1547 .version = MCASP_VERSION_1,
1550 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1551 .tx_dma_offset = 0x2000,
1552 .rx_dma_offset = 0x2000,
1553 .version = MCASP_VERSION_2,
1556 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1559 .version = MCASP_VERSION_3,
1562 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1563 /* The CFG port offset will be calculated if it is needed */
1566 .version = MCASP_VERSION_4,
1569 static const struct of_device_id mcasp_dt_ids[] = {
1571 .compatible = "ti,dm646x-mcasp-audio",
1572 .data = &dm646x_mcasp_pdata,
1575 .compatible = "ti,da830-mcasp-audio",
1576 .data = &da830_mcasp_pdata,
1579 .compatible = "ti,am33xx-mcasp-audio",
1580 .data = &am33xx_mcasp_pdata,
1583 .compatible = "ti,dra7-mcasp-audio",
1584 .data = &dra7_mcasp_pdata,
1588 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1590 static int mcasp_reparent_fck(struct platform_device *pdev)
1592 struct device_node *node = pdev->dev.of_node;
1593 struct clk *gfclk, *parent_clk;
1594 const char *parent_name;
1600 parent_name = of_get_property(node, "fck_parent", NULL);
1604 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1606 gfclk = clk_get(&pdev->dev, "fck");
1607 if (IS_ERR(gfclk)) {
1608 dev_err(&pdev->dev, "failed to get fck\n");
1609 return PTR_ERR(gfclk);
1612 parent_clk = clk_get(NULL, parent_name);
1613 if (IS_ERR(parent_clk)) {
1614 dev_err(&pdev->dev, "failed to get parent clock\n");
1615 ret = PTR_ERR(parent_clk);
1619 ret = clk_set_parent(gfclk, parent_clk);
1621 dev_err(&pdev->dev, "failed to reparent fck\n");
1626 clk_put(parent_clk);
1632 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1633 struct platform_device *pdev)
1635 struct device_node *np = pdev->dev.of_node;
1636 struct davinci_mcasp_pdata *pdata = NULL;
1637 const struct of_device_id *match =
1638 of_match_device(mcasp_dt_ids, &pdev->dev);
1639 struct of_phandle_args dma_spec;
1641 const u32 *of_serial_dir32;
1645 if (pdev->dev.platform_data) {
1646 pdata = pdev->dev.platform_data;
1647 pdata->dismod = DISMOD_LOW;
1650 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1657 /* control shouldn't reach here. something is wrong */
1662 ret = of_property_read_u32(np, "op-mode", &val);
1664 pdata->op_mode = val;
1666 ret = of_property_read_u32(np, "tdm-slots", &val);
1668 if (val < 2 || val > 32) {
1670 "tdm-slots must be in rage [2-32]\n");
1675 pdata->tdm_slots = val;
1678 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1680 if (of_serial_dir32) {
1681 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1682 (sizeof(*of_serial_dir) * val),
1684 if (!of_serial_dir) {
1689 for (i = 0; i < val; i++)
1690 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1692 pdata->num_serializer = val;
1693 pdata->serial_dir = of_serial_dir;
1696 ret = of_property_match_string(np, "dma-names", "tx");
1700 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1705 pdata->tx_dma_channel = dma_spec.args[0];
1707 /* RX is not valid in DIT mode */
1708 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1709 ret = of_property_match_string(np, "dma-names", "rx");
1713 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1718 pdata->rx_dma_channel = dma_spec.args[0];
1721 ret = of_property_read_u32(np, "tx-num-evt", &val);
1723 pdata->txnumevt = val;
1725 ret = of_property_read_u32(np, "rx-num-evt", &val);
1727 pdata->rxnumevt = val;
1729 ret = of_property_read_u32(np, "sram-size-playback", &val);
1731 pdata->sram_size_playback = val;
1733 ret = of_property_read_u32(np, "sram-size-capture", &val);
1735 pdata->sram_size_capture = val;
1737 ret = of_property_read_u32(np, "dismod", &val);
1739 if (val == 0 || val == 2 || val == 3) {
1740 pdata->dismod = DISMOD_VAL(val);
1742 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val);
1743 pdata->dismod = DISMOD_LOW;
1746 pdata->dismod = DISMOD_LOW;
1753 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1764 static const char *sdma_prefix = "ti,omap";
1766 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1768 struct dma_chan *chan;
1772 if (!mcasp->dev->of_node)
1775 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1776 chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1778 if (PTR_ERR(chan) != -EPROBE_DEFER)
1780 "Can't verify DMA configuration (%ld)\n",
1782 return PTR_ERR(chan);
1784 if (WARN_ON(!chan->device || !chan->device->dev))
1787 if (chan->device->dev->of_node)
1788 ret = of_property_read_string(chan->device->dev->of_node,
1789 "compatible", &tmp);
1791 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1793 dma_release_channel(chan);
1797 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1798 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1804 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1809 if (pdata->version != MCASP_VERSION_4)
1810 return pdata->tx_dma_offset;
1812 for (i = 0; i < pdata->num_serializer; i++) {
1813 if (pdata->serial_dir[i] == TX_MODE) {
1815 offset = DAVINCI_MCASP_TXBUF_REG(i);
1817 pr_err("%s: Only one serializer allowed!\n",
1827 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1832 if (pdata->version != MCASP_VERSION_4)
1833 return pdata->rx_dma_offset;
1835 for (i = 0; i < pdata->num_serializer; i++) {
1836 if (pdata->serial_dir[i] == RX_MODE) {
1838 offset = DAVINCI_MCASP_RXBUF_REG(i);
1840 pr_err("%s: Only one serializer allowed!\n",
1850 #ifdef CONFIG_GPIOLIB
1851 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset)
1853 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1855 if (mcasp->num_serializer && offset < mcasp->num_serializer &&
1856 mcasp->serial_dir[offset] != INACTIVE_MODE) {
1857 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset);
1861 /* Do not change the PIN yet */
1863 return pm_runtime_get_sync(mcasp->dev);
1866 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset)
1868 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1870 /* Set the direction to input */
1871 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1873 /* Set the pin as McASP pin */
1874 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1876 pm_runtime_put_sync(mcasp->dev);
1879 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip,
1880 unsigned offset, int value)
1882 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1886 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1888 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1890 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
1891 if (!(val & BIT(offset))) {
1892 /* Set the pin as GPIO pin */
1893 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1895 /* Set the direction to output */
1896 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1902 static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset,
1905 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1908 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1910 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1913 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip,
1916 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1919 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
1920 if (!(val & BIT(offset))) {
1921 /* Set the direction to input */
1922 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1924 /* Set the pin as GPIO pin */
1925 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1931 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset)
1933 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1936 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);
1937 if (val & BIT(offset))
1943 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip,
1946 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1949 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
1950 if (val & BIT(offset))
1956 static const struct gpio_chip davinci_mcasp_template_chip = {
1957 .owner = THIS_MODULE,
1958 .request = davinci_mcasp_gpio_request,
1959 .free = davinci_mcasp_gpio_free,
1960 .direction_output = davinci_mcasp_gpio_direction_out,
1961 .set = davinci_mcasp_gpio_set,
1962 .direction_input = davinci_mcasp_gpio_direction_in,
1963 .get = davinci_mcasp_gpio_get,
1964 .get_direction = davinci_mcasp_gpio_get_direction,
1969 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
1971 if (!of_property_read_bool(mcasp->dev->of_node, "gpio-controller"))
1974 mcasp->gpio_chip = davinci_mcasp_template_chip;
1975 mcasp->gpio_chip.label = dev_name(mcasp->dev);
1976 mcasp->gpio_chip.parent = mcasp->dev;
1977 #ifdef CONFIG_OF_GPIO
1978 mcasp->gpio_chip.of_node = mcasp->dev->of_node;
1981 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp);
1984 #else /* CONFIG_GPIOLIB */
1985 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
1989 #endif /* CONFIG_GPIOLIB */
1991 static int davinci_mcasp_probe(struct platform_device *pdev)
1993 struct snd_dmaengine_dai_dma_data *dma_data;
1994 struct resource *mem, *res, *dat;
1995 struct davinci_mcasp_pdata *pdata;
1996 struct davinci_mcasp *mcasp;
2002 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
2003 dev_err(&pdev->dev, "No platform data supplied\n");
2007 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
2012 pdata = davinci_mcasp_set_pdata_from_of(pdev);
2014 dev_err(&pdev->dev, "no platform data\n");
2018 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
2020 dev_warn(mcasp->dev,
2021 "\"mpu\" mem resource not found, using index 0\n");
2022 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2024 dev_err(&pdev->dev, "no mem resource?\n");
2029 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
2030 if (IS_ERR(mcasp->base))
2031 return PTR_ERR(mcasp->base);
2033 pm_runtime_enable(&pdev->dev);
2035 mcasp->op_mode = pdata->op_mode;
2036 /* sanity check for tdm slots parameter */
2037 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
2038 if (pdata->tdm_slots < 2) {
2039 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
2041 mcasp->tdm_slots = 2;
2042 } else if (pdata->tdm_slots > 32) {
2043 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
2045 mcasp->tdm_slots = 32;
2047 mcasp->tdm_slots = pdata->tdm_slots;
2051 mcasp->num_serializer = pdata->num_serializer;
2053 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
2054 mcasp->num_serializer, sizeof(u32),
2056 if (!mcasp->context.xrsr_regs) {
2061 mcasp->serial_dir = pdata->serial_dir;
2062 mcasp->version = pdata->version;
2063 mcasp->txnumevt = pdata->txnumevt;
2064 mcasp->rxnumevt = pdata->rxnumevt;
2065 mcasp->dismod = pdata->dismod;
2067 mcasp->dev = &pdev->dev;
2069 irq = platform_get_irq_byname(pdev, "common");
2071 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
2072 dev_name(&pdev->dev));
2077 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2078 davinci_mcasp_common_irq_handler,
2079 IRQF_ONESHOT | IRQF_SHARED,
2082 dev_err(&pdev->dev, "common IRQ request failed\n");
2086 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2087 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2090 irq = platform_get_irq_byname(pdev, "rx");
2092 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
2093 dev_name(&pdev->dev));
2098 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2099 davinci_mcasp_rx_irq_handler,
2100 IRQF_ONESHOT, irq_name, mcasp);
2102 dev_err(&pdev->dev, "RX IRQ request failed\n");
2106 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2109 irq = platform_get_irq_byname(pdev, "tx");
2111 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
2112 dev_name(&pdev->dev));
2117 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2118 davinci_mcasp_tx_irq_handler,
2119 IRQF_ONESHOT, irq_name, mcasp);
2121 dev_err(&pdev->dev, "TX IRQ request failed\n");
2125 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2128 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
2130 mcasp->dat_port = true;
2132 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
2134 dma_data->addr = dat->start;
2136 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
2138 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
2139 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
2143 *dma = pdata->tx_dma_channel;
2145 /* dmaengine filter data for DT and non-DT boot */
2146 if (pdev->dev.of_node)
2147 dma_data->filter_data = "tx";
2149 dma_data->filter_data = dma;
2151 /* RX is not valid in DIT mode */
2152 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
2153 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
2155 dma_data->addr = dat->start;
2158 mem->start + davinci_mcasp_rxdma_offset(pdata);
2160 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
2161 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
2165 *dma = pdata->rx_dma_channel;
2167 /* dmaengine filter data for DT and non-DT boot */
2168 if (pdev->dev.of_node)
2169 dma_data->filter_data = "rx";
2171 dma_data->filter_data = dma;
2174 if (mcasp->version < MCASP_VERSION_3) {
2175 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
2176 /* dma_params->dma_addr is pointing to the data port address */
2177 mcasp->dat_port = true;
2179 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2182 /* Allocate memory for long enough list for all possible
2183 * scenarios. Maximum number tdm slots is 32 and there cannot
2184 * be more serializers than given in the configuration. The
2185 * serializer directions could be taken into account, but it
2186 * would make code much more complex and save only couple of
2189 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2190 devm_kcalloc(mcasp->dev,
2191 32 + mcasp->num_serializer - 1,
2192 sizeof(unsigned int),
2195 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2196 devm_kcalloc(mcasp->dev,
2197 32 + mcasp->num_serializer - 1,
2198 sizeof(unsigned int),
2201 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2202 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2207 ret = davinci_mcasp_set_ch_constraints(mcasp);
2211 dev_set_drvdata(&pdev->dev, mcasp);
2213 mcasp_reparent_fck(pdev);
2215 /* All PINS as McASP */
2216 pm_runtime_get_sync(mcasp->dev);
2217 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
2218 pm_runtime_put(mcasp->dev);
2220 ret = davinci_mcasp_init_gpiochip(mcasp);
2224 ret = devm_snd_soc_register_component(&pdev->dev,
2225 &davinci_mcasp_component,
2226 &davinci_mcasp_dai[pdata->op_mode], 1);
2231 ret = davinci_mcasp_get_dma_type(mcasp);
2234 ret = edma_pcm_platform_register(&pdev->dev);
2237 ret = sdma_pcm_platform_register(&pdev->dev, NULL, NULL);
2240 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2247 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2254 pm_runtime_disable(&pdev->dev);
2258 static int davinci_mcasp_remove(struct platform_device *pdev)
2260 pm_runtime_disable(&pdev->dev);
2266 static int davinci_mcasp_runtime_suspend(struct device *dev)
2268 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2269 struct davinci_mcasp_context *context = &mcasp->context;
2273 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2274 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
2276 if (mcasp->txnumevt) {
2277 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2278 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
2280 if (mcasp->rxnumevt) {
2281 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2282 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
2285 for (i = 0; i < mcasp->num_serializer; i++)
2286 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
2287 DAVINCI_MCASP_XRSRCTL_REG(i));
2292 static int davinci_mcasp_runtime_resume(struct device *dev)
2294 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2295 struct davinci_mcasp_context *context = &mcasp->context;
2299 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2300 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
2302 if (mcasp->txnumevt) {
2303 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2304 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
2306 if (mcasp->rxnumevt) {
2307 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2308 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
2311 for (i = 0; i < mcasp->num_serializer; i++)
2312 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
2313 context->xrsr_regs[i]);
2320 static const struct dev_pm_ops davinci_mcasp_pm_ops = {
2321 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend,
2322 davinci_mcasp_runtime_resume,
2326 static struct platform_driver davinci_mcasp_driver = {
2327 .probe = davinci_mcasp_probe,
2328 .remove = davinci_mcasp_remove,
2330 .name = "davinci-mcasp",
2331 .pm = &davinci_mcasp_pm_ops,
2332 .of_match_table = mcasp_dt_ids,
2336 module_platform_driver(davinci_mcasp_driver);
2338 MODULE_AUTHOR("Steve Chen");
2339 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2340 MODULE_LICENSE("GPL");