sound/soc/tegra/tegra210_i2s.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // tegra210_i2s.c - Tegra210 I2S driver
   4 //
   5 // Copyright (c) 2020 NVIDIA CORPORATION.  All rights reserved.
   6
   7 #include <linux/clk.h>
   8 #include <linux/device.h>
   9 #include <linux/module.h>
  10 #include <linux/of_device.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/pm_runtime.h>
  13 #include <linux/regmap.h>
  14 #include <sound/core.h>
  15 #include <sound/pcm_params.h>
  16 #include <sound/soc.h>
  17 #include "tegra210_i2s.h"
  18 #include "tegra_cif.h"
  19
  20 static const struct reg_default tegra210_i2s_reg_defaults[] = {
  21         { TEGRA210_I2S_RX_INT_MASK, 0x00000003 },
  22         { TEGRA210_I2S_RX_CIF_CTRL, 0x00007700 },
  23         { TEGRA210_I2S_TX_INT_MASK, 0x00000003 },
  24         { TEGRA210_I2S_TX_CIF_CTRL, 0x00007700 },
  25         { TEGRA210_I2S_CG, 0x1 },
  26         { TEGRA210_I2S_TIMING, 0x0000001f },
  27         { TEGRA210_I2S_ENABLE, 0x1 },
  28         /*
  29          * Below update does not have any effect on Tegra186 and Tegra194.
  30          * On Tegra210, I2S4 has "i2s4a" and "i2s4b" pins and below update
  31          * is required to select i2s4b for it to be functional for I2S
  32          * operation.
  33          */
  34         { TEGRA210_I2S_CYA, 0x1 },
  35 };
  36
  37 static void tegra210_i2s_set_slot_ctrl(struct regmap *regmap,
  38                                        unsigned int total_slots,
  39                                        unsigned int tx_slot_mask,
  40                                        unsigned int rx_slot_mask)
  41 {
  42         regmap_write(regmap, TEGRA210_I2S_SLOT_CTRL, total_slots - 1);
  43         regmap_write(regmap, TEGRA210_I2S_TX_SLOT_CTRL, tx_slot_mask);
  44         regmap_write(regmap, TEGRA210_I2S_RX_SLOT_CTRL, rx_slot_mask);
  45 }
  46
  47 static int tegra210_i2s_set_clock_rate(struct device *dev,
  48                                        unsigned int clock_rate)
  49 {
  50         struct tegra210_i2s *i2s = dev_get_drvdata(dev);
  51         unsigned int val;
  52         int err;
  53
  54         regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val);
  55
  56         /* No need to set rates if I2S is being operated in slave */
  57         if (!(val & I2S_CTRL_MASTER_EN))
  58                 return 0;
  59
  60         err = clk_set_rate(i2s->clk_i2s, clock_rate);
  61         if (err) {
  62                 dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n",
  63                         clock_rate, err);
  64                 return err;
  65         }
  66
  67         if (!IS_ERR(i2s->clk_sync_input)) {
  68                 /*
  69                  * Other I/O modules in AHUB can use i2s bclk as reference
  70                  * clock. Below sets sync input clock rate as per bclk,
  71                  * which can be used as input to other I/O modules.
  72                  */
  73                 err = clk_set_rate(i2s->clk_sync_input, clock_rate);
  74                 if (err) {
  75                         dev_err(dev,
  76                                 "can't set I2S sync input rate %u, err = %d\n",
  77                                 clock_rate, err);
  78                         return err;
  79                 }
  80         }
  81
  82         return 0;
  83 }
  84
  85 static int tegra210_i2s_sw_reset(struct snd_soc_component *compnt,
  86                                  bool is_playback)
  87 {
  88         struct device *dev = compnt->dev;
  89         struct tegra210_i2s *i2s = dev_get_drvdata(dev);
  90         unsigned int reset_mask = I2S_SOFT_RESET_MASK;
  91         unsigned int reset_en = I2S_SOFT_RESET_EN;
  92         unsigned int reset_reg, cif_reg, stream_reg;
  93         unsigned int cif_ctrl, stream_ctrl, i2s_ctrl, val;
  94         int err;
  95
  96         if (is_playback) {
  97                 reset_reg = TEGRA210_I2S_RX_SOFT_RESET;
  98                 cif_reg = TEGRA210_I2S_RX_CIF_CTRL;
  99                 stream_reg = TEGRA210_I2S_RX_CTRL;
 100         } else {
 101                 reset_reg = TEGRA210_I2S_TX_SOFT_RESET;
 102                 cif_reg = TEGRA210_I2S_TX_CIF_CTRL;
 103                 stream_reg = TEGRA210_I2S_TX_CTRL;
 104         }
 105
 106         /* Store CIF and I2S control values */
 107         regmap_read(i2s->regmap, cif_reg, &cif_ctrl);
 108         regmap_read(i2s->regmap, stream_reg, &stream_ctrl);
 109         regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &i2s_ctrl);
 110
 111         /* Reset to make sure the previous transactions are clean */
 112         regmap_update_bits(i2s->regmap, reset_reg, reset_mask, reset_en);
 113
 114         err = regmap_read_poll_timeout(i2s->regmap, reset_reg, val,
 115                                        !(val & reset_mask & reset_en),
 116                                        10, 10000);
 117         if (err) {
 118                 dev_err(dev, "timeout: failed to reset I2S for %s\n",
 119                         is_playback ? "playback" : "capture");
 120                 return err;
 121         }
 122
 123         /* Restore CIF and I2S control values */
 124         regmap_write(i2s->regmap, cif_reg, cif_ctrl);
 125         regmap_write(i2s->regmap, stream_reg, stream_ctrl);
 126         regmap_write(i2s->regmap, TEGRA210_I2S_CTRL, i2s_ctrl);
 127
 128         return 0;
 129 }
 130
 131 static int tegra210_i2s_init(struct snd_soc_dapm_widget *w,
 132                              struct snd_kcontrol *kcontrol, int event)
 133 {
 134         struct snd_soc_component *compnt = snd_soc_dapm_to_component(w->dapm);
 135         struct device *dev = compnt->dev;
 136         struct tegra210_i2s *i2s = dev_get_drvdata(dev);
 137         unsigned int val, status_reg;
 138         bool is_playback;
 139         int err;
 140
 141         switch (w->reg) {
 142         case TEGRA210_I2S_RX_ENABLE:
 143                 is_playback = true;
 144                 status_reg = TEGRA210_I2S_RX_STATUS;
 145                 break;
 146         case TEGRA210_I2S_TX_ENABLE:
 147                 is_playback = false;
 148                 status_reg = TEGRA210_I2S_TX_STATUS;
 149                 break;
 150         default:
 151                 return -EINVAL;
 152         }
 153
 154         /* Ensure I2S is in disabled state before new session */
 155         err = regmap_read_poll_timeout(i2s->regmap, status_reg, val,
 156                                        !(val & I2S_EN_MASK & I2S_EN),
 157                                        10, 10000);
 158         if (err) {
 159                 dev_err(dev, "timeout: previous I2S %s is still active\n",
 160                         is_playback ? "playback" : "capture");
 161                 return err;
 162         }
 163
 164         return tegra210_i2s_sw_reset(compnt, is_playback);
 165 }
 166
 167 static int tegra210_i2s_runtime_suspend(struct device *dev)
 168 {
 169         struct tegra210_i2s *i2s = dev_get_drvdata(dev);
 170
 171         regcache_cache_only(i2s->regmap, true);
 172         regcache_mark_dirty(i2s->regmap);
 173
 174         clk_disable_unprepare(i2s->clk_i2s);
 175
 176         return 0;
 177 }
 178
 179 static int tegra210_i2s_runtime_resume(struct device *dev)
 180 {
 181         struct tegra210_i2s *i2s = dev_get_drvdata(dev);
 182         int err;
 183
 184         err = clk_prepare_enable(i2s->clk_i2s);
 185         if (err) {
 186                 dev_err(dev, "failed to enable I2S bit clock, err: %d\n", err);
 187                 return err;
 188         }
 189
 190         regcache_cache_only(i2s->regmap, false);
 191         regcache_sync(i2s->regmap);
 192
 193         return 0;
 194 }
 195
 196 static void tegra210_i2s_set_data_offset(struct tegra210_i2s *i2s,
 197                                          unsigned int data_offset)
 198 {
 199         /* Capture path */
 200         regmap_update_bits(i2s->regmap, TEGRA210_I2S_TX_CTRL,
 201                            I2S_CTRL_DATA_OFFSET_MASK,
 202                            data_offset << I2S_DATA_SHIFT);
 203
 204         /* Playback path */
 205         regmap_update_bits(i2s->regmap, TEGRA210_I2S_RX_CTRL,
 206                            I2S_CTRL_DATA_OFFSET_MASK,
 207                            data_offset << I2S_DATA_SHIFT);
 208 }
 209
 210 static int tegra210_i2s_set_fmt(struct snd_soc_dai *dai,
 211                                 unsigned int fmt)
 212 {
 213         struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 214         unsigned int mask, val;
 215
 216         mask = I2S_CTRL_MASTER_EN_MASK;
 217         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 218         case SND_SOC_DAIFMT_CBS_CFS:
 219                 val = 0;
 220                 break;
 221         case SND_SOC_DAIFMT_CBM_CFM:
 222                 val = I2S_CTRL_MASTER_EN;
 223                 break;
 224         default:
 225                 return -EINVAL;
 226         }
 227
 228         mask |= I2S_CTRL_FRAME_FMT_MASK | I2S_CTRL_LRCK_POL_MASK;
 229         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 230         case SND_SOC_DAIFMT_DSP_A:
 231                 val |= I2S_CTRL_FRAME_FMT_FSYNC_MODE;
 232                 val |= I2S_CTRL_LRCK_POL_HIGH;
 233                 tegra210_i2s_set_data_offset(i2s, 1);
 234                 break;
 235         case SND_SOC_DAIFMT_DSP_B:
 236                 val |= I2S_CTRL_FRAME_FMT_FSYNC_MODE;
 237                 val |= I2S_CTRL_LRCK_POL_HIGH;
 238                 tegra210_i2s_set_data_offset(i2s, 0);
 239                 break;
 240         /* I2S mode has data offset of 1 */
 241         case SND_SOC_DAIFMT_I2S:
 242                 val |= I2S_CTRL_FRAME_FMT_LRCK_MODE;
 243                 val |= I2S_CTRL_LRCK_POL_LOW;
 244                 tegra210_i2s_set_data_offset(i2s, 1);
 245                 break;
 246         /*
 247          * For RJ mode data offset is dependent on the sample size
 248          * and the bclk ratio, and so is set when hw_params is called.
 249          */
 250         case SND_SOC_DAIFMT_RIGHT_J:
 251                 val |= I2S_CTRL_FRAME_FMT_LRCK_MODE;
 252                 val |= I2S_CTRL_LRCK_POL_HIGH;
 253                 break;
 254         case SND_SOC_DAIFMT_LEFT_J:
 255                 val |= I2S_CTRL_FRAME_FMT_LRCK_MODE;
 256                 val |= I2S_CTRL_LRCK_POL_HIGH;
 257                 tegra210_i2s_set_data_offset(i2s, 0);
 258                 break;
 259         default:
 260                 return -EINVAL;
 261         }
 262
 263         mask |= I2S_CTRL_EDGE_CTRL_MASK;
 264         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 265         case SND_SOC_DAIFMT_NB_NF:
 266                 val |= I2S_CTRL_EDGE_CTRL_POS_EDGE;
 267                 break;
 268         case SND_SOC_DAIFMT_NB_IF:
 269                 val |= I2S_CTRL_EDGE_CTRL_POS_EDGE;
 270                 val ^= I2S_CTRL_LRCK_POL_MASK;
 271                 break;
 272         case SND_SOC_DAIFMT_IB_NF:
 273                 val |= I2S_CTRL_EDGE_CTRL_NEG_EDGE;
 274                 break;
 275         case SND_SOC_DAIFMT_IB_IF:
 276                 val |= I2S_CTRL_EDGE_CTRL_NEG_EDGE;
 277                 val ^= I2S_CTRL_LRCK_POL_MASK;
 278                 break;
 279         default:
 280                 return -EINVAL;
 281         }
 282
 283         regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, mask, val);
 284
 285         i2s->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 286
 287         return 0;
 288 }
 289
 290 static int tegra210_i2s_set_tdm_slot(struct snd_soc_dai *dai,
 291                                      unsigned int tx_mask, unsigned int rx_mask,
 292                                      int slots, int slot_width)
 293 {
 294         struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 295
 296         /* Copy the required tx and rx mask */
 297         i2s->tx_mask = (tx_mask > DEFAULT_I2S_SLOT_MASK) ?
 298                        DEFAULT_I2S_SLOT_MASK : tx_mask;
 299         i2s->rx_mask = (rx_mask > DEFAULT_I2S_SLOT_MASK) ?
 300                        DEFAULT_I2S_SLOT_MASK : rx_mask;
 301
 302         return 0;
 303 }
 304
 305 static int tegra210_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
 306                                            unsigned int ratio)
 307 {
 308         struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 309
 310         i2s->bclk_ratio = ratio;
 311
 312         return 0;
 313 }
 314
 315 static int tegra210_i2s_get_control(struct snd_kcontrol *kcontrol,
 316                                     struct snd_ctl_elem_value *ucontrol)
 317 {
 318         struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
 319         struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
 320         long *uctl_val = &ucontrol->value.integer.value[0];
 321
 322         if (strstr(kcontrol->id.name, "Loopback"))
 323                 *uctl_val = i2s->loopback;
 324         else if (strstr(kcontrol->id.name, "FSYNC Width"))
 325                 *uctl_val = i2s->fsync_width;
 326         else if (strstr(kcontrol->id.name, "Capture Stereo To Mono"))
 327                 *uctl_val = i2s->stereo_to_mono[I2S_TX_PATH];
 328         else if (strstr(kcontrol->id.name, "Capture Mono To Stereo"))
 329                 *uctl_val = i2s->mono_to_stereo[I2S_TX_PATH];
 330         else if (strstr(kcontrol->id.name, "Playback Stereo To Mono"))
 331                 *uctl_val = i2s->stereo_to_mono[I2S_RX_PATH];
 332         else if (strstr(kcontrol->id.name, "Playback Mono To Stereo"))
 333                 *uctl_val = i2s->mono_to_stereo[I2S_RX_PATH];
 334         else if (strstr(kcontrol->id.name, "Playback FIFO Threshold"))
 335                 *uctl_val = i2s->rx_fifo_th;
 336         else if (strstr(kcontrol->id.name, "BCLK Ratio"))
 337                 *uctl_val = i2s->bclk_ratio;
 338
 339         return 0;
 340 }
 341
 342 static int tegra210_i2s_put_control(struct snd_kcontrol *kcontrol,
 343                                     struct snd_ctl_elem_value *ucontrol)
 344 {
 345         struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
 346         struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
 347         int value = ucontrol->value.integer.value[0];
 348
 349         if (strstr(kcontrol->id.name, "Loopback")) {
 350                 i2s->loopback = value;
 351
 352                 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL,
 353                                    I2S_CTRL_LPBK_MASK,
 354                                    i2s->loopback << I2S_CTRL_LPBK_SHIFT);
 355
 356         } else if (strstr(kcontrol->id.name, "FSYNC Width")) {
 357                 /*
 358                  * Frame sync width is used only for FSYNC modes and not
 359                  * applicable for LRCK modes. Reset value for this field is "0",
 360                  * which means the width is one bit clock wide.
 361                  * The width requirement may depend on the codec and in such
 362                  * cases mixer control is used to update custom values. A value
 363                  * of "N" here means, width is "N + 1" bit clock wide.
 364                  */
 365                 i2s->fsync_width = value;
 366
 367                 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL,
 368                                    I2S_CTRL_FSYNC_WIDTH_MASK,
 369                                    i2s->fsync_width << I2S_FSYNC_WIDTH_SHIFT);
 370
 371         } else if (strstr(kcontrol->id.name, "Capture Stereo To Mono")) {
 372                 i2s->stereo_to_mono[I2S_TX_PATH] = value;
 373         } else if (strstr(kcontrol->id.name, "Capture Mono To Stereo")) {
 374                 i2s->mono_to_stereo[I2S_TX_PATH] = value;
 375         } else if (strstr(kcontrol->id.name, "Playback Stereo To Mono")) {
 376                 i2s->stereo_to_mono[I2S_RX_PATH] = value;
 377         } else if (strstr(kcontrol->id.name, "Playback Mono To Stereo")) {
 378                 i2s->mono_to_stereo[I2S_RX_PATH] = value;
 379         } else if (strstr(kcontrol->id.name, "Playback FIFO Threshold")) {
 380                 i2s->rx_fifo_th = value;
 381         } else if (strstr(kcontrol->id.name, "BCLK Ratio")) {
 382                 i2s->bclk_ratio = value;
 383         }
 384
 385         return 0;
 386 }
 387
 388 static int tegra210_i2s_set_timing_params(struct device *dev,
 389                                           unsigned int sample_size,
 390                                           unsigned int srate,
 391                                           unsigned int channels)
 392 {
 393         struct tegra210_i2s *i2s = dev_get_drvdata(dev);
 394         unsigned int val, bit_count, bclk_rate, num_bclk = sample_size;
 395         int err;
 396
 397         if (i2s->bclk_ratio)
 398                 num_bclk *= i2s->bclk_ratio;
 399
 400         if (i2s->dai_fmt == SND_SOC_DAIFMT_RIGHT_J)
 401                 tegra210_i2s_set_data_offset(i2s, num_bclk - sample_size);
 402
 403         /* I2S bit clock rate */
 404         bclk_rate = srate * channels * num_bclk;
 405
 406         err = tegra210_i2s_set_clock_rate(dev, bclk_rate);
 407         if (err) {
 408                 dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n",
 409                         bclk_rate, err);
 410                 return err;
 411         }
 412
 413         regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val);
 414
 415         /*
 416          * For LRCK mode, channel bit count depends on number of bit clocks
 417          * on the left channel, where as for FSYNC mode bit count depends on
 418          * the number of bit clocks in both left and right channels for DSP
 419          * mode or the number of bit clocks in one TDM frame.
 420          *
 421          */
 422         switch (val & I2S_CTRL_FRAME_FMT_MASK) {
 423         case I2S_CTRL_FRAME_FMT_LRCK_MODE:
 424                 bit_count = (bclk_rate / (srate * 2)) - 1;
 425                 break;
 426         case I2S_CTRL_FRAME_FMT_FSYNC_MODE:
 427                 bit_count = (bclk_rate / srate) - 1;
 428
 429                 tegra210_i2s_set_slot_ctrl(i2s->regmap, channels,
 430                                            i2s->tx_mask, i2s->rx_mask);
 431                 break;
 432         default:
 433                 dev_err(dev, "invalid I2S frame format\n");
 434                 return -EINVAL;
 435         }
 436
 437         if (bit_count > I2S_TIMING_CH_BIT_CNT_MASK) {
 438                 dev_err(dev, "invalid I2S channel bit count %u\n", bit_count);
 439                 return -EINVAL;
 440         }
 441
 442         regmap_write(i2s->regmap, TEGRA210_I2S_TIMING,
 443                      bit_count << I2S_TIMING_CH_BIT_CNT_SHIFT);
 444
 445         return 0;
 446 }
 447
 448 static int tegra210_i2s_hw_params(struct snd_pcm_substream *substream,
 449                                   struct snd_pcm_hw_params *params,
 450                                   struct snd_soc_dai *dai)
 451 {
 452         struct device *dev = dai->dev;
 453         struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 454         unsigned int sample_size, channels, srate, val, reg, path;
 455         struct tegra_cif_conf cif_conf;
 456
 457         memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
 458
 459         channels = params_channels(params);
 460         if (channels < 1) {
 461                 dev_err(dev, "invalid I2S %d channel configuration\n",
 462                         channels);
 463                 return -EINVAL;
 464         }
 465
 466         cif_conf.audio_ch = channels;
 467         cif_conf.client_ch = channels;
 468
 469         switch (params_format(params)) {
 470         case SNDRV_PCM_FORMAT_S8:
 471                 val = I2S_BITS_8;
 472                 sample_size = 8;
 473                 cif_conf.audio_bits = TEGRA_ACIF_BITS_8;
 474                 cif_conf.client_bits = TEGRA_ACIF_BITS_8;
 475                 break;
 476         case SNDRV_PCM_FORMAT_S16_LE:
 477                 val = I2S_BITS_16;
 478                 sample_size = 16;
 479                 cif_conf.audio_bits = TEGRA_ACIF_BITS_16;
 480                 cif_conf.client_bits = TEGRA_ACIF_BITS_16;
 481                 break;
 482         case SNDRV_PCM_FORMAT_S32_LE:
 483                 val = I2S_BITS_32;
 484                 sample_size = 32;
 485                 cif_conf.audio_bits = TEGRA_ACIF_BITS_32;
 486                 cif_conf.client_bits = TEGRA_ACIF_BITS_32;
 487                 break;
 488         default:
 489                 dev_err(dev, "unsupported format!\n");
 490                 return -EOPNOTSUPP;
 491         }
 492
 493         /* Program sample size */
 494         regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL,
 495                            I2S_CTRL_BIT_SIZE_MASK, val);
 496
 497         srate = params_rate(params);
 498
 499         /* For playback I2S RX-CIF and for capture TX-CIF is used */
 500         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 501                 path = I2S_RX_PATH;
 502         else
 503                 path = I2S_TX_PATH;
 504
 505         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 506                 unsigned int max_th;
 507
 508                 /* FIFO threshold in terms of frames */
 509                 max_th = (I2S_RX_FIFO_DEPTH / cif_conf.audio_ch) - 1;
 510
 511                 if (i2s->rx_fifo_th > max_th)
 512                         i2s->rx_fifo_th = max_th;
 513
 514                 cif_conf.threshold = i2s->rx_fifo_th;
 515
 516                 reg = TEGRA210_I2S_RX_CIF_CTRL;
 517         } else {
 518                 reg = TEGRA210_I2S_TX_CIF_CTRL;
 519         }
 520
 521         cif_conf.mono_conv = i2s->mono_to_stereo[path];
 522         cif_conf.stereo_conv = i2s->stereo_to_mono[path];
 523
 524         tegra_set_cif(i2s->regmap, reg, &cif_conf);
 525
 526         return tegra210_i2s_set_timing_params(dev, sample_size, srate,
 527                                               cif_conf.client_ch);
 528 }
 529
 530 static const struct snd_soc_dai_ops tegra210_i2s_dai_ops = {
 531         .set_fmt        = tegra210_i2s_set_fmt,
 532         .hw_params      = tegra210_i2s_hw_params,
 533         .set_bclk_ratio = tegra210_i2s_set_dai_bclk_ratio,
 534         .set_tdm_slot   = tegra210_i2s_set_tdm_slot,
 535 };
 536
 537 static struct snd_soc_dai_driver tegra210_i2s_dais[] = {
 538         {
 539                 .name = "I2S-CIF",
 540                 .playback = {
 541                         .stream_name = "CIF-Playback",
 542                         .channels_min = 1,
 543                         .channels_max = 16,
 544                         .rates = SNDRV_PCM_RATE_8000_192000,
 545                         .formats = SNDRV_PCM_FMTBIT_S8 |
 546                                 SNDRV_PCM_FMTBIT_S16_LE |
 547                                 SNDRV_PCM_FMTBIT_S32_LE,
 548                 },
 549                 .capture = {
 550                         .stream_name = "CIF-Capture",
 551                         .channels_min = 1,
 552                         .channels_max = 16,
 553                         .rates = SNDRV_PCM_RATE_8000_192000,
 554                         .formats = SNDRV_PCM_FMTBIT_S8 |
 555                                 SNDRV_PCM_FMTBIT_S16_LE |
 556                                 SNDRV_PCM_FMTBIT_S32_LE,
 557                 },
 558         },
 559         {
 560                 .name = "I2S-DAP",
 561                 .playback = {
 562                         .stream_name = "DAP-Playback",
 563                         .channels_min = 1,
 564                         .channels_max = 16,
 565                         .rates = SNDRV_PCM_RATE_8000_192000,
 566                         .formats = SNDRV_PCM_FMTBIT_S8 |
 567                                 SNDRV_PCM_FMTBIT_S16_LE |
 568                                 SNDRV_PCM_FMTBIT_S32_LE,
 569                 },
 570                 .capture = {
 571                         .stream_name = "DAP-Capture",
 572                         .channels_min = 1,
 573                         .channels_max = 16,
 574                         .rates = SNDRV_PCM_RATE_8000_192000,
 575                         .formats = SNDRV_PCM_FMTBIT_S8 |
 576                                 SNDRV_PCM_FMTBIT_S16_LE |
 577                                 SNDRV_PCM_FMTBIT_S32_LE,
 578                 },
 579                 .ops = &tegra210_i2s_dai_ops,
 580                 .symmetric_rates = 1,
 581         },
 582 };
 583
 584 static const char * const tegra210_i2s_stereo_conv_text[] = {
 585         "CH0", "CH1", "AVG",
 586 };
 587
 588 static const char * const tegra210_i2s_mono_conv_text[] = {
 589         "Zero", "Copy",
 590 };
 591
 592 static const struct soc_enum tegra210_i2s_mono_conv_enum =
 593         SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_i2s_mono_conv_text),
 594                         tegra210_i2s_mono_conv_text);
 595
 596 static const struct soc_enum tegra210_i2s_stereo_conv_enum =
 597         SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_i2s_stereo_conv_text),
 598                         tegra210_i2s_stereo_conv_text);
 599
 600 static const struct snd_kcontrol_new tegra210_i2s_controls[] = {
 601         SOC_SINGLE_EXT("Loopback", 0, 0, 1, 0, tegra210_i2s_get_control,
 602                        tegra210_i2s_put_control),
 603         SOC_SINGLE_EXT("FSYNC Width", 0, 0, 255, 0, tegra210_i2s_get_control,
 604                        tegra210_i2s_put_control),
 605         SOC_ENUM_EXT("Capture Stereo To Mono", tegra210_i2s_stereo_conv_enum,
 606                      tegra210_i2s_get_control, tegra210_i2s_put_control),
 607         SOC_ENUM_EXT("Capture Mono To Stereo", tegra210_i2s_mono_conv_enum,
 608                      tegra210_i2s_get_control, tegra210_i2s_put_control),
 609         SOC_ENUM_EXT("Playback Stereo To Mono", tegra210_i2s_stereo_conv_enum,
 610                      tegra210_i2s_get_control, tegra210_i2s_put_control),
 611         SOC_ENUM_EXT("Playback Mono To Stereo", tegra210_i2s_mono_conv_enum,
 612                      tegra210_i2s_get_control, tegra210_i2s_put_control),
 613         SOC_SINGLE_EXT("Playback FIFO Threshold", 0, 0, I2S_RX_FIFO_DEPTH - 1,
 614                        0, tegra210_i2s_get_control, tegra210_i2s_put_control),
 615         SOC_SINGLE_EXT("BCLK Ratio", 0, 0, INT_MAX, 0, tegra210_i2s_get_control,
 616                        tegra210_i2s_put_control),
 617 };
 618
 619 static const struct snd_soc_dapm_widget tegra210_i2s_widgets[] = {
 620         SND_SOC_DAPM_AIF_IN_E("RX", NULL, 0, TEGRA210_I2S_RX_ENABLE,
 621                               0, 0, tegra210_i2s_init, SND_SOC_DAPM_PRE_PMU),
 622         SND_SOC_DAPM_AIF_OUT_E("TX", NULL, 0, TEGRA210_I2S_TX_ENABLE,
 623                                0, 0, tegra210_i2s_init, SND_SOC_DAPM_PRE_PMU),
 624         SND_SOC_DAPM_MIC("MIC", NULL),
 625         SND_SOC_DAPM_SPK("SPK", NULL),
 626 };
 627
 628 static const struct snd_soc_dapm_route tegra210_i2s_routes[] = {
 629         /* Playback route from XBAR */
 630         { "XBAR-Playback",      NULL,   "XBAR-TX" },
 631         { "CIF-Playback",       NULL,   "XBAR-Playback" },
 632         { "RX",                 NULL,   "CIF-Playback" },
 633         { "DAP-Playback",       NULL,   "RX" },
 634         { "SPK",                NULL,   "DAP-Playback" },
 635         /* Capture route to XBAR */
 636         { "XBAR-RX",            NULL,   "XBAR-Capture" },
 637         { "XBAR-Capture",       NULL,   "CIF-Capture" },
 638         { "CIF-Capture",        NULL,   "TX" },
 639         { "TX",                 NULL,   "DAP-Capture" },
 640         { "DAP-Capture",        NULL,   "MIC" },
 641 };
 642
 643 static const struct snd_soc_component_driver tegra210_i2s_cmpnt = {
 644         .dapm_widgets           = tegra210_i2s_widgets,
 645         .num_dapm_widgets       = ARRAY_SIZE(tegra210_i2s_widgets),
 646         .dapm_routes            = tegra210_i2s_routes,
 647         .num_dapm_routes        = ARRAY_SIZE(tegra210_i2s_routes),
 648         .controls               = tegra210_i2s_controls,
 649         .num_controls           = ARRAY_SIZE(tegra210_i2s_controls),
 650         .non_legacy_dai_naming  = 1,
 651 };
 652
 653 static bool tegra210_i2s_wr_reg(struct device *dev, unsigned int reg)
 654 {
 655         switch (reg) {
 656         case TEGRA210_I2S_RX_ENABLE ... TEGRA210_I2S_RX_SOFT_RESET:
 657         case TEGRA210_I2S_RX_INT_MASK ... TEGRA210_I2S_RX_CLK_TRIM:
 658         case TEGRA210_I2S_TX_ENABLE ... TEGRA210_I2S_TX_SOFT_RESET:
 659         case TEGRA210_I2S_TX_INT_MASK ... TEGRA210_I2S_TX_CLK_TRIM:
 660         case TEGRA210_I2S_ENABLE ... TEGRA210_I2S_CG:
 661         case TEGRA210_I2S_CTRL ... TEGRA210_I2S_CYA:
 662                 return true;
 663         default:
 664                 return false;
 665         };
 666 }
 667
 668 static bool tegra210_i2s_rd_reg(struct device *dev, unsigned int reg)
 669 {
 670         if (tegra210_i2s_wr_reg(dev, reg))
 671                 return true;
 672
 673         switch (reg) {
 674         case TEGRA210_I2S_RX_STATUS:
 675         case TEGRA210_I2S_RX_INT_STATUS:
 676         case TEGRA210_I2S_RX_CIF_FIFO_STATUS:
 677         case TEGRA210_I2S_TX_STATUS:
 678         case TEGRA210_I2S_TX_INT_STATUS:
 679         case TEGRA210_I2S_TX_CIF_FIFO_STATUS:
 680         case TEGRA210_I2S_STATUS:
 681         case TEGRA210_I2S_INT_STATUS:
 682                 return true;
 683         default:
 684                 return false;
 685         };
 686 }
 687
 688 static bool tegra210_i2s_volatile_reg(struct device *dev, unsigned int reg)
 689 {
 690         switch (reg) {
 691         case TEGRA210_I2S_RX_STATUS:
 692         case TEGRA210_I2S_RX_INT_STATUS:
 693         case TEGRA210_I2S_RX_CIF_FIFO_STATUS:
 694         case TEGRA210_I2S_TX_STATUS:
 695         case TEGRA210_I2S_TX_INT_STATUS:
 696         case TEGRA210_I2S_TX_CIF_FIFO_STATUS:
 697         case TEGRA210_I2S_STATUS:
 698         case TEGRA210_I2S_INT_STATUS:
 699         case TEGRA210_I2S_RX_SOFT_RESET:
 700         case TEGRA210_I2S_TX_SOFT_RESET:
 701                 return true;
 702         default:
 703                 return false;
 704         };
 705 }
 706
 707 static const struct regmap_config tegra210_i2s_regmap_config = {
 708         .reg_bits               = 32,
 709         .reg_stride             = 4,
 710         .val_bits               = 32,
 711         .max_register           = TEGRA210_I2S_CYA,
 712         .writeable_reg          = tegra210_i2s_wr_reg,
 713         .readable_reg           = tegra210_i2s_rd_reg,
 714         .volatile_reg           = tegra210_i2s_volatile_reg,
 715         .reg_defaults           = tegra210_i2s_reg_defaults,
 716         .num_reg_defaults       = ARRAY_SIZE(tegra210_i2s_reg_defaults),
 717         .cache_type             = REGCACHE_FLAT,
 718 };
 719
 720 static int tegra210_i2s_probe(struct platform_device *pdev)
 721 {
 722         struct device *dev = &pdev->dev;
 723         struct tegra210_i2s *i2s;
 724         void __iomem *regs;
 725         int err;
 726
 727         i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
 728         if (!i2s)
 729                 return -ENOMEM;
 730
 731         i2s->rx_fifo_th = DEFAULT_I2S_RX_FIFO_THRESHOLD;
 732         i2s->tx_mask = DEFAULT_I2S_SLOT_MASK;
 733         i2s->rx_mask = DEFAULT_I2S_SLOT_MASK;
 734         i2s->loopback = false;
 735
 736         dev_set_drvdata(dev, i2s);
 737
 738         i2s->clk_i2s = devm_clk_get(dev, "i2s");
 739         if (IS_ERR(i2s->clk_i2s)) {
 740                 dev_err(dev, "can't retrieve I2S bit clock\n");
 741                 return PTR_ERR(i2s->clk_i2s);
 742         }
 743
 744         /*
 745          * Not an error, as this clock is needed only when some other I/O
 746          * requires input clock from current I2S instance, which is
 747          * configurable from DT.
 748          */
 749         i2s->clk_sync_input = devm_clk_get(dev, "sync_input");
 750         if (IS_ERR(i2s->clk_sync_input))
 751                 dev_dbg(dev, "can't retrieve I2S sync input clock\n");
 752
 753         regs = devm_platform_ioremap_resource(pdev, 0);
 754         if (IS_ERR(regs))
 755                 return PTR_ERR(regs);
 756
 757         i2s->regmap = devm_regmap_init_mmio(dev, regs,
 758                                             &tegra210_i2s_regmap_config);
 759         if (IS_ERR(i2s->regmap)) {
 760                 dev_err(dev, "regmap init failed\n");
 761                 return PTR_ERR(i2s->regmap);
 762         }
 763
 764         regcache_cache_only(i2s->regmap, true);
 765
 766         err = devm_snd_soc_register_component(dev, &tegra210_i2s_cmpnt,
 767                                               tegra210_i2s_dais,
 768                                               ARRAY_SIZE(tegra210_i2s_dais));
 769         if (err) {
 770                 dev_err(dev, "can't register I2S component, err: %d\n", err);
 771                 return err;
 772         }
 773
 774         pm_runtime_enable(dev);
 775
 776         return 0;
 777 }
 778
 779 static int tegra210_i2s_remove(struct platform_device *pdev)
 780 {
 781         pm_runtime_disable(&pdev->dev);
 782
 783         return 0;
 784 }
 785
 786 static const struct dev_pm_ops tegra210_i2s_pm_ops = {
 787         SET_RUNTIME_PM_OPS(tegra210_i2s_runtime_suspend,
 788                            tegra210_i2s_runtime_resume, NULL)
 789         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 790                                 pm_runtime_force_resume)
 791 };
 792
 793 static const struct of_device_id tegra210_i2s_of_match[] = {
 794         { .compatible = "nvidia,tegra210-i2s" },
 795         {},
 796 };
 797 MODULE_DEVICE_TABLE(of, tegra210_i2s_of_match);
 798
 799 static struct platform_driver tegra210_i2s_driver = {
 800         .driver = {
 801                 .name = "tegra210-i2s",
 802                 .of_match_table = tegra210_i2s_of_match,
 803                 .pm = &tegra210_i2s_pm_ops,
 804         },
 805         .probe = tegra210_i2s_probe,
 806         .remove = tegra210_i2s_remove,
 807 };
 808 module_platform_driver(tegra210_i2s_driver)
 809
 810 MODULE_AUTHOR("Songhee Baek <sbaek@nvidia.com>");
 811 MODULE_DESCRIPTION("Tegra210 ASoC I2S driver");
 812 MODULE_LICENSE("GPL v2");